Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	118749527	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118749527	0	0
T1	1435	718	0	0
T2	5283	0	0	0
T3	2905	578	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	0	0	0
T47	1003	0	0	0
T48	5818	262	0	0
T49	0	333	0	0
T53	881	0	0	0
T54	1049	0	0	0
T72	0	461	0	0
T73	0	579	0	0
T74	0	553	0	0
T81	0	142	0	0
T82	0	64	0	0
T83	0	157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	215372999	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	215372999	0	0
T1	1435	359	0	0
T2	5283	0	0	0
T3	2905	1175	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	0	0	0
T47	1003	0	0	0
T48	5818	251	0	0
T49	0	324	0	0
T53	881	0	0	0
T54	1049	0	0	0
T72	0	247	0	0
T73	0	1949	0	0
T74	0	2057	0	0
T81	0	304	0	0
T82	0	61	0	0
T83	0	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	321588528	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	321588528	0	0
T1	1435	3	0	0
T2	5283	844	0	0
T3	2905	3	0	0
T44	2789	1471	0	0
T45	5086	2596	0	0
T46	155765	14850	0	0
T47	1003	40	0	0
T48	5818	449	0	0
T53	881	22	0	0
T54	1049	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	593216971	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	593216971	0	0
T1	1435	3	0	0
T2	5283	689	0	0
T3	2905	26	0	0
T44	2789	754	0	0
T45	5086	1334	0	0
T46	155765	66518	0	0
T47	1003	40	0	0
T48	5818	426	0	0
T53	881	22	0	0
T54	1049	145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1435	1345	0	0
T2	5283	5023	0	0
T3	2905	2821	0	0
T44	2789	2517	0	0
T45	5086	4296	0	0
T46	155765	155696	0	0
T47	1003	905	0	0
T48	5818	5732	0	0
T53	881	786	0	0
T54	1049	974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0