Unified Coverage Report :: Module :: keccak_2share

Module : keccak_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	100.00	75.00			50.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p	81.25	100.00	75.00			50.00	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	100.00	75.00			50.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.25	100.00	75.00			50.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.11	71.25	100.00		40.00	79.31	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
TOTAL		73	73	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	0	0
CONT_ASSIGN	82	0	0
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
ROUTINE	440	0	0
ROUTINE	440	5	5	100.00
ROUTINE	453	0	0
ROUTINE	453	5	5	100.00
ROUTINE	486	0	0
ROUTINE	486	10	10	100.00
ROUTINE	555	0	0
ROUTINE	555	4	4	100.00
ROUTINE	569	0	0
ROUTINE	569	3	3	100.00
ROUTINE	624	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
77	1	1
78	1	1
79	1	1
80	1	1
81		unreachable
82		unreachable
89	1	1
90	1	1
105	1	1
106	1	1
107	1	1
132	1	1
136	1	1
143	1	1
150	1	1
373	1	1
374	1	1
391	1	1
392	1	1
399	1	1
401	24	24
421	1	1
440	1	1
441	1	1
442	1	1
443	1	1
447	1	1
453	1	1
454	1	1
455	1	1
456	1	1
460	1	1
486	1	1
487	1	1
489	1	1
490	1	1
492	1	1
493	1	1
496	1	1
497	1	1
498	1	1
501	1	1
555	1	1
556	1	1
557	1	1
560	1	1
569	1	1
570	1	1
572	1	1
624	1	1
625	1	1
627	1	1

---

Cond Coverage for Module : keccak_2share

	Total	Covered	Percent
Conditions	8	6	75.00
Logical	8	6	75.00
Non-Logical	0	0
Event	0	0

 LINE       492
 EXPRESSION ((z == 0) ? ((W - 1)) : ((z - 1)))
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       492
 SUB-EXPRESSION (z == 0)
                ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       493
 EXPRESSION (c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z])
             ----------1----------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Module : keccak_2share

	Line No.	Total	Covered	Percent
Branches		2	1	50.00
TERNARY	492	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	492	((z == 0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

---

Assert Coverage for Module : keccak_2share

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidL_A	1060	1060	0	0
ValidRound_A	1060	1060	0	0
ValidW_A	1060	1060	0	0
ValidWidth_A	1060	1060	0	0

ValidL_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

ValidRound_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

ValidW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0