Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1839054	0	0
entropy_period_rd_A	2147483647	3300	0	0
intr_enable_rd_A	2147483647	3890	0	0
prefix_0_rd_A	2147483647	3292	0	0
prefix_10_rd_A	2147483647	3328	0	0
prefix_1_rd_A	2147483647	3377	0	0
prefix_2_rd_A	2147483647	3250	0	0
prefix_3_rd_A	2147483647	3439	0	0
prefix_4_rd_A	2147483647	3103	0	0
prefix_5_rd_A	2147483647	3351	0	0
prefix_6_rd_A	2147483647	3291	0	0
prefix_7_rd_A	2147483647	3221	0	0
prefix_8_rd_A	2147483647	3284	0	0
prefix_9_rd_A	2147483647	3362	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839054	0	0
T45	5086	0	0	0
T48	5818	155	0	0
T49	8256	160	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T54	1049	0	0	0
T72	1784	10	0	0
T73	0	134	0	0
T74	0	166	0	0
T75	0	185	0	0
T78	0	126	0	0
T79	5578	0	0	0
T80	5081	0	0	0
T81	3381	0	0	0
T100	0	4	0	0
T101	0	3	0	0
T114	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3300	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	215	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T75	0	8	0	0
T76	0	7	0	0
T77	0	1	0	0
T81	0	11	0	0
T92	0	4	0	0
T107	0	15	0	0
T115	0	1	0	0
T116	0	2	0	0
T117	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3890	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	475	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	16	0	0
T77	0	9	0	0
T81	0	4	0	0
T107	0	11	0	0
T115	0	8	0	0
T118	0	20	0	0
T119	0	7	0	0
T120	0	23	0	0
T121	0	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3292	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	459	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T76	0	1	0	0
T77	0	3	0	0
T81	0	10	0	0
T92	0	6	0	0
T107	0	9	0	0
T115	0	6	0	0
T116	0	57	0	0
T117	0	4	0	0
T122	0	29	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3328	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	451	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T76	0	2	0	0
T77	0	3	0	0
T81	0	6	0	0
T84	0	24	0	0
T92	0	2	0	0
T107	0	8	0	0
T115	0	8	0	0
T116	0	19	0	0
T122	0	24	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3377	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	459	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T73	0	3	0	0
T76	0	9	0	0
T77	0	2	0	0
T81	0	7	0	0
T92	0	13	0	0
T107	0	4	0	0
T115	0	3	0	0
T116	0	16	0	0
T117	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3250	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	487	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T76	0	2	0	0
T77	0	1	0	0
T81	0	9	0	0
T84	0	14	0	0
T92	0	4	0	0
T107	0	5	0	0
T115	0	1	0	0
T116	0	23	0	0
T122	0	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3439	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	441	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T76	0	4	0	0
T77	0	9	0	0
T81	0	14	0	0
T84	0	6	0	0
T92	0	6	0	0
T107	0	11	0	0
T115	0	5	0	0
T116	0	44	0	0
T122	0	33	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3103	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	438	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T77	0	8	0	0
T81	0	6	0	0
T84	0	25	0	0
T92	0	7	0	0
T107	0	9	0	0
T115	0	1	0	0
T116	0	10	0	0
T117	0	2	0	0
T122	0	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3351	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	485	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T76	0	2	0	0
T77	0	9	0	0
T81	0	2	0	0
T92	0	2	0	0
T107	0	8	0	0
T115	0	2	0	0
T116	0	4	0	0
T117	0	2	0	0
T122	0	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3291	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	463	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T76	0	9	0	0
T77	0	3	0	0
T81	0	8	0	0
T92	0	10	0	0
T107	0	6	0	0
T115	0	5	0	0
T116	0	27	0	0
T117	0	13	0	0
T122	0	36	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3221	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	461	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T75	0	5	0	0
T76	0	2	0	0
T77	0	6	0	0
T81	0	6	0	0
T92	0	4	0	0
T107	0	10	0	0
T115	0	5	0	0
T116	0	6	0	0
T122	0	9	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3284	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	426	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T77	0	8	0	0
T81	0	11	0	0
T84	0	20	0	0
T85	0	127	0	0
T107	0	8	0	0
T115	0	6	0	0
T116	0	23	0	0
T117	0	6	0	0
T122	0	14	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3362	0	0
T44	2789	0	0	0
T45	5086	0	0	0
T46	155765	475	0	0
T47	1003	0	0	0
T48	5818	0	0	0
T49	8256	0	0	0
T51	1170	0	0	0
T52	1316	0	0	0
T53	881	0	0	0
T54	1049	0	0	0
T77	0	6	0	0
T81	0	7	0	0
T84	0	19	0	0
T92	0	3	0	0
T107	0	3	0	0
T115	0	3	0	0
T116	0	17	0	0
T117	0	3	0	0
T122	0	23	0	0