Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255464142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

205060817

1

T1

18

T2

10484

T3

1238

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	242071225	1			T1	20		T2	7221		T3	641
values[0x0]	104734627	1			T1	13		T2	3664		T3	299
values[0x1]	113719107	1			T1	7		T2	3800		T3	298

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198768811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

261756148

1

T1

20

T2

11286

T3

1238

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1433132	1			T3	8		T48	3		T49	1
valid_sources[0x01]	1469255	1			T2	128		T3	7		T48	2
valid_sources[0x02]	1435383	1			T48	12		T49	1		T50	6
valid_sources[0x03]	1451297	1			T2	129		T48	5		T50	1
valid_sources[0x04]	1436386	1			T2	384		T48	4		T50	3
valid_sources[0x05]	1436941	1			T3	39		T48	3		T49	1
valid_sources[0x06]	3867520	1			T2	128		T48	12		T50	2
valid_sources[0x07]	3836792	1			T3	5		T48	4		T49	1
valid_sources[0x08]	2276771	1			T2	128		T48	6		T50	15
valid_sources[0x09]	1439717	1			T2	256		T48	12		T49	3
valid_sources[0x0a]	1432918	1			T2	128		T3	11		T48	8
valid_sources[0x0b]	2033803	1			T48	6		T50	3		T57	1
valid_sources[0x0c]	4604990	1			T48	4		T50	6		T81	54
valid_sources[0x0d]	1432556	1			T48	11		T50	2		T81	51
valid_sources[0x0e]	1832352	1			T48	4		T49	1		T50	3
valid_sources[0x0f]	1448688	1			T48	13		T49	2		T81	53
valid_sources[0x10]	1435417	1			T48	3		T49	1		T81	73
valid_sources[0x11]	1744252	1			T3	2		T48	6		T49	1
valid_sources[0x12]	1567325	1			T2	256		T50	6		T81	57
valid_sources[0x13]	1434369	1			T48	6		T49	1		T50	9
valid_sources[0x14]	1511810	1			T3	16		T48	3		T50	3
valid_sources[0x15]	1467650	1			T3	10		T48	1		T49	1
valid_sources[0x16]	1431781	1			T48	4		T50	3		T81	58
valid_sources[0x17]	1430760	1			T2	128		T3	35		T48	9
valid_sources[0x18]	1453454	1			T2	384		T3	23		T48	11
valid_sources[0x19]	1442650	1			T2	128		T48	2		T49	1
valid_sources[0x1a]	1444192	1			T48	7		T50	5		T81	66
valid_sources[0x1b]	6279288	1			T2	128		T3	15		T48	5
valid_sources[0x1c]	1435708	1			T3	11		T48	1		T50	7
valid_sources[0x1d]	2071059	1			T3	66		T48	2		T49	2
valid_sources[0x1e]	1916543	1			T48	12		T49	1		T50	8
valid_sources[0x1f]	1430844	1			T48	4		T50	4		T81	71
valid_sources[0x20]	3218862	1			T48	7		T49	1		T50	9
valid_sources[0x21]	1898890	1			T48	10		T50	6		T81	68
valid_sources[0x22]	2762973	1			T48	4		T50	4		T81	57
valid_sources[0x23]	1435603	1			T2	128		T48	7		T49	1
valid_sources[0x24]	1438493	1			T3	18		T48	4		T49	1
valid_sources[0x25]	1437361	1			T3	3		T48	4		T49	1
valid_sources[0x26]	1436953	1			T48	4		T50	9		T79	41
valid_sources[0x27]	3503645	1			T48	1		T50	4		T57	1
valid_sources[0x28]	1512993	1			T48	1		T49	2		T50	11
valid_sources[0x29]	1452597	1			T48	3		T49	1		T50	4
valid_sources[0x2a]	2168670	1			T2	128		T3	11		T48	6
valid_sources[0x2b]	1463171	1			T48	4		T49	1		T50	3
valid_sources[0x2c]	1518713	1			T48	13		T50	6		T57	1
valid_sources[0x2d]	1471384	1			T2	128		T48	4		T49	1
valid_sources[0x2e]	2314986	1			T3	15		T48	5		T49	1
valid_sources[0x2f]	1441936	1			T48	6		T50	2		T57	1
valid_sources[0x30]	2837057	1			T3	4		T50	1		T81	59
valid_sources[0x31]	1503341	1			T48	8		T49	2		T50	4
valid_sources[0x32]	1438287	1			T2	128		T48	11		T49	1
valid_sources[0x33]	2339931	1			T3	13		T48	10		T49	1
valid_sources[0x34]	1445717	1			T3	4		T48	3		T50	2
valid_sources[0x35]	1466770	1			T2	128		T3	17		T48	6
valid_sources[0x36]	2296112	1			T48	15		T49	1		T50	3
valid_sources[0x37]	1451929	1			T48	7		T49	1		T50	1
valid_sources[0x38]	1443426	1			T2	128		T3	18		T48	2
valid_sources[0x39]	1438640	1			T3	6		T48	13		T49	2
valid_sources[0x3a]	1460320	1			T48	5		T50	3		T81	52
valid_sources[0x3b]	1433171	1			T2	256		T3	19		T48	5
valid_sources[0x3c]	1895259	1			T2	128		T48	6		T50	2
valid_sources[0x3d]	1773954	1			T3	8		T48	8		T49	1
valid_sources[0x3e]	1430785	1			T2	256		T3	7		T48	3
valid_sources[0x3f]	1425170	1			T48	1		T50	5		T57	2
valid_sources[0x40]	1434600	1			T48	15		T50	3		T81	62
valid_sources[0x41]	2106812	1			T2	128		T48	7		T50	3
valid_sources[0x42]	1505521	1			T2	128		T3	29		T48	4
valid_sources[0x43]	1547482	1			T48	3		T49	1		T50	2
valid_sources[0x44]	1444621	1			T48	13		T50	1		T81	62
valid_sources[0x45]	1429950	1			T2	128		T48	4		T50	2
valid_sources[0x46]	1475208	1			T3	10		T48	12		T49	1
valid_sources[0x47]	3687748	1			T2	128		T3	16		T48	5
valid_sources[0x48]	1444202	1			T48	7		T49	1		T50	10
valid_sources[0x49]	1440545	1			T2	128		T48	4		T49	1
valid_sources[0x4a]	1542708	1			T2	256		T48	10		T49	3
valid_sources[0x4b]	3475197	1			T2	128		T48	10		T50	5
valid_sources[0x4c]	1432605	1			T48	3		T49	3		T50	3
valid_sources[0x4d]	1467748	1			T48	7		T50	5		T81	78
valid_sources[0x4e]	3620934	1			T2	128		T3	7		T48	2
valid_sources[0x4f]	2361753	1			T3	11		T48	5		T49	1
valid_sources[0x50]	1442209	1			T48	4		T50	16		T81	43
valid_sources[0x51]	1425288	1			T3	1		T48	4		T50	10
valid_sources[0x52]	3853097	1			T3	19		T48	5		T50	2
valid_sources[0x53]	1728578	1			T2	128		T48	7		T49	2
valid_sources[0x54]	1432826	1			T48	7		T49	1		T50	4
valid_sources[0x55]	1437460	1			T49	1		T50	12		T81	52
valid_sources[0x56]	1434396	1			T2	128		T48	4		T49	1
valid_sources[0x57]	1438802	1			T2	128		T3	1		T48	7
valid_sources[0x58]	1438387	1			T2	128		T3	23		T48	14
valid_sources[0x59]	1433512	1			T2	128		T48	9		T50	2
valid_sources[0x5a]	1436571	1			T2	128		T48	9		T49	1
valid_sources[0x5b]	2353379	1			T3	21		T48	4		T49	1
valid_sources[0x5c]	1433855	1			T2	128		T48	2		T50	6
valid_sources[0x5d]	1438513	1			T48	3		T50	8		T81	54
valid_sources[0x5e]	1491169	1			T48	6		T49	1		T50	8
valid_sources[0x5f]	1433947	1			T2	128		T48	3		T50	10
valid_sources[0x60]	1453694	1			T2	128		T48	1		T49	1
valid_sources[0x61]	1498437	1			T2	128		T48	13		T50	12
valid_sources[0x62]	1432928	1			T3	15		T48	6		T49	5
valid_sources[0x63]	3829227	1			T2	128		T3	27		T48	4
valid_sources[0x64]	1480366	1			T2	128		T48	3		T49	1
valid_sources[0x65]	3526972	1			T48	5		T49	1		T50	3
valid_sources[0x66]	2212769	1			T2	128		T3	2		T48	8
valid_sources[0x67]	1435281	1			T48	6		T49	1		T50	1
valid_sources[0x68]	1443349	1			T48	3		T49	1		T50	4
valid_sources[0x69]	1434443	1			T2	128		T48	6		T50	4
valid_sources[0x6a]	1491494	1			T2	128		T48	4		T50	6
valid_sources[0x6b]	2328846	1			T2	128		T48	14		T50	1
valid_sources[0x6c]	1442807	1			T48	5		T49	1		T50	12
valid_sources[0x6d]	1436446	1			T48	1		T49	1		T50	9
valid_sources[0x6e]	2060964	1			T50	7		T81	57		T51	8
valid_sources[0x6f]	1434463	1			T2	128		T48	5		T50	8
valid_sources[0x70]	1493703	1			T48	9		T49	1		T50	1
valid_sources[0x71]	1542974	1			T48	6		T49	1		T50	4
valid_sources[0x72]	1548832	1			T3	19		T48	8		T50	9
valid_sources[0x73]	1438480	1			T48	6		T50	10		T81	50
valid_sources[0x74]	1488922	1			T3	15		T48	3		T50	7
valid_sources[0x75]	1443393	1			T48	7		T49	1		T50	7
valid_sources[0x76]	1639784	1			T3	2		T48	3		T50	4
valid_sources[0x77]	4507090	1			T3	6		T48	4		T50	3
valid_sources[0x78]	1443842	1			T3	9		T48	6		T49	2
valid_sources[0x79]	1435590	1			T2	256		T3	18		T48	4
valid_sources[0x7a]	1435148	1			T2	256		T3	13		T48	9
valid_sources[0x7b]	1434981	1			T3	5		T48	1		T50	6
valid_sources[0x7c]	2352501	1			T3	30		T48	1		T49	2
valid_sources[0x7d]	1437468	1			T2	558		T3	17		T48	5
valid_sources[0x7e]	1525751	1			T48	7		T50	4		T81	51
valid_sources[0x7f]	1431776	1			T3	5		T48	6		T50	6
valid_sources[0x80]	1426180	1			T2	128		T48	5		T50	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89087314

1

T1

10

T2

3558

T3

641

values[0x0]

all_enables

biggest_size

62265140

1

T1

6

T2

3451

T3

299

values[0x1]

all_enables

biggest_size

53708363

1

T1

2

T2

3475

T3

298