Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265614160

1

T1

22

T2

4201

T48

396

full_word

205689261

1

T1

18

T2

10484

T3

1238

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	471303131	1			T1	40		T2	14685		T3	1238
auto[TlIntgErrCmd]	115	1			T51	10		T112	6		T113	9
auto[TlIntgErrData]	86	1			T51	4		T113	5		T117	5
auto[TlIntgErrBoth]	89	1			T51	6		T112	4		T113	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244005751

1

T1

20

T2

7221

T3

641

auto[1]

227297670

1

T1

20

T2

7464

T3

597

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154760721	1			T1	10		T2	3663		T48	375
auto[TlIntgErrNone]	partial	auto[1]	110853170	1			T1	12		T2	538		T48	21
auto[TlIntgErrNone]	full_word	auto[0]	89244905	1			T1	10		T2	3558		T3	641
auto[TlIntgErrNone]	full_word	auto[1]	116444335	1			T1	8		T2	6926		T3	597
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T51	3		T112	2		T113	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T51	6		T112	4		T113	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T51	1		T148	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T113	1		T117	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T51	4		T113	2		T117	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T113	3		T117	3		T115	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T117	1		T149	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T150	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T51	4		T112	1		T113	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T51	2		T112	3		T113	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T114	1		T151	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T116	1		T152	1		-	-