Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	118940454	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1272	1272	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118940454	0	0
T51	8968	0	0	0
T52	3176	313	0	0
T53	0	319	0	0
T55	1116	0	0	0
T56	1183	0	0	0
T82	0	188	0	0
T83	0	338	0	0
T84	0	62	0	0
T85	0	316	0	0
T86	0	137	0	0
T93	1606	76	0	0
T94	0	412	0	0
T95	0	188	0	0
T96	1753	0	0	0
T97	2753	0	0	0
T98	1380	0	0	0
T99	1324	0	0	0
T100	1276	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272	1272	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T57	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	230072602	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1272	1272	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	230072602	0	0
T51	8968	0	0	0
T52	3176	288	0	0
T53	0	314	0	0
T55	1116	0	0	0
T56	1183	0	0	0
T82	0	184	0	0
T83	0	1259	0	0
T84	0	48	0	0
T85	0	276	0	0
T86	0	75	0	0
T93	1606	159	0	0
T94	0	378	0	0
T95	0	168	0	0
T96	1753	0	0	0
T97	2753	0	0	0
T98	1380	0	0	0
T99	1324	0	0	0
T100	1276	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272	1272	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T57	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	321219055	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1272	1272	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	321219055	0	0
T1	2045	40	0	0
T2	134011	14791	0	0
T3	9017	1332	0	0
T48	8390	2939	0	0
T49	3076	269	0	0
T50	4106	2590	0	0
T57	1041	22	0	0
T79	2284	497	0	0
T80	2312	288	0	0
T81	30293	14797	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272	1272	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T57	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	644801921	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1272	1272	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	644801921	0	0
T1	2045	40	0	0
T2	134011	45296	0	0
T3	9017	1238	0	0
T48	8390	1428	0	0
T49	3076	151	0	0
T50	4106	1321	0	0
T57	1041	22	0	0
T79	2284	855	0	0
T80	2312	169	0	0
T81	30293	14685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2045	1964	0	0
T2	134011	133914	0	0
T3	9017	8948	0	0
T48	8390	7850	0	0
T49	3076	2727	0	0
T50	4106	3811	0	0
T57	1041	957	0	0
T79	2284	2230	0	0
T80	2312	1849	0	0
T81	30293	30224	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272	1272	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T57	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0