Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2285670	0	0
entropy_period_rd_A	2147483647	3648	0	0
intr_enable_rd_A	2147483647	4394	0	0
prefix_0_rd_A	2147483647	3489	0	0
prefix_10_rd_A	2147483647	3716	0	0
prefix_1_rd_A	2147483647	3621	0	0
prefix_2_rd_A	2147483647	3411	0	0
prefix_3_rd_A	2147483647	3704	0	0
prefix_4_rd_A	2147483647	3515	0	0
prefix_5_rd_A	2147483647	3914	0	0
prefix_6_rd_A	2147483647	3703	0	0
prefix_7_rd_A	2147483647	3824	0	0
prefix_8_rd_A	2147483647	3609	0	0
prefix_9_rd_A	2147483647	3560	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2285670	0	0
T51	8968	3	0	0
T52	3176	0	0	0
T53	7494	182	0	0
T82	6825	245	0	0
T83	0	205	0	0
T84	0	2	0	0
T86	1392	0	0	0
T87	1015	0	0	0
T88	6786	0	0	0
T89	947	0	0	0
T90	6221	0	0	0
T95	0	1	0	0
T100	1276	0	0	0
T112	0	2	0	0
T113	0	3	0	0
T115	0	3	0	0
T117	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3648	0	0
T2	134011	173	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	0	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	38	0	0
T90	0	38	0	0
T92	0	12	0	0
T93	1606	6	0	0
T97	0	6	0	0
T119	0	2	0	0
T120	0	32	0	0
T123	0	80	0	0
T125	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4394	0	0
T2	134011	281	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	7	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	67	0	0
T90	0	31	0	0
T93	1606	5	0	0
T100	0	4	0	0
T120	0	21	0	0
T123	0	24	0	0
T126	0	17	0	0
T127	0	20	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3489	0	0
T2	134011	231	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	0	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	26	0	0
T90	0	38	0	0
T92	0	28	0	0
T93	1606	2	0	0
T97	0	4	0	0
T119	0	6	0	0
T120	0	13	0	0
T123	0	30	0	0
T128	0	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3716	0	0
T2	134011	311	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	13	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	27	0	0
T90	0	24	0	0
T92	0	38	0	0
T93	1606	3	0	0
T97	0	14	0	0
T119	0	3	0	0
T120	0	10	0	0
T123	0	24	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3621	0	0
T2	134011	280	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	7	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	15	0	0
T90	0	38	0	0
T92	0	25	0	0
T93	1606	3	0	0
T97	0	4	0	0
T119	0	9	0	0
T120	0	2	0	0
T123	0	46	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3411	0	0
T2	134011	272	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	9	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	23	0	0
T90	0	29	0	0
T92	0	10	0	0
T93	1606	9	0	0
T97	0	7	0	0
T119	0	3	0	0
T120	0	23	0	0
T123	0	27	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3704	0	0
T2	134011	274	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	10	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	25	0	0
T90	0	30	0	0
T92	0	11	0	0
T93	1606	5	0	0
T97	0	5	0	0
T119	0	3	0	0
T120	0	7	0	0
T123	0	74	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3515	0	0
T2	134011	287	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	13	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	20	0	0
T90	0	17	0	0
T92	0	2	0	0
T93	1606	2	0	0
T97	0	5	0	0
T119	0	2	0	0
T120	0	18	0	0
T123	0	46	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3914	0	0
T2	134011	337	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	12	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	24	0	0
T90	0	30	0	0
T92	0	9	0	0
T93	1606	6	0	0
T97	0	4	0	0
T120	0	13	0	0
T123	0	31	0	0
T125	0	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3703	0	0
T2	134011	299	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	4	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	25	0	0
T90	0	37	0	0
T92	0	52	0	0
T93	1606	5	0	0
T97	0	3	0	0
T119	0	7	0	0
T120	0	16	0	0
T123	0	30	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3824	0	0
T2	134011	294	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	9	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	20	0	0
T90	0	27	0	0
T92	0	57	0	0
T93	1606	8	0	0
T97	0	4	0	0
T120	0	17	0	0
T123	0	37	0	0
T125	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3609	0	0
T2	134011	256	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	6	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	22	0	0
T90	0	29	0	0
T92	0	29	0	0
T93	1606	5	0	0
T97	0	4	0	0
T120	0	11	0	0
T123	0	56	0	0
T125	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3560	0	0
T2	134011	227	0	0
T3	9017	0	0	0
T48	8390	0	0	0
T49	3076	0	0	0
T50	4106	0	0	0
T57	1041	0	0	0
T79	2284	0	0	0
T80	2312	0	0	0
T81	30293	0	0	0
T88	0	13	0	0
T90	0	32	0	0
T92	0	11	0	0
T93	1606	5	0	0
T97	0	10	0	0
T120	0	9	0	0
T123	0	46	0	0
T129	0	11	0	0
T130	0	2	0	0