Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102294421	1			T1	1		T56	8		T59	8
all_values[1]	102294421	1			T1	1		T56	8		T59	8
all_values[2]	102294421	1			T1	1		T56	8		T59	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

728031

1

T1

3

T56

8

T59

6

auto[1]

306155232

1

T56

16

T59

18

T60

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305328555

1

T1

3

T56

15

T59

15

auto[1]

1554708

1

T56

9

T59

9

T60

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	213562	1			T1	1		T56	2		T59	1
all_values[0]	auto[0]	auto[1]	2674	1			T56	1		T59	1		T60	1
all_values[0]	auto[1]	auto[0]	101562623	1			T56	3		T59	4		T60	1
all_values[0]	auto[1]	auto[1]	515562	1			T56	2		T59	2		T60	2
all_values[1]	auto[0]	auto[0]	225863	1			T1	1		T56	1		T59	1
all_values[1]	auto[0]	auto[1]	1843	1			T59	1		T60	1		T142	2
all_values[1]	auto[1]	auto[0]	101550322	1			T56	4		T59	4		T60	1
all_values[1]	auto[1]	auto[1]	516393	1			T56	3		T59	2		T60	2
all_values[2]	auto[0]	auto[0]	282129	1			T1	1		T56	2		T59	1
all_values[2]	auto[0]	auto[1]	1960	1			T56	2		T59	1		T60	2
all_values[2]	auto[1]	auto[0]	101494056	1			T56	3		T59	4		T60	1
all_values[2]	auto[1]	auto[1]	516276	1			T56	1		T59	2		T60	1