Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.45 97.09 92.48 66.55 75.00 93.80 99.79


Total modules in report: 53
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tlul_err_resp 57.80 76.92 40.91 55.56
keccak_round 75.45 71.25 100.00 26.67 79.31 100.00
keccak_2share 81.25 100.00 75.00 50.00 100.00
kmac_app 87.58 94.65 87.72 64.00 91.55 100.00
kmac_staterd 90.00 100.00 70.00 100.00
sha3 90.45 97.30 81.25 81.82 91.89 100.00
kmac 90.77 96.32 91.89 63.67 100.00 92.73 100.00
  prim_fifo_sync 93.12 100.00 77.49 95.00 100.00
  tlul_adapter_sram 93.36 98.45 79.18 95.83 100.00
prim_intr_hw 93.75 100.00 75.00 100.00 100.00
sha3pad 93.83 99.38 88.37 85.71 95.70 100.00
kmac_errchk 94.24 96.72 96.67 81.82 96.00 100.00
kmac_core 94.46 98.55 92.86 100.00 92.00 88.89
prim_arbiter_fixed 95.05 87.50 92.68 100.00 100.00
  tlul_rsp_intg_gen 95.83 91.67 100.00
prim_subreg_shadow 97.12 100.00 88.46 100.00 100.00
  prim_fifo_sync_cnt 97.22 94.44 100.00
tlul_socket_1n 97.25 100.00 93.33 95.65 100.00
prim_packer 97.50 100.00 100.00 90.00 100.00
kmac_msgfifo 97.92 100.00 100.00 91.67 100.00
tlul_adapter_reg 98.98 100.00 95.92 100.00 100.00
kmac_reg_top 99.90 100.00 99.62 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
prim_sparse_fsm_flop 100.00 100.00 100.00
prim_count 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
sha3pad_assert_if 100.00 100.00
prim_mubi4_sender 100.00 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_slicer 100.00 100.00 100.00
  prim_subreg_arb 100.00 100.00 100.00 100.00
kmac_csr_assert_fpv 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_sram_byte 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_flop
prim_flop_2sync
tb
prim_sec_anchor_buf