Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
375753 |
1 |
|
|
T4 |
18 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
329308 |
1 |
|
|
T6 |
178 |
|
T15 |
86 |
|
T19 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175851 |
1 |
|
|
T4 |
6 |
|
T6 |
48 |
|
T14 |
46 |
lower_val |
174134 |
1 |
|
|
T4 |
5 |
|
T6 |
34 |
|
T14 |
44 |
zero_val |
2084 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
352294 |
1 |
|
|
T4 |
10 |
|
T6 |
104 |
|
T7 |
2 |
lower_val |
352755 |
1 |
|
|
T4 |
8 |
|
T6 |
76 |
|
T14 |
112 |
zero_val |
12 |
1 |
|
|
T19 |
2 |
|
T131 |
2 |
|
T132 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46882 |
1 |
|
|
T4 |
3 |
|
T14 |
19 |
|
T15 |
26 |
higher_val |
higher_val |
auto[1] |
41209 |
1 |
|
|
T6 |
33 |
|
T15 |
5 |
|
T19 |
595 |
higher_val |
lower_val |
auto[0] |
46436 |
1 |
|
|
T4 |
3 |
|
T14 |
27 |
|
T15 |
28 |
higher_val |
lower_val |
auto[1] |
41320 |
1 |
|
|
T6 |
15 |
|
T15 |
9 |
|
T19 |
552 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T132 |
2 |
|
T133 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T19 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
46805 |
1 |
|
|
T4 |
2 |
|
T14 |
16 |
|
T15 |
46 |
lower_val |
higher_val |
auto[1] |
40319 |
1 |
|
|
T6 |
19 |
|
T15 |
12 |
|
T19 |
561 |
lower_val |
lower_val |
auto[0] |
46442 |
1 |
|
|
T4 |
3 |
|
T14 |
28 |
|
T15 |
28 |
lower_val |
lower_val |
auto[1] |
40568 |
1 |
|
|
T6 |
15 |
|
T15 |
9 |
|
T19 |
593 |
zero_val |
higher_val |
auto[0] |
762 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
higher_val |
auto[1] |
270 |
1 |
|
|
T15 |
1 |
|
T19 |
5 |
|
T131 |
1 |
zero_val |
lower_val |
auto[0] |
773 |
1 |
|
|
T17 |
1 |
|
T20 |
1 |
|
T45 |
1 |
zero_val |
lower_val |
auto[1] |
279 |
1 |
|
|
T19 |
1 |
|
T27 |
3 |
|
T131 |
3 |