Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102294421	1			T1	1		T56	8		T59	8
all_pins[1]	102294421	1			T1	1		T56	8		T59	8
all_pins[2]	102294421	1			T1	1		T56	8		T59	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	247307436	1			T1	3		T56	19		T59	18
values[0x1]	59575827	1			T56	5		T59	6		T60	5
transitions[0x0=>0x1]	59113739	1			T56	5		T59	3		T60	3
transitions[0x1=>0x0]	59113758	1			T56	5		T59	4		T60	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101778859	1			T1	1		T56	6		T59	6
all_pins[0]	values[0x1]	515562	1			T56	2		T59	2		T60	2
all_pins[0]	transitions[0x0=>0x1]	220325	1			T56	2		T59	2		T130	2
all_pins[0]	transitions[0x1=>0x0]	58410518	1			T143	2		T130	2		T144	3
all_pins[1]	values[0x0]	43588666	1			T1	1		T56	8		T59	8
all_pins[1]	values[0x1]	58705755	1			T60	2		T143	2		T130	2
all_pins[1]	transitions[0x0=>0x1]	58541047	1			T60	2		T143	2		T130	1
all_pins[1]	transitions[0x1=>0x0]	189802	1			T56	3		T59	4		T60	1
all_pins[2]	values[0x0]	101939911	1			T1	1		T56	5		T59	4
all_pins[2]	values[0x1]	354510	1			T56	3		T59	4		T60	1
all_pins[2]	transitions[0x0=>0x1]	352367	1			T56	3		T59	1		T60	1
all_pins[2]	transitions[0x1=>0x0]	513438	1			T56	2		T60	2		T130	1