Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
346005 |
1 |
|
|
T4 |
9 |
|
T6 |
100 |
|
T7 |
2 |
auto[1] |
3425 |
1 |
|
|
T5 |
1 |
|
T6 |
14 |
|
T14 |
15 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
307801 |
1 |
|
|
T6 |
52 |
|
T7 |
2 |
|
T14 |
70 |
auto[1] |
41629 |
1 |
|
|
T4 |
9 |
|
T5 |
1 |
|
T6 |
62 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334626 |
1 |
|
|
T4 |
9 |
|
T6 |
77 |
|
T7 |
2 |
auto[1] |
14804 |
1 |
|
|
T5 |
1 |
|
T6 |
37 |
|
T14 |
31 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
14804 |
1 |
|
|
T5 |
1 |
|
T6 |
37 |
|
T14 |
31 |
sw_kmac_invalid_sideload |
334626 |
1 |
|
|
T4 |
9 |
|
T6 |
77 |
|
T7 |
2 |
app_valid_sideload |
14804 |
1 |
|
|
T5 |
1 |
|
T6 |
37 |
|
T14 |
31 |
app_invalid_sideload |
334626 |
1 |
|
|
T4 |
9 |
|
T6 |
77 |
|
T7 |
2 |