Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 281 1 T56 7 T59 7 T60 4
all_values[1] 281 1 T56 7 T59 7 T60 4
all_values[2] 281 1 T56 7 T59 7 T60 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 451 1 T56 9 T59 8 T60 8
auto[1] 392 1 T56 12 T59 13 T60 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 327 1 T56 7 T59 9 T60 4
auto[1] 516 1 T56 14 T59 12 T60 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 497 1 T56 13 T59 11 T60 8
auto[1] 346 1 T56 8 T59 10 T60 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 70 1 T56 3 T60 1 T145 2
all_values[0] auto[0] auto[0] auto[1] 26 1 T60 1 T142 1 T143 1
all_values[0] auto[0] auto[1] auto[0] 43 1 T56 1 T59 2 T130 2
all_values[0] auto[0] auto[1] auto[1] 25 1 T56 1 T60 1 T130 1
all_values[0] auto[1] auto[0] auto[1] 62 1 T56 2 T59 2 T60 1
all_values[0] auto[1] auto[1] auto[1] 55 1 T59 3 T145 1 T146 1
all_values[1] auto[0] auto[0] auto[0] 67 1 T59 2 T60 2 T145 2
all_values[1] auto[0] auto[0] auto[1] 28 1 T56 1 T142 2 T130 1
all_values[1] auto[0] auto[1] auto[0] 55 1 T56 3 T59 4 T145 2
all_values[1] auto[0] auto[1] auto[1] 25 1 T60 1 T143 1 T130 2
all_values[1] auto[1] auto[0] auto[1] 58 1 T56 1 T60 1 T142 2
all_values[1] auto[1] auto[1] auto[1] 48 1 T56 2 T59 1 T130 1
all_values[2] auto[0] auto[0] auto[0] 51 1 T59 1 T60 1 T145 1
all_values[2] auto[0] auto[0] auto[1] 25 1 T56 1 T60 1 T145 1
all_values[2] auto[0] auto[1] auto[0] 41 1 T143 1 T130 1 T146 2
all_values[2] auto[0] auto[1] auto[1] 41 1 T56 3 T59 2 T142 3
all_values[2] auto[1] auto[0] auto[1] 64 1 T56 1 T59 3 T145 1
all_values[2] auto[1] auto[1] auto[1] 59 1 T56 2 T59 1 T60 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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