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 LINE       2780
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T55,T52

 LINE       2780
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T55,T51

 LINE       2780
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T55,T51
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T55,T52

 LINE       2780
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T55,T52

 LINE       2780
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T55,T52

 LINE       2780
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T55,T52

 LINE       2780
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T3

 LINE       2780
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T3,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T55

 LINE       2780
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T55
1	1	Covered	T1,T2,T55

 LINE       2845
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T54,T106
1	1	1	Covered	T56,T59,T60

 LINE       2852
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T78,T83
1	1	1	Covered	T2,T3,T55

 LINE       2859
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T83,T106
1	1	1	Covered	T56,T59,T60

 LINE       2866
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T28,T33
1	1	1	Covered	T2,T3,T55

 LINE       2871
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T51,T52,T53

 LINE       2872
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T55

 LINE       2873
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T54,T78
1	1	1	Covered	T2,T3,T55

 LINE       2898
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T106
1	1	1	Covered	T4,T5,T6

 LINE       2905
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T107
1	1	1	Covered	T2,T3,T55

 LINE       2906
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T54,T78
1	1	1	Covered	T2,T3,T55

 LINE       2911
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T55

 LINE       2912
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T106
1	1	1	Covered	T2,T3,T55

 LINE       2915
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T80,T81,T83
1	1	1	Covered	T2,T3,T55

 LINE       2918
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T77,T78
1	1	1	Covered	T2,T3,T55

 LINE       2921
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T77,T78
1	1	1	Covered	T2,T3,T55

 LINE       2924
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T80,T28
1	1	1	Covered	T2,T3,T55

 LINE       2927
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T80
1	1	1	Covered	T2,T3,T55

 LINE       2930
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T28
1	1	1	Covered	T2,T3,T55

 LINE       2933
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T81,T106,T28
1	1	1	Covered	T2,T3,T55

 LINE       2936
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T54,T78
1	1	1	Covered	T2,T3,T55

 LINE       2939
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T78,T81
1	1	1	Covered	T2,T3,T55

 LINE       2942
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T78,T81
1	1	1	Covered	T2,T3,T55

 LINE       2945
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T80,T108
1	1	1	Covered	T2,T3,T55

 LINE       2948
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T78,T106
1	1	1	Covered	T2,T3,T55

 LINE       2951
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T106
1	1	1	Covered	T2,T3,T55

 LINE       2954
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T83,T106,T28
1	1	1	Covered	T2,T3,T55

 LINE       2957
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T106,T28
1	1	1	Covered	T2,T3,T55

 LINE       2960
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T81
1	1	1	Covered	T2,T3,T55

 LINE       2963
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T81
1	1	1	Covered	T2,T3,T55

 LINE       2966
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T83,T106,T108
1	1	1	Covered	T2,T3,T55

 LINE       2969
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T28,T33
1	1	1	Covered	T2,T3,T55

 LINE       2972
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T81,T106,T28
1	1	1	Covered	T2,T55,T52

 LINE       2975
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T83,T106
1	1	1	Covered	T2,T3,T55

 LINE       2978
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T77,T78
1	1	1	Covered	T2,T3,T55

 LINE       2981
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T81,T106
1	1	1	Covered	T2,T3,T55

 LINE       2984
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T106
1	1	1	Covered	T2,T3,T55

 LINE       2987
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T106
1	1	1	Covered	T2,T3,T55

 LINE       2990
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T78,T83
1	1	1	Covered	T2,T3,T55

 LINE       2993
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T77,T78
1	1	1	Covered	T2,T3,T55

 LINE       2996
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T83
1	1	1	Covered	T3,T55,T52

 LINE       2999
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T80,T81
1	1	1	Covered	T2,T3,T55

 LINE       3002
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T108
1	1	1	Covered	T2,T3,T55

 LINE       3005
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T78,T80
1	1	1	Covered	T2,T3,T55

 LINE       3008
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T81
1	1	1	Covered	T2,T3,T55

 LINE       3011
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T83
1	1	1	Covered	T2,T3,T55

 LINE       3014
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T80,T81
1	1	1	Covered	T2,T3,T55

 LINE       3017
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T106,T28
1	1	1	Covered	T2,T3,T55

 LINE       3020
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T54,T108
1	1	1	Covered	T2,T3,T55

 LINE       3023
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T83
1	1	1	Covered	T2,T3,T55

 LINE       3026
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T81,T83,T28
1	1	1	Covered	T2,T3,T55

 LINE       3029
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T106,T28,T33
1	1	1	Covered	T2,T3,T55

 LINE       3032
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T78,T83
1	1	1	Covered	T2,T3,T55

 LINE       3035
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T78,T80
1	1	1	Covered	T3,T55,T52

 LINE       3038
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T28,T33,T29
1	1	1	Covered	T2,T3,T55

 LINE       3041
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T81,T83
1	1	1	Covered	T2,T3,T55

 LINE       3044
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T77,T78
1	1	1	Covered	T2,T3,T55

 LINE       3047
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T81
1	1	1	Covered	T3,T55,T52

 LINE       3050
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T83
1	1	1	Covered	T2,T3,T55

 LINE       3053
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T80
1	1	1	Covered	T2,T3,T55

 LINE       3056
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T83
1	1	1	Covered	T2,T3,T55

 LINE       3059
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T55
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T78,T80
1	1	1	Covered	T2,T3,T55

 LINE       3432
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T53,T58,T87
1	0	Covered	T52,T91,T99
1	1	Covered	T1,T2,T3