Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.60 96.58 92.49 100.00 89.77 94.67 98.84 96.88


Total test records in report: 1274
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T1251 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2771191506 Jan 21 03:19:59 PM PST 24 Jan 21 03:20:01 PM PST 24 12755229 ps
T1252 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2749012860 Jan 21 03:19:03 PM PST 24 Jan 21 03:19:11 PM PST 24 1647026944 ps
T1253 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1031518436 Jan 21 03:18:58 PM PST 24 Jan 21 03:19:00 PM PST 24 13989253 ps
T1254 /workspace/coverage/cover_reg_top/44.kmac_intr_test.3139131411 Jan 21 03:20:07 PM PST 24 Jan 21 03:20:09 PM PST 24 167425141 ps
T1255 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3436796675 Jan 21 03:19:00 PM PST 24 Jan 21 03:19:04 PM PST 24 32413596 ps
T1256 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1073220308 Jan 21 03:19:13 PM PST 24 Jan 21 03:19:15 PM PST 24 86998639 ps
T1257 /workspace/coverage/cover_reg_top/39.kmac_intr_test.4052944146 Jan 21 03:20:08 PM PST 24 Jan 21 03:20:10 PM PST 24 17562115 ps
T1258 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1475094701 Jan 21 03:19:47 PM PST 24 Jan 21 03:19:49 PM PST 24 30843662 ps
T1259 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1931946717 Jan 21 03:19:51 PM PST 24 Jan 21 03:19:55 PM PST 24 407430659 ps
T1260 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.533407770 Jan 21 03:18:53 PM PST 24 Jan 21 03:18:55 PM PST 24 73478424 ps
T1261 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.776750685 Jan 21 04:00:36 PM PST 24 Jan 21 04:00:39 PM PST 24 24075952 ps
T1262 /workspace/coverage/cover_reg_top/10.kmac_intr_test.3572342 Jan 21 03:19:17 PM PST 24 Jan 21 03:19:19 PM PST 24 15947722 ps
T1263 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.968424736 Jan 21 03:18:35 PM PST 24 Jan 21 03:18:39 PM PST 24 35986890 ps
T1264 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1582304778 Jan 21 03:19:15 PM PST 24 Jan 21 03:19:19 PM PST 24 182982187 ps
T1265 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3919030564 Jan 21 03:18:26 PM PST 24 Jan 21 03:18:30 PM PST 24 158444251 ps
T1266 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.492361799 Jan 21 03:18:53 PM PST 24 Jan 21 03:18:55 PM PST 24 90545491 ps
T1267 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4115792686 Jan 21 03:18:49 PM PST 24 Jan 21 03:18:53 PM PST 24 119553365 ps
T1268 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3282595289 Jan 21 03:18:42 PM PST 24 Jan 21 03:18:45 PM PST 24 36168343 ps
T1269 /workspace/coverage/cover_reg_top/12.kmac_intr_test.98640235 Jan 21 03:19:33 PM PST 24 Jan 21 03:19:36 PM PST 24 29924054 ps
T1270 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1677550301 Jan 21 03:19:36 PM PST 24 Jan 21 03:19:39 PM PST 24 363784531 ps
T1271 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2960111992 Jan 21 03:20:01 PM PST 24 Jan 21 03:20:03 PM PST 24 92814568 ps
T1272 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.638707906 Jan 21 03:19:48 PM PST 24 Jan 21 03:19:50 PM PST 24 223486195 ps
T1273 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3541860050 Jan 21 03:18:38 PM PST 24 Jan 21 03:18:42 PM PST 24 1018416242 ps
T1274 /workspace/coverage/cover_reg_top/7.kmac_intr_test.2001361885 Jan 21 03:19:10 PM PST 24 Jan 21 03:19:13 PM PST 24 13162408 ps


Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3582399845
Short name T1
Test name
Test status
Simulation time 44573291 ps
CPU time 1.57 seconds
Started Jan 21 03:19:03 PM PST 24
Finished Jan 21 03:19:06 PM PST 24
Peak memory 215076 kb
Host smart-d666bc77-0c64-4ca8-8fd3-00a0fb0f57ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582399845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3582399845 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest


Test location /workspace/coverage/default/6.kmac_stress_all.797785984
Short name T15
Test name
Test status
Simulation time 116802882645 ps
CPU time 825.54 seconds
Started Jan 21 01:48:20 PM PST 24
Finished Jan 21 02:02:07 PM PST 24
Peak memory 322984 kb
Host smart-8932c771-ab43-434a-a198-30a7580f5242
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=797785984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.797785984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1557078547
Short name T52
Test name
Test status
Simulation time 221167764 ps
CPU time 2.84 seconds
Started Jan 21 03:19:43 PM PST 24
Finished Jan 21 03:19:47 PM PST 24
Peak memory 215280 kb
Host smart-9740bb35-a132-48cd-8ce9-4cae736bf794
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557078547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1557078547 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/default/17.kmac_stress_all_with_rand_reset.1595446632
Short name T38
Test name
Test status
Simulation time 95057585882 ps
CPU time 2190.68 seconds
Started Jan 21 01:53:47 PM PST 24
Finished Jan 21 02:30:18 PM PST 24
Peak memory 355312 kb
Host smart-93678e02-b649-4a24-aa6e-5b79e6c02a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595446632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all_with_rand_reset.1595446632 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.431866729
Short name T130
Test name
Test status
Simulation time 16272286 ps
CPU time 0.78 seconds
Started Jan 21 03:19:26 PM PST 24
Finished Jan 21 03:19:28 PM PST 24
Peak memory 206588 kb
Host smart-d193a7dc-2e18-49f0-99ba-ecfb88a03c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431866729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.431866729 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest


Test location /workspace/coverage/default/0.kmac_sec_cm.2416568191
Short name T11
Test name
Test status
Simulation time 16068420568 ps
CPU time 54.56 seconds
Started Jan 21 01:46:31 PM PST 24
Finished Jan 21 01:47:26 PM PST 24
Peak memory 258848 kb
Host smart-73a63f1f-05cc-4259-8a15-500aafcd7bab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416568191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2416568191 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest


Test location /workspace/coverage/default/9.kmac_error.1450995125
Short name T34
Test name
Test status
Simulation time 55407957858 ps
CPU time 307.09 seconds
Started Jan 21 01:49:36 PM PST 24
Finished Jan 21 01:54:45 PM PST 24
Peak memory 256632 kb
Host smart-310fcf25-09bb-4ad2-988b-ba6ab7d6245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450995125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1450995125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.824256207
Short name T102
Test name
Test status
Simulation time 1785465677 ps
CPU time 4.99 seconds
Started Jan 21 03:19:09 PM PST 24
Finished Jan 21 03:19:15 PM PST 24
Peak memory 215060 kb
Host smart-304279fe-48e6-4a2a-9d21-9540eff0adc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824256207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.824256
207 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1323270960
Short name T87
Test name
Test status
Simulation time 30457881 ps
CPU time 1.21 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 215352 kb
Host smart-67061744-1ba6-446b-9027-56aecbcb4f83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323270960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1323270960 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/default/21.kmac_stress_all.1348792043
Short name T27
Test name
Test status
Simulation time 123216398889 ps
CPU time 861.3 seconds
Started Jan 21 02:58:16 PM PST 24
Finished Jan 21 03:12:42 PM PST 24
Peak memory 322304 kb
Host smart-b6b238cf-451c-4aec-be7b-b044a5d19913
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1348792043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1348792043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.572507121
Short name T88
Test name
Test status
Simulation time 439222776 ps
CPU time 2.81 seconds
Started Jan 21 03:45:17 PM PST 24
Finished Jan 21 03:45:21 PM PST 24
Peak memory 222736 kb
Host smart-d65397e3-3d20-47dc-a6bd-10def78d9001
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572507121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_
shadow_reg_errors_with_csr_rw.572507121 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/default/2.kmac_key_error.3431355600
Short name T5
Test name
Test status
Simulation time 923700243 ps
CPU time 5.01 seconds
Started Jan 21 01:47:08 PM PST 24
Finished Jan 21 01:47:16 PM PST 24
Peak memory 207520 kb
Host smart-405f266a-29c8-407c-9d1f-d76d94be631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431355600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3431355600 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.410695954
Short name T19
Test name
Test status
Simulation time 590301443158 ps
CPU time 4218.77 seconds
Started Jan 21 01:50:38 PM PST 24
Finished Jan 21 03:00:59 PM PST 24
Peak memory 539480 kb
Host smart-51c65584-a430-4b9f-aa22-1e0add9094eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=410695954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.410695954 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.4290799328
Short name T152
Test name
Test status
Simulation time 503983966 ps
CPU time 5.31 seconds
Started Jan 21 03:19:46 PM PST 24
Finished Jan 21 03:19:53 PM PST 24
Peak memory 215008 kb
Host smart-b8f0a0b8-1eeb-4a0c-abf6-4207f882ed22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290799328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.4290
799328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3588226488
Short name T124
Test name
Test status
Simulation time 35811859 ps
CPU time 1.48 seconds
Started Jan 21 03:36:00 PM PST 24
Finished Jan 21 03:36:03 PM PST 24
Peak memory 215020 kb
Host smart-739d7f96-3b4d-450f-b798-4770876e6696
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588226488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3588226488 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2026889168
Short name T58
Test name
Test status
Simulation time 81241947 ps
CPU time 2.04 seconds
Started Jan 21 03:19:50 PM PST 24
Finished Jan 21 03:19:53 PM PST 24
Peak memory 215384 kb
Host smart-75596cb2-a798-4c8d-88f1-609a2947ed61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026889168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.2026889168 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.970489467
Short name T157
Test name
Test status
Simulation time 15826365 ps
CPU time 0.87 seconds
Started Jan 21 05:15:43 PM PST 24
Finished Jan 21 05:15:48 PM PST 24
Peak memory 206604 kb
Host smart-190fe25e-3dad-4aad-a87c-4dbad80e019d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970489467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.970489467 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.441389770
Short name T148
Test name
Test status
Simulation time 2012270767 ps
CPU time 5.42 seconds
Started Jan 21 03:19:27 PM PST 24
Finished Jan 21 03:19:33 PM PST 24
Peak memory 206856 kb
Host smart-d990d8be-6cfe-48ae-9a90-ca2cd7f451be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441389770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.44138
9770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest


Test location /workspace/coverage/default/38.kmac_error.191699981
Short name T138
Test name
Test status
Simulation time 8019159120 ps
CPU time 221.93 seconds
Started Jan 21 02:09:34 PM PST 24
Finished Jan 21 02:13:21 PM PST 24
Peak memory 248180 kb
Host smart-82f7bb6f-88d9-49fe-a4e0-66c535cee59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191699981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.191699981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest


Test location /workspace/coverage/default/17.kmac_key_error.3582221827
Short name T24
Test name
Test status
Simulation time 945582293 ps
CPU time 4.99 seconds
Started Jan 21 01:53:37 PM PST 24
Finished Jan 21 01:53:43 PM PST 24
Peak memory 207496 kb
Host smart-5179cab1-4599-41e4-8436-74b734b8bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582221827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3582221827 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest


Test location /workspace/coverage/default/29.kmac_stress_all_with_rand_reset.4077400858
Short name T57
Test name
Test status
Simulation time 76357102607 ps
CPU time 1440.14 seconds
Started Jan 21 02:35:36 PM PST 24
Finished Jan 21 02:59:38 PM PST 24
Peak memory 314104 kb
Host smart-4a2b6218-82e9-4016-a664-28e122166482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077400858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.4077400858 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2134147181
Short name T107
Test name
Test status
Simulation time 196195571 ps
CPU time 2.52 seconds
Started Jan 21 03:18:57 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 206744 kb
Host smart-08ea71f1-e3ac-473c-935b-40792125aa0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134147181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.21341
47181 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest


Test location /workspace/coverage/default/20.kmac_lc_escalation.2106213628
Short name T238
Test name
Test status
Simulation time 54239269 ps
CPU time 1.32 seconds
Started Jan 21 02:12:33 PM PST 24
Finished Jan 21 02:12:36 PM PST 24
Peak memory 219284 kb
Host smart-3a6662da-c106-4375-b6c8-1e86f2bc79b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106213628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2106213628 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest


Test location /workspace/coverage/default/11.kmac_alert_test.4188942821
Short name T183
Test name
Test status
Simulation time 54974445 ps
CPU time 0.78 seconds
Started Jan 21 02:22:33 PM PST 24
Finished Jan 21 02:22:34 PM PST 24
Peak memory 207268 kb
Host smart-92dc5dc5-4e90-4e2b-ac85-0041770ce639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188942821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.4188942821 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.2263977985
Short name T1197
Test name
Test status
Simulation time 11639955 ps
CPU time 0.8 seconds
Started Jan 21 03:18:35 PM PST 24
Finished Jan 21 03:18:38 PM PST 24
Peak memory 206564 kb
Host smart-bc7536a2-5742-4cf0-8c98-58280ef84fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263977985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2263977985 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.10697060
Short name T151
Test name
Test status
Simulation time 449369774 ps
CPU time 5.01 seconds
Started Jan 21 03:18:40 PM PST 24
Finished Jan 21 03:18:49 PM PST 24
Peak memory 218656 kb
Host smart-1a3363ee-e1e8-40b4-a8f0-8f68ffe02c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10697060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.1069706
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2537605619
Short name T104
Test name
Test status
Simulation time 74987386 ps
CPU time 2.56 seconds
Started Jan 21 03:19:22 PM PST 24
Finished Jan 21 03:19:26 PM PST 24
Peak memory 215044 kb
Host smart-45baae69-1d43-4708-99e4-aaffe3ccca9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537605619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2537
605619 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest


Test location /workspace/coverage/default/11.kmac_stress_all.1312236624
Short name T135
Test name
Test status
Simulation time 187667754191 ps
CPU time 2105.22 seconds
Started Jan 21 01:50:29 PM PST 24
Finished Jan 21 02:25:35 PM PST 24
Peak memory 418212 kb
Host smart-6763dbb0-c55c-4dc9-afa5-cf77ed5b3e6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1312236624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1312236624 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2617758682
Short name T132
Test name
Test status
Simulation time 56471482871 ps
CPU time 1114.89 seconds
Started Jan 21 01:51:18 PM PST 24
Finished Jan 21 02:09:55 PM PST 24
Peak memory 333564 kb
Host smart-d21f1c5c-f8c9-460b-81a8-2de3179e8abd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2617758682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2617758682 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/44.kmac_stress_all.2995554496
Short name T43
Test name
Test status
Simulation time 63964660224 ps
CPU time 431.55 seconds
Started Jan 21 02:14:13 PM PST 24
Finished Jan 21 02:21:26 PM PST 24
Peak memory 292132 kb
Host smart-a94c730c-4359-4643-a4a5-3e3f64acc0cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2995554496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2995554496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest


Test location /workspace/coverage/default/0.kmac_edn_timeout_error.2931876598
Short name T8
Test name
Test status
Simulation time 115497035 ps
CPU time 3.38 seconds
Started Jan 21 01:46:23 PM PST 24
Finished Jan 21 01:46:27 PM PST 24
Peak memory 216756 kb
Host smart-b62b844e-4921-4d79-90a1-7ce09fe52728
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2931876598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2931876598 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2171377132
Short name T129
Test name
Test status
Simulation time 875278481 ps
CPU time 5.96 seconds
Started Jan 21 03:18:36 PM PST 24
Finished Jan 21 03:18:44 PM PST 24
Peak memory 206888 kb
Host smart-cb45bb7c-925f-47b4-92b8-d33da4f3d67a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171377132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2171377
132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3426812183
Short name T1190
Test name
Test status
Simulation time 527135476 ps
CPU time 10.59 seconds
Started Jan 21 03:18:33 PM PST 24
Finished Jan 21 03:18:48 PM PST 24
Peak memory 206864 kb
Host smart-6b157200-9f73-497c-bdb1-37f97797d1fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426812183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3426812
183 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.968424736
Short name T1263
Test name
Test status
Simulation time 35986890 ps
CPU time 1.17 seconds
Started Jan 21 03:18:35 PM PST 24
Finished Jan 21 03:18:39 PM PST 24
Peak memory 215080 kb
Host smart-72669153-bff7-41b2-b0a2-f154dacf2ece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968424736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.96842473
6 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3171814609
Short name T1185
Test name
Test status
Simulation time 160117607 ps
CPU time 1.7 seconds
Started Jan 21 03:18:37 PM PST 24
Finished Jan 21 03:18:41 PM PST 24
Peak memory 222896 kb
Host smart-b876159a-7087-4775-a819-d2b6a6c11e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171814609 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3171814609 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.540238997
Short name T1232
Test name
Test status
Simulation time 134457186 ps
CPU time 0.97 seconds
Started Jan 21 03:18:29 PM PST 24
Finished Jan 21 03:18:31 PM PST 24
Peak memory 206660 kb
Host smart-73666c4f-2076-4b42-b8b4-0f0772e788f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540238997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.540238997 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2695300596
Short name T1186
Test name
Test status
Simulation time 15273207 ps
CPU time 0.79 seconds
Started Jan 21 03:18:31 PM PST 24
Finished Jan 21 03:18:38 PM PST 24
Peak memory 206472 kb
Host smart-04286d75-6b19-47db-b179-150cbb0b244c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695300596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2695300596 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1809352558
Short name T1249
Test name
Test status
Simulation time 15478745 ps
CPU time 0.77 seconds
Started Jan 21 03:18:27 PM PST 24
Finished Jan 21 03:18:28 PM PST 24
Peak memory 206628 kb
Host smart-2a45b243-7802-462f-a627-5b1880295afe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809352558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1809352558
+enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.4060172681
Short name T1214
Test name
Test status
Simulation time 45179631 ps
CPU time 1.49 seconds
Started Jan 21 03:18:37 PM PST 24
Finished Jan 21 03:18:41 PM PST 24
Peak memory 206784 kb
Host smart-d555a94e-9610-465c-8dc6-50a6dd003cd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060172681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.4060172681 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3903816904
Short name T1209
Test name
Test status
Simulation time 96958661 ps
CPU time 0.96 seconds
Started Jan 21 03:18:27 PM PST 24
Finished Jan 21 03:18:29 PM PST 24
Peak memory 206984 kb
Host smart-79409d33-be1b-43e4-931b-9d562f876837
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903816904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.3903816904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3919030564
Short name T1265
Test name
Test status
Simulation time 158444251 ps
CPU time 3.14 seconds
Started Jan 21 03:18:26 PM PST 24
Finished Jan 21 03:18:30 PM PST 24
Peak memory 215572 kb
Host smart-4419485a-79d4-480b-9055-dca8dad51ff8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919030564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3919030564 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2629826931
Short name T1178
Test name
Test status
Simulation time 44076194 ps
CPU time 2.89 seconds
Started Jan 21 03:18:30 PM PST 24
Finished Jan 21 03:18:38 PM PST 24
Peak memory 215152 kb
Host smart-b518bb6a-96e8-460d-a80c-97c5a6689596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629826931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2629826931 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.553082100
Short name T150
Test name
Test status
Simulation time 521949866 ps
CPU time 4.41 seconds
Started Jan 21 03:18:28 PM PST 24
Finished Jan 21 03:18:35 PM PST 24
Peak memory 215084 kb
Host smart-f151e103-43f8-4492-a735-e1bf84e0f29f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553082100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.553082
100 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3597896301
Short name T1170
Test name
Test status
Simulation time 420057544 ps
CPU time 9.46 seconds
Started Jan 21 03:18:53 PM PST 24
Finished Jan 21 03:19:04 PM PST 24
Peak memory 206840 kb
Host smart-1d12c1dc-75aa-4af1-b5b7-3d18f96fed96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597896301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3597896
301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.302006342
Short name T171
Test name
Test status
Simulation time 530355019 ps
CPU time 10.93 seconds
Started Jan 21 03:18:52 PM PST 24
Finished Jan 21 03:19:04 PM PST 24
Peak memory 206308 kb
Host smart-f360acae-d20e-42df-9f07-122f21ec5318
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302006342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.30200634
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1013458720
Short name T1150
Test name
Test status
Simulation time 26920172 ps
CPU time 0.93 seconds
Started Jan 21 03:18:36 PM PST 24
Finished Jan 21 03:18:39 PM PST 24
Peak memory 206640 kb
Host smart-9ec7330c-4b08-4df4-9d66-bdb7fb8417a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013458720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1013458
720 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3635393299
Short name T1156
Test name
Test status
Simulation time 43973870 ps
CPU time 1.72 seconds
Started Jan 21 03:18:59 PM PST 24
Finished Jan 21 03:19:03 PM PST 24
Peak memory 214932 kb
Host smart-315aacf4-7a5e-432d-bc5b-ea38c17652d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635393299 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3635393299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2367304414
Short name T1234
Test name
Test status
Simulation time 44203618 ps
CPU time 1.03 seconds
Started Jan 21 03:18:44 PM PST 24
Finished Jan 21 03:18:46 PM PST 24
Peak memory 206788 kb
Host smart-fb4aaaef-8c16-4ea9-9c03-ab69d23491c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367304414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2367304414 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.257021043
Short name T120
Test name
Test status
Simulation time 101862423 ps
CPU time 1.17 seconds
Started Jan 21 03:18:40 PM PST 24
Finished Jan 21 03:18:45 PM PST 24
Peak memory 215076 kb
Host smart-fa43ddab-b1ad-4732-865d-cf507233cab7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257021043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial
_access.257021043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3282595289
Short name T1268
Test name
Test status
Simulation time 36168343 ps
CPU time 0.72 seconds
Started Jan 21 03:18:42 PM PST 24
Finished Jan 21 03:18:45 PM PST 24
Peak memory 206664 kb
Host smart-eb973a31-f6c1-40ab-b1e2-d992d694fc01
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282595289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3282595289
+enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2654282273
Short name T1211
Test name
Test status
Simulation time 80629393 ps
CPU time 1.43 seconds
Started Jan 21 03:18:50 PM PST 24
Finished Jan 21 03:18:54 PM PST 24
Peak memory 206772 kb
Host smart-cc43b02b-e53a-4136-95e0-977dcb94d7ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654282273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2654282273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3994313689
Short name T1176
Test name
Test status
Simulation time 34958572 ps
CPU time 1.18 seconds
Started Jan 21 03:18:39 PM PST 24
Finished Jan 21 03:18:44 PM PST 24
Peak memory 215436 kb
Host smart-077d5caa-0415-4630-a791-f8894e83ea9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994313689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3994313689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2502248324
Short name T117
Test name
Test status
Simulation time 60379250 ps
CPU time 1.88 seconds
Started Jan 21 03:18:44 PM PST 24
Finished Jan 21 03:18:47 PM PST 24
Peak memory 215400 kb
Host smart-287a0c16-a408-4991-9da5-8e3ed506c4db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502248324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.2502248324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3541860050
Short name T1273
Test name
Test status
Simulation time 1018416242 ps
CPU time 2.95 seconds
Started Jan 21 03:18:38 PM PST 24
Finished Jan 21 03:18:42 PM PST 24
Peak memory 215108 kb
Host smart-2e0a55bd-e0ef-47e4-b3dd-9bd4b5c4a742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541860050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3541860050 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3028703976
Short name T1237
Test name
Test status
Simulation time 18986528 ps
CPU time 1.49 seconds
Started Jan 21 03:19:15 PM PST 24
Finished Jan 21 03:19:17 PM PST 24
Peak memory 215072 kb
Host smart-55e530b7-e56d-442c-a366-2d01b5a82ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028703976 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3028703976 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.222921210
Short name T1207
Test name
Test status
Simulation time 36219379 ps
CPU time 1.24 seconds
Started Jan 21 03:19:17 PM PST 24
Finished Jan 21 03:19:19 PM PST 24
Peak memory 206912 kb
Host smart-bbb385f9-9fde-4fc0-b3a0-4663805a39e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222921210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.222921210 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.3572342
Short name T1262
Test name
Test status
Simulation time 15947722 ps
CPU time 0.84 seconds
Started Jan 21 03:19:17 PM PST 24
Finished Jan 21 03:19:19 PM PST 24
Peak memory 206564 kb
Host smart-022f75ef-d83c-41dc-922a-623a2f057fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3572342 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1582304778
Short name T1264
Test name
Test status
Simulation time 182982187 ps
CPU time 2.51 seconds
Started Jan 21 03:19:15 PM PST 24
Finished Jan 21 03:19:19 PM PST 24
Peak memory 215016 kb
Host smart-53eea23e-d2cd-48cf-a505-f4dd353b7e5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582304778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.1582304778 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.993731340
Short name T1246
Test name
Test status
Simulation time 73086523 ps
CPU time 1.26 seconds
Started Jan 21 03:19:17 PM PST 24
Finished Jan 21 03:19:19 PM PST 24
Peak memory 215424 kb
Host smart-f61b5b7d-2c5b-4340-9d9c-aa5d02c50824
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993731340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_
errors.993731340 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3979914561
Short name T159
Test name
Test status
Simulation time 147281648 ps
CPU time 1.98 seconds
Started Jan 21 03:19:21 PM PST 24
Finished Jan 21 03:19:24 PM PST 24
Peak memory 223044 kb
Host smart-2e635e3b-d718-434d-bb27-97006325c728
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979914561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.3979914561 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.672957326
Short name T1228
Test name
Test status
Simulation time 235302544 ps
CPU time 3.53 seconds
Started Jan 21 03:19:16 PM PST 24
Finished Jan 21 03:19:21 PM PST 24
Peak memory 215100 kb
Host smart-41ea9289-d61a-44d1-9395-edebdf1bc562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672957326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.672957326 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3380415306
Short name T112
Test name
Test status
Simulation time 107401679 ps
CPU time 3.14 seconds
Started Jan 21 03:19:16 PM PST 24
Finished Jan 21 03:19:20 PM PST 24
Peak memory 206788 kb
Host smart-d1ce13f0-90d0-4500-a3d7-c138462953cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380415306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3380
415306 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2612760870
Short name T80
Test name
Test status
Simulation time 77670134 ps
CPU time 2.02 seconds
Started Jan 21 03:19:23 PM PST 24
Finished Jan 21 03:19:26 PM PST 24
Peak memory 215076 kb
Host smart-e4c62ce4-f925-40d1-8df0-baced9d01732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612760870 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2612760870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3214911757
Short name T1169
Test name
Test status
Simulation time 33485888 ps
CPU time 1.2 seconds
Started Jan 21 03:19:24 PM PST 24
Finished Jan 21 03:19:26 PM PST 24
Peak memory 206904 kb
Host smart-8c626968-55c8-43dd-80df-17b0d614f8e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214911757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3214911757 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3313883419
Short name T1177
Test name
Test status
Simulation time 61588058 ps
CPU time 1.64 seconds
Started Jan 21 03:19:26 PM PST 24
Finished Jan 21 03:19:28 PM PST 24
Peak memory 214964 kb
Host smart-a4de539c-80ad-4ddf-a8bc-2a3f9c8e0747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313883419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.3313883419 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3405797469
Short name T91
Test name
Test status
Simulation time 283313142 ps
CPU time 1.36 seconds
Started Jan 21 03:19:18 PM PST 24
Finished Jan 21 03:19:20 PM PST 24
Peak memory 215340 kb
Host smart-82777b3c-6230-44fd-99c5-737bab87cc58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405797469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.3405797469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3224913994
Short name T96
Test name
Test status
Simulation time 112904077 ps
CPU time 1.6 seconds
Started Jan 21 03:33:40 PM PST 24
Finished Jan 21 03:33:45 PM PST 24
Peak memory 215428 kb
Host smart-955b519f-20fc-4338-9884-264158bc6153
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224913994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.3224913994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1661042056
Short name T54
Test name
Test status
Simulation time 257064130 ps
CPU time 2.21 seconds
Started Jan 21 03:19:17 PM PST 24
Finished Jan 21 03:19:20 PM PST 24
Peak memory 215100 kb
Host smart-d3f2c250-046d-485d-abc2-16398753045c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661042056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1661042056 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2126259441
Short name T82
Test name
Test status
Simulation time 78072283 ps
CPU time 1.54 seconds
Started Jan 21 03:19:38 PM PST 24
Finished Jan 21 03:19:41 PM PST 24
Peak memory 214976 kb
Host smart-48b5ae36-697f-47ab-b523-c8b54ccbc9ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126259441 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2126259441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1615333440
Short name T1159
Test name
Test status
Simulation time 22028178 ps
CPU time 0.95 seconds
Started Jan 21 03:19:31 PM PST 24
Finished Jan 21 03:19:33 PM PST 24
Peak memory 206640 kb
Host smart-26c5ba98-e9e6-43a5-ad81-53a9c98d4b46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615333440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1615333440 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.98640235
Short name T1269
Test name
Test status
Simulation time 29924054 ps
CPU time 0.78 seconds
Started Jan 21 03:19:33 PM PST 24
Finished Jan 21 03:19:36 PM PST 24
Peak memory 206592 kb
Host smart-4337a659-ff32-4c10-bdea-3c9f54423fdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98640235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.98640235 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3487381504
Short name T1223
Test name
Test status
Simulation time 97725466 ps
CPU time 2.68 seconds
Started Jan 21 03:19:35 PM PST 24
Finished Jan 21 03:19:39 PM PST 24
Peak memory 206744 kb
Host smart-e80ef63e-1727-4acb-b45e-7854851372c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487381504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3487381504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2982518588
Short name T118
Test name
Test status
Simulation time 146059025 ps
CPU time 1.27 seconds
Started Jan 21 03:19:23 PM PST 24
Finished Jan 21 03:19:26 PM PST 24
Peak memory 215476 kb
Host smart-f4e6ea94-5194-49c4-975d-21cfbfb9bc02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982518588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2982518588 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2432226377
Short name T1219
Test name
Test status
Simulation time 59778122 ps
CPU time 1.79 seconds
Started Jan 21 03:19:26 PM PST 24
Finished Jan 21 03:19:29 PM PST 24
Peak memory 215352 kb
Host smart-d000f2cb-ed0e-467f-a840-2fe0433bfc1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432226377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.2432226377 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3638062703
Short name T1221
Test name
Test status
Simulation time 123502705 ps
CPU time 2.88 seconds
Started Jan 21 03:19:24 PM PST 24
Finished Jan 21 03:19:28 PM PST 24
Peak memory 215072 kb
Host smart-eb85dc5a-792e-46f8-84fe-556640f3950d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638062703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3638062703 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3141189160
Short name T1161
Test name
Test status
Simulation time 99805495 ps
CPU time 2.41 seconds
Started Jan 21 03:19:35 PM PST 24
Finished Jan 21 03:19:39 PM PST 24
Peak memory 222924 kb
Host smart-e20c4e46-2150-49ff-b667-89345cb5407b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141189160 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3141189160 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1901297372
Short name T1195
Test name
Test status
Simulation time 171282242 ps
CPU time 1.03 seconds
Started Jan 21 03:19:35 PM PST 24
Finished Jan 21 03:19:37 PM PST 24
Peak memory 206688 kb
Host smart-af9b6979-60de-43db-a38e-d2b749d72326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901297372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1901297372 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.1547551616
Short name T1238
Test name
Test status
Simulation time 39903824 ps
CPU time 0.77 seconds
Started Jan 21 03:19:34 PM PST 24
Finished Jan 21 03:19:36 PM PST 24
Peak memory 206568 kb
Host smart-d4e3409a-a9cd-4edf-a4bb-559691deb518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547551616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1547551616 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2871520641
Short name T1203
Test name
Test status
Simulation time 43763325 ps
CPU time 2.47 seconds
Started Jan 21 03:19:35 PM PST 24
Finished Jan 21 03:19:38 PM PST 24
Peak memory 215148 kb
Host smart-dd938aaa-bbd5-40a8-870b-4d471e408f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871520641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.2871520641 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3525914614
Short name T89
Test name
Test status
Simulation time 340686582 ps
CPU time 1.1 seconds
Started Jan 21 03:19:33 PM PST 24
Finished Jan 21 03:19:36 PM PST 24
Peak memory 207264 kb
Host smart-34fee34f-bab9-465d-9dea-6c47f5f45beb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525914614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3525914614 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1677550301
Short name T1270
Test name
Test status
Simulation time 363784531 ps
CPU time 1.95 seconds
Started Jan 21 03:19:36 PM PST 24
Finished Jan 21 03:19:39 PM PST 24
Peak memory 215464 kb
Host smart-9017ec77-d44c-490e-a668-66d774843146
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677550301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.1677550301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1920394718
Short name T1216
Test name
Test status
Simulation time 148461113 ps
CPU time 2.1 seconds
Started Jan 21 03:19:35 PM PST 24
Finished Jan 21 03:19:38 PM PST 24
Peak memory 215132 kb
Host smart-703ef3b0-fb66-47cb-9787-cbc009375608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920394718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1920394718 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.990196580
Short name T119
Test name
Test status
Simulation time 252452499 ps
CPU time 2.89 seconds
Started Jan 21 03:19:35 PM PST 24
Finished Jan 21 03:19:39 PM PST 24
Peak memory 214876 kb
Host smart-8514e7bb-bfc8-4bd2-bc45-c040206fbfb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990196580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.99019
6580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2574634286
Short name T1202
Test name
Test status
Simulation time 61839901 ps
CPU time 1.98 seconds
Started Jan 21 03:19:51 PM PST 24
Finished Jan 21 03:19:54 PM PST 24
Peak memory 222608 kb
Host smart-7d29a014-32a7-447e-837a-2f36f6e1ddb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574634286 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2574634286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2240773345
Short name T1192
Test name
Test status
Simulation time 76358402 ps
CPU time 0.94 seconds
Started Jan 21 03:19:50 PM PST 24
Finished Jan 21 03:19:52 PM PST 24
Peak memory 206636 kb
Host smart-ac262b4f-7dd5-413f-b5e3-b181a3f0aaa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240773345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2240773345 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.698252192
Short name T1180
Test name
Test status
Simulation time 24886659 ps
CPU time 0.87 seconds
Started Jan 21 03:19:46 PM PST 24
Finished Jan 21 03:19:48 PM PST 24
Peak memory 206516 kb
Host smart-90b82696-40a5-4c00-b927-4689f83ab6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698252192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.698252192 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.638707906
Short name T1272
Test name
Test status
Simulation time 223486195 ps
CPU time 1.79 seconds
Started Jan 21 03:19:48 PM PST 24
Finished Jan 21 03:19:50 PM PST 24
Peak memory 215044 kb
Host smart-89812133-453c-4854-b648-5f7ff8f47ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638707906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr
_outstanding.638707906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3194486984
Short name T1193
Test name
Test status
Simulation time 42411973 ps
CPU time 1.3 seconds
Started Jan 21 03:19:35 PM PST 24
Finished Jan 21 03:19:37 PM PST 24
Peak memory 215428 kb
Host smart-ce68f5ae-a62f-42bc-a6b7-68db0b54e664
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194486984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.3194486984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3893312866
Short name T1179
Test name
Test status
Simulation time 70351746 ps
CPU time 1.38 seconds
Started Jan 21 03:19:51 PM PST 24
Finished Jan 21 03:19:53 PM PST 24
Peak memory 214532 kb
Host smart-3a7b5915-9255-4330-a406-6945453e1177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893312866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3893312866 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1975912030
Short name T113
Test name
Test status
Simulation time 116346385 ps
CPU time 2.75 seconds
Started Jan 21 03:19:59 PM PST 24
Finished Jan 21 03:20:02 PM PST 24
Peak memory 215060 kb
Host smart-bd574c96-01f3-4d15-96bd-09a9cc632306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975912030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1975
912030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1830142420
Short name T79
Test name
Test status
Simulation time 54385094 ps
CPU time 1.45 seconds
Started Jan 21 03:19:50 PM PST 24
Finished Jan 21 03:19:52 PM PST 24
Peak memory 215088 kb
Host smart-212b87d1-e081-4fec-8581-d76a2b289283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830142420 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1830142420 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2776191637
Short name T1191
Test name
Test status
Simulation time 16778697 ps
CPU time 0.96 seconds
Started Jan 21 03:19:59 PM PST 24
Finished Jan 21 03:20:01 PM PST 24
Peak memory 206580 kb
Host smart-f0c6d531-f2aa-4d43-947e-b7bcc7d86c71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776191637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2776191637 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.3485820593
Short name T1187
Test name
Test status
Simulation time 26418000 ps
CPU time 0.78 seconds
Started Jan 21 03:19:47 PM PST 24
Finished Jan 21 03:19:49 PM PST 24
Peak memory 206492 kb
Host smart-bd9825c1-d64a-4d30-ae52-6c523a648f3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485820593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3485820593 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2820201098
Short name T127
Test name
Test status
Simulation time 44193570 ps
CPU time 2.34 seconds
Started Jan 21 03:19:49 PM PST 24
Finished Jan 21 03:19:52 PM PST 24
Peak memory 206860 kb
Host smart-4362a998-6af1-4e25-8f1d-b6df00c6c780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820201098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.2820201098 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3220315691
Short name T94
Test name
Test status
Simulation time 206821148 ps
CPU time 1.05 seconds
Started Jan 21 03:19:47 PM PST 24
Finished Jan 21 03:19:49 PM PST 24
Peak memory 215112 kb
Host smart-e650ca29-a9e0-4b32-b292-52692c039381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220315691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3220315691 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.587536032
Short name T1184
Test name
Test status
Simulation time 358545319 ps
CPU time 1.74 seconds
Started Jan 21 03:19:50 PM PST 24
Finished Jan 21 03:19:53 PM PST 24
Peak memory 215140 kb
Host smart-9e0854b5-4152-4aa4-a22f-cadd2c1749fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587536032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac
_shadow_reg_errors_with_csr_rw.587536032 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1862701137
Short name T1212
Test name
Test status
Simulation time 32345463 ps
CPU time 1.67 seconds
Started Jan 21 03:19:48 PM PST 24
Finished Jan 21 03:19:51 PM PST 24
Peak memory 215308 kb
Host smart-ddd4b80d-cd3a-4143-9f3c-ba75be3a30cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862701137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1862701137 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.80558647
Short name T1200
Test name
Test status
Simulation time 90664483 ps
CPU time 2.64 seconds
Started Jan 21 03:19:48 PM PST 24
Finished Jan 21 03:19:52 PM PST 24
Peak memory 215060 kb
Host smart-a619af39-9813-4caf-b8d9-25a3edd921b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80558647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.805586
47 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3226694756
Short name T1231
Test name
Test status
Simulation time 120968029 ps
CPU time 1.74 seconds
Started Jan 21 03:19:44 PM PST 24
Finished Jan 21 03:19:46 PM PST 24
Peak memory 223144 kb
Host smart-a66cc1a8-9c0a-418d-878d-9bc4f69c3e2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226694756 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3226694756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1475094701
Short name T1258
Test name
Test status
Simulation time 30843662 ps
CPU time 1.13 seconds
Started Jan 21 03:19:47 PM PST 24
Finished Jan 21 03:19:49 PM PST 24
Peak memory 206912 kb
Host smart-b4edcdad-0c8c-4b0c-bf0b-7a23ed624a79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475094701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1475094701 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2573078574
Short name T59
Test name
Test status
Simulation time 24529738 ps
CPU time 0.78 seconds
Started Jan 21 03:19:50 PM PST 24
Finished Jan 21 03:19:51 PM PST 24
Peak memory 206560 kb
Host smart-96111205-6b3d-4464-b64b-7a49188e45db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573078574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2573078574 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.949633984
Short name T1162
Test name
Test status
Simulation time 171147068 ps
CPU time 1.59 seconds
Started Jan 21 03:19:44 PM PST 24
Finished Jan 21 03:19:47 PM PST 24
Peak memory 206740 kb
Host smart-fafb40d9-d4c0-41d0-9565-d0e3a18eae4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949633984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.949633984 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1263849246
Short name T1241
Test name
Test status
Simulation time 134101316 ps
CPU time 1.26 seconds
Started Jan 21 03:19:45 PM PST 24
Finished Jan 21 03:19:47 PM PST 24
Peak memory 215360 kb
Host smart-916152bd-8cb3-419c-a112-969dc718f159
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263849246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.1263849246 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1931946717
Short name T1259
Test name
Test status
Simulation time 407430659 ps
CPU time 3.2 seconds
Started Jan 21 03:19:51 PM PST 24
Finished Jan 21 03:19:55 PM PST 24
Peak memory 215436 kb
Host smart-716dec42-b9d8-4c71-8fb5-87af0f0d947f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931946717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.1931946717 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3183959291
Short name T1168
Test name
Test status
Simulation time 85588840 ps
CPU time 2.09 seconds
Started Jan 21 03:19:51 PM PST 24
Finished Jan 21 03:19:55 PM PST 24
Peak memory 215120 kb
Host smart-3ed11f54-90b6-4713-8072-bf84f66ea0e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183959291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3183959291 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2874984713
Short name T149
Test name
Test status
Simulation time 418990120 ps
CPU time 4.14 seconds
Started Jan 21 03:19:44 PM PST 24
Finished Jan 21 03:19:49 PM PST 24
Peak memory 214928 kb
Host smart-98fd521d-10c3-4c01-b692-3b7fe5dee525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874984713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2874
984713 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4097067516
Short name T1153
Test name
Test status
Simulation time 90369198 ps
CPU time 1.34 seconds
Started Jan 21 03:20:01 PM PST 24
Finished Jan 21 03:20:03 PM PST 24
Peak memory 215084 kb
Host smart-a78771f8-9b0c-438d-9532-ade6e0f108da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097067516 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.4097067516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.595020795
Short name T161
Test name
Test status
Simulation time 37507600 ps
CPU time 1.23 seconds
Started Jan 21 03:20:00 PM PST 24
Finished Jan 21 03:20:02 PM PST 24
Peak memory 206856 kb
Host smart-2c7ef558-2ba7-4c5a-aa28-9530d9a4782f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595020795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.595020795 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.1088659615
Short name T1225
Test name
Test status
Simulation time 33648511 ps
CPU time 0.75 seconds
Started Jan 21 03:19:50 PM PST 24
Finished Jan 21 03:19:52 PM PST 24
Peak memory 206516 kb
Host smart-1f7161ba-8592-4203-b000-3b9e802af3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088659615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1088659615 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2960111992
Short name T1271
Test name
Test status
Simulation time 92814568 ps
CPU time 1.51 seconds
Started Jan 21 03:20:01 PM PST 24
Finished Jan 21 03:20:03 PM PST 24
Peak memory 206428 kb
Host smart-46622a27-ac64-4f55-aed9-9218e027b5c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960111992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2960111992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3623873305
Short name T1227
Test name
Test status
Simulation time 41423519 ps
CPU time 1.31 seconds
Started Jan 21 03:19:50 PM PST 24
Finished Jan 21 03:19:52 PM PST 24
Peak memory 215404 kb
Host smart-54cd48f5-eb34-4b0b-8b6c-81ab6fc9dfee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623873305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.3623873305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.932210702
Short name T1215
Test name
Test status
Simulation time 118696436 ps
CPU time 1.37 seconds
Started Jan 21 03:19:53 PM PST 24
Finished Jan 21 03:19:55 PM PST 24
Peak memory 215140 kb
Host smart-b789123a-ded1-478f-9c7d-fdac775d424b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932210702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.932210702 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3618890830
Short name T1248
Test name
Test status
Simulation time 130775873 ps
CPU time 2.35 seconds
Started Jan 21 03:19:58 PM PST 24
Finished Jan 21 03:20:01 PM PST 24
Peak memory 223036 kb
Host smart-aad46536-f516-4582-8e80-6420fb60b8b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618890830 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3618890830 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.838528914
Short name T1189
Test name
Test status
Simulation time 106994607 ps
CPU time 1.17 seconds
Started Jan 21 03:19:55 PM PST 24
Finished Jan 21 03:19:57 PM PST 24
Peak memory 206908 kb
Host smart-60ca6bea-fb88-4273-aaa2-1bf240bd2050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838528914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.838528914 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2411924526
Short name T1206
Test name
Test status
Simulation time 13398904 ps
CPU time 0.75 seconds
Started Jan 21 03:19:59 PM PST 24
Finished Jan 21 03:20:01 PM PST 24
Peak memory 206500 kb
Host smart-dfd4e4ca-e7dd-4c8d-b283-a601cfdaf227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411924526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2411924526 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2078932480
Short name T1174
Test name
Test status
Simulation time 665287554 ps
CPU time 2.6 seconds
Started Jan 21 03:19:55 PM PST 24
Finished Jan 21 03:19:58 PM PST 24
Peak memory 215036 kb
Host smart-99a03c3c-04b7-49fb-955d-e8e4ff2f4f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078932480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.2078932480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1206462184
Short name T1194
Test name
Test status
Simulation time 52768126 ps
CPU time 1.29 seconds
Started Jan 21 03:20:01 PM PST 24
Finished Jan 21 03:20:04 PM PST 24
Peak memory 215356 kb
Host smart-a4d013a5-1497-4ed7-a20d-cc8637bfcbcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206462184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1206462184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.945374507
Short name T95
Test name
Test status
Simulation time 1024854470 ps
CPU time 3.1 seconds
Started Jan 21 03:19:53 PM PST 24
Finished Jan 21 03:19:57 PM PST 24
Peak memory 223576 kb
Host smart-538b60e7-f8b3-4b8e-81e5-e879d933612e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945374507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac
_shadow_reg_errors_with_csr_rw.945374507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.776750685
Short name T1261
Test name
Test status
Simulation time 24075952 ps
CPU time 1.48 seconds
Started Jan 21 04:00:36 PM PST 24
Finished Jan 21 04:00:39 PM PST 24
Peak memory 215096 kb
Host smart-2d5546ef-ebf3-45da-a6ff-bec03f4784c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776750685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.776750685 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1657084120
Short name T147
Test name
Test status
Simulation time 188572786 ps
CPU time 2.51 seconds
Started Jan 21 03:20:00 PM PST 24
Finished Jan 21 03:20:04 PM PST 24
Peak memory 217176 kb
Host smart-c69ada46-37cc-4d15-af20-9f6b0f7813fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657084120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1657
084120 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3709967726
Short name T1236
Test name
Test status
Simulation time 45776136 ps
CPU time 1.31 seconds
Started Jan 21 03:20:00 PM PST 24
Finished Jan 21 03:20:03 PM PST 24
Peak memory 214880 kb
Host smart-11093e7d-a332-4a7c-89a3-6fc5297091de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709967726 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3709967726 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.193981013
Short name T128
Test name
Test status
Simulation time 30127045 ps
CPU time 1.08 seconds
Started Jan 21 04:04:50 PM PST 24
Finished Jan 21 04:04:53 PM PST 24
Peak memory 206880 kb
Host smart-0c436e54-1a00-4919-bbc9-d97cf3a49e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193981013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.193981013 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.4253691926
Short name T165
Test name
Test status
Simulation time 20845541 ps
CPU time 0.75 seconds
Started Jan 21 03:20:01 PM PST 24
Finished Jan 21 03:20:03 PM PST 24
Peak memory 206516 kb
Host smart-a1480348-d2e3-4c98-85c2-127f758a3e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253691926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.4253691926 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2426677452
Short name T1182
Test name
Test status
Simulation time 65576498 ps
CPU time 1.8 seconds
Started Jan 21 03:47:25 PM PST 24
Finished Jan 21 03:47:29 PM PST 24
Peak memory 215040 kb
Host smart-5ee96497-d9e0-43d5-a907-4cc1bb07fc38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426677452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.2426677452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3362917330
Short name T100
Test name
Test status
Simulation time 38335247 ps
CPU time 1.05 seconds
Started Jan 21 03:19:55 PM PST 24
Finished Jan 21 03:19:57 PM PST 24
Peak memory 215116 kb
Host smart-4e9e0cfe-4617-4e3c-9f30-8f926ffc7756
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362917330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3362917330 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.314890326
Short name T93
Test name
Test status
Simulation time 215404546 ps
CPU time 2.81 seconds
Started Jan 21 03:20:00 PM PST 24
Finished Jan 21 03:20:04 PM PST 24
Peak memory 215416 kb
Host smart-f0d68661-722e-4a0a-a203-2739ac8d6146
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314890326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac
_shadow_reg_errors_with_csr_rw.314890326 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3053430211
Short name T78
Test name
Test status
Simulation time 421726518 ps
CPU time 2.97 seconds
Started Jan 21 03:20:00 PM PST 24
Finished Jan 21 03:20:04 PM PST 24
Peak memory 215076 kb
Host smart-4b68498c-64c2-4e11-ad58-4565a912fdfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053430211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3053430211 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1968962496
Short name T1167
Test name
Test status
Simulation time 234290653 ps
CPU time 2.47 seconds
Started Jan 21 03:19:56 PM PST 24
Finished Jan 21 03:19:59 PM PST 24
Peak memory 215040 kb
Host smart-a1903ea8-82be-4619-ab15-4dbfeebad9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968962496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1968
962496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.1897969811
Short name T1247
Test name
Test status
Simulation time 468025464 ps
CPU time 10.8 seconds
Started Jan 21 03:18:49 PM PST 24
Finished Jan 21 03:19:02 PM PST 24
Peak memory 206848 kb
Host smart-f312be83-43fd-4e3e-aede-bd8e83e17b69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897969811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1897969
811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2915892998
Short name T55
Test name
Test status
Simulation time 3723123338 ps
CPU time 12.31 seconds
Started Jan 21 03:18:47 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 206940 kb
Host smart-d8e02d7c-8e63-4950-9357-219dc156b9b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915892998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2915892
998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2400667253
Short name T1218
Test name
Test status
Simulation time 53729740 ps
CPU time 1.2 seconds
Started Jan 21 03:18:50 PM PST 24
Finished Jan 21 03:18:53 PM PST 24
Peak memory 215052 kb
Host smart-5a71f5ad-6f0b-4209-9b2f-f8f2d029c7e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400667253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2400667
253 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2113095349
Short name T1217
Test name
Test status
Simulation time 206552188 ps
CPU time 1.71 seconds
Started Jan 21 03:18:52 PM PST 24
Finished Jan 21 03:18:55 PM PST 24
Peak memory 214592 kb
Host smart-9b6aac02-7561-44c2-8b78-34b785cb6814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113095349 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2113095349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.492361799
Short name T1266
Test name
Test status
Simulation time 90545491 ps
CPU time 1.16 seconds
Started Jan 21 03:18:53 PM PST 24
Finished Jan 21 03:18:55 PM PST 24
Peak memory 206716 kb
Host smart-a9739944-67c0-4460-a1f3-b3d4bba4ff79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492361799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.492361799 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.1687703726
Short name T143
Test name
Test status
Simulation time 32960039 ps
CPU time 0.75 seconds
Started Jan 21 03:18:59 PM PST 24
Finished Jan 21 03:19:02 PM PST 24
Peak memory 206420 kb
Host smart-cc127b90-bb32-4ee8-ab09-c315c2120b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687703726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1687703726 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1639737216
Short name T123
Test name
Test status
Simulation time 27959778 ps
CPU time 1.2 seconds
Started Jan 21 03:18:51 PM PST 24
Finished Jan 21 03:18:54 PM PST 24
Peak memory 214972 kb
Host smart-78399336-7cc6-4586-a943-a0fc9004da51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639737216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.1639737216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.2228067236
Short name T1233
Test name
Test status
Simulation time 33320811 ps
CPU time 0.69 seconds
Started Jan 21 03:18:49 PM PST 24
Finished Jan 21 03:18:51 PM PST 24
Peak memory 206624 kb
Host smart-a6be27b5-71fd-4183-b6aa-d68d28841623
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228067236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2228067236
+enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2990681656
Short name T166
Test name
Test status
Simulation time 28679437 ps
CPU time 1.59 seconds
Started Jan 21 03:18:56 PM PST 24
Finished Jan 21 03:18:58 PM PST 24
Peak memory 215108 kb
Host smart-704c4847-297a-4cc6-a0ca-56087da0193c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990681656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2990681656 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4226818480
Short name T1242
Test name
Test status
Simulation time 80641651 ps
CPU time 1 seconds
Started Jan 21 03:18:47 PM PST 24
Finished Jan 21 03:18:50 PM PST 24
Peak memory 215220 kb
Host smart-a1ab52c8-1bcf-46f6-a4e7-d4b552ebff43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226818480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.4226818480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2867169599
Short name T1243
Test name
Test status
Simulation time 45097924 ps
CPU time 1.82 seconds
Started Jan 21 03:18:49 PM PST 24
Finished Jan 21 03:18:52 PM PST 24
Peak memory 215000 kb
Host smart-3ee9d9b5-f573-4307-81e8-948dd95a6b35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867169599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2867169599 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3382965773
Short name T1213
Test name
Test status
Simulation time 347930469 ps
CPU time 4.11 seconds
Started Jan 21 03:18:56 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 217476 kb
Host smart-8dd83045-057b-4934-bf6c-3cdc15d2ca20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382965773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.33829
65773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.1457354660
Short name T1230
Test name
Test status
Simulation time 16924405 ps
CPU time 0.78 seconds
Started Jan 21 03:19:57 PM PST 24
Finished Jan 21 03:19:58 PM PST 24
Peak memory 206516 kb
Host smart-3f747ac1-b749-4b09-99ed-0bc259d07b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457354660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1457354660 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.1326136757
Short name T1151
Test name
Test status
Simulation time 71758799 ps
CPU time 0.81 seconds
Started Jan 21 03:20:01 PM PST 24
Finished Jan 21 03:20:03 PM PST 24
Peak memory 205992 kb
Host smart-7aa675a4-8bfa-463d-944e-ce63f09c990d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326136757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1326136757 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.399610022
Short name T1199
Test name
Test status
Simulation time 14637540 ps
CPU time 0.79 seconds
Started Jan 21 03:38:12 PM PST 24
Finished Jan 21 03:38:13 PM PST 24
Peak memory 206572 kb
Host smart-fd6232ff-c7f0-4b68-9db3-3386264826d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399610022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.399610022 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3764793362
Short name T121
Test name
Test status
Simulation time 20906956 ps
CPU time 0.76 seconds
Started Jan 21 03:19:59 PM PST 24
Finished Jan 21 03:20:01 PM PST 24
Peak memory 206500 kb
Host smart-a32b8f18-cfa1-45c5-a19c-19b66b8b81d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764793362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3764793362 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2771191506
Short name T1251
Test name
Test status
Simulation time 12755229 ps
CPU time 0.79 seconds
Started Jan 21 03:19:59 PM PST 24
Finished Jan 21 03:20:01 PM PST 24
Peak memory 206496 kb
Host smart-0dc7c72c-7e19-4422-9f67-69080f97f294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771191506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2771191506 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2095972291
Short name T122
Test name
Test status
Simulation time 39737897 ps
CPU time 0.82 seconds
Started Jan 21 03:20:00 PM PST 24
Finished Jan 21 03:20:02 PM PST 24
Peak memory 206568 kb
Host smart-2b5a5cff-dafc-454a-9ed6-9adbd907f43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095972291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2095972291 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.468712530
Short name T1244
Test name
Test status
Simulation time 83019377 ps
CPU time 0.8 seconds
Started Jan 21 03:44:23 PM PST 24
Finished Jan 21 03:44:25 PM PST 24
Peak memory 206500 kb
Host smart-fd5c7843-2d07-47d3-adf0-27ee8854738b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468712530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.468712530 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.894315048
Short name T1250
Test name
Test status
Simulation time 37468203 ps
CPU time 0.76 seconds
Started Jan 21 03:40:37 PM PST 24
Finished Jan 21 03:40:39 PM PST 24
Peak memory 206576 kb
Host smart-ef758c59-35ee-401d-919e-2c5465bf6405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894315048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.894315048 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.4032160272
Short name T56
Test name
Test status
Simulation time 21563456 ps
CPU time 0.75 seconds
Started Jan 21 04:02:29 PM PST 24
Finished Jan 21 04:02:38 PM PST 24
Peak memory 206576 kb
Host smart-456e3cf3-3c89-4df8-ba95-6bf7f485ecc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032160272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4032160272 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2626566753
Short name T170
Test name
Test status
Simulation time 870998311 ps
CPU time 10.52 seconds
Started Jan 21 03:18:56 PM PST 24
Finished Jan 21 03:19:08 PM PST 24
Peak memory 206804 kb
Host smart-2b780d6e-5db2-42e4-aa9f-845d8d6a2c03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626566753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2626566
753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.268987322
Short name T1163
Test name
Test status
Simulation time 551849842 ps
CPU time 8.83 seconds
Started Jan 21 03:18:59 PM PST 24
Finished Jan 21 03:19:10 PM PST 24
Peak memory 206864 kb
Host smart-19bfc3b0-d739-40b5-a3a9-c266126ddec9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268987322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.26898732
2 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.533407770
Short name T1260
Test name
Test status
Simulation time 73478424 ps
CPU time 1.01 seconds
Started Jan 21 03:18:53 PM PST 24
Finished Jan 21 03:18:55 PM PST 24
Peak memory 206464 kb
Host smart-f4163675-a497-4de9-9291-aa28de28f2b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533407770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.53340777
0 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3027143256
Short name T51
Test name
Test status
Simulation time 28333221 ps
CPU time 1.17 seconds
Started Jan 21 03:18:54 PM PST 24
Finished Jan 21 03:18:56 PM PST 24
Peak memory 215044 kb
Host smart-883bcbb9-c51c-410b-85ca-fbbf1743de28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027143256 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3027143256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.283221584
Short name T1171
Test name
Test status
Simulation time 34937994 ps
CPU time 1 seconds
Started Jan 21 03:18:49 PM PST 24
Finished Jan 21 03:18:51 PM PST 24
Peak memory 206636 kb
Host smart-698eb38a-fc98-423d-b7fd-7f4a7db3de8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283221584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.283221584 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1601024468
Short name T168
Test name
Test status
Simulation time 49533150 ps
CPU time 0.78 seconds
Started Jan 21 03:18:52 PM PST 24
Finished Jan 21 03:18:54 PM PST 24
Peak memory 206492 kb
Host smart-0bf71370-c48d-475d-94c9-fdf456189814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601024468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1601024468 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.475893772
Short name T84
Test name
Test status
Simulation time 28199050 ps
CPU time 1.18 seconds
Started Jan 21 03:18:48 PM PST 24
Finished Jan 21 03:18:51 PM PST 24
Peak memory 215004 kb
Host smart-56d98c0b-21e8-43bd-98da-ff65449c8240
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475893772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial
_access.475893772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1230611646
Short name T1158
Test name
Test status
Simulation time 26274557 ps
CPU time 0.71 seconds
Started Jan 21 03:18:46 PM PST 24
Finished Jan 21 03:18:49 PM PST 24
Peak memory 206640 kb
Host smart-1621c370-166e-41af-bac3-0d31bc0e92ab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230611646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1230611646
+enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1399926542
Short name T1210
Test name
Test status
Simulation time 186469040 ps
CPU time 2.2 seconds
Started Jan 21 03:18:48 PM PST 24
Finished Jan 21 03:18:52 PM PST 24
Peak memory 215020 kb
Host smart-51870d5d-55b6-4d9f-88dc-5deb0e6cafae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399926542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1399926542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2729665147
Short name T116
Test name
Test status
Simulation time 98700222 ps
CPU time 1.13 seconds
Started Jan 21 03:39:43 PM PST 24
Finished Jan 21 03:39:45 PM PST 24
Peak memory 206872 kb
Host smart-93febd8a-af9a-4ae0-a299-a9bbaf74326b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729665147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.2729665147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4115792686
Short name T1267
Test name
Test status
Simulation time 119553365 ps
CPU time 2.98 seconds
Started Jan 21 03:18:49 PM PST 24
Finished Jan 21 03:18:53 PM PST 24
Peak memory 215304 kb
Host smart-1438d703-8ac0-4bba-ad65-dd6ee897c4e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115792686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.4115792686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.98565440
Short name T106
Test name
Test status
Simulation time 29747835 ps
CPU time 2.06 seconds
Started Jan 21 04:01:16 PM PST 24
Finished Jan 21 04:01:20 PM PST 24
Peak memory 215024 kb
Host smart-ab226c68-114d-43da-82cf-8ffee6d24c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98565440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.98565440 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1288119406
Short name T110
Test name
Test status
Simulation time 208354845 ps
CPU time 3.05 seconds
Started Jan 21 03:18:51 PM PST 24
Finished Jan 21 03:18:56 PM PST 24
Peak memory 206724 kb
Host smart-c24ac998-3608-4c5f-a97b-0a542ca905e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288119406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.12881
19406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.683807804
Short name T1229
Test name
Test status
Simulation time 11557372 ps
CPU time 0.77 seconds
Started Jan 21 03:20:01 PM PST 24
Finished Jan 21 03:20:03 PM PST 24
Peak memory 206516 kb
Host smart-d0a4266c-b866-4224-b854-0dffec66ef2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683807804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.683807804 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.38584507
Short name T144
Test name
Test status
Simulation time 38134765 ps
CPU time 0.75 seconds
Started Jan 21 03:19:55 PM PST 24
Finished Jan 21 03:19:57 PM PST 24
Peak memory 206616 kb
Host smart-92668143-a285-4824-af43-8fabf025449e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38584507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.38584507 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.1373229833
Short name T146
Test name
Test status
Simulation time 24213318 ps
CPU time 0.78 seconds
Started Jan 21 03:33:54 PM PST 24
Finished Jan 21 03:34:02 PM PST 24
Peak memory 206780 kb
Host smart-756776d7-0f97-402a-af67-1121c25d2ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373229833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1373229833 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.172773466
Short name T1152
Test name
Test status
Simulation time 24708048 ps
CPU time 0.74 seconds
Started Jan 21 04:02:18 PM PST 24
Finished Jan 21 04:02:24 PM PST 24
Peak memory 206564 kb
Host smart-222473a3-77cb-4ef7-810d-5bf411c731cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172773466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.172773466 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.3341725587
Short name T169
Test name
Test status
Simulation time 13450219 ps
CPU time 0.74 seconds
Started Jan 21 03:19:58 PM PST 24
Finished Jan 21 03:19:59 PM PST 24
Peak memory 206500 kb
Host smart-546ac5a5-3cf6-404f-af22-31d7f178fa2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341725587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3341725587 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.1970162664
Short name T1155
Test name
Test status
Simulation time 11324361 ps
CPU time 0.73 seconds
Started Jan 21 03:19:53 PM PST 24
Finished Jan 21 03:19:55 PM PST 24
Peak memory 206540 kb
Host smart-990fa76d-82d3-46fb-a99a-bf3be21faa29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970162664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1970162664 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.551312138
Short name T142
Test name
Test status
Simulation time 137806674 ps
CPU time 0.85 seconds
Started Jan 21 03:20:06 PM PST 24
Finished Jan 21 03:20:07 PM PST 24
Peak memory 206572 kb
Host smart-6f332da8-9534-4847-bf1c-6118787cf76d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551312138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.551312138 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2680245178
Short name T1188
Test name
Test status
Simulation time 17877404 ps
CPU time 0.75 seconds
Started Jan 21 03:20:06 PM PST 24
Finished Jan 21 03:20:08 PM PST 24
Peak memory 206548 kb
Host smart-da8f1e74-b06a-4b9d-98fa-3d58d9d4d540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680245178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2680245178 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3746198508
Short name T158
Test name
Test status
Simulation time 104149997 ps
CPU time 0.78 seconds
Started Jan 21 03:20:04 PM PST 24
Finished Jan 21 03:20:06 PM PST 24
Peak memory 206464 kb
Host smart-4ebf68eb-ef11-48c9-ab98-98f277a231e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746198508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3746198508 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.4052944146
Short name T1257
Test name
Test status
Simulation time 17562115 ps
CPU time 0.76 seconds
Started Jan 21 03:20:08 PM PST 24
Finished Jan 21 03:20:10 PM PST 24
Peak memory 206580 kb
Host smart-5772537f-afbb-4209-8170-bcd4713076d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052944146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.4052944146 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2749012860
Short name T1252
Test name
Test status
Simulation time 1647026944 ps
CPU time 6.37 seconds
Started Jan 21 03:19:03 PM PST 24
Finished Jan 21 03:19:11 PM PST 24
Peak memory 206940 kb
Host smart-ecd8beea-296f-45d5-b1cf-5b9ca02555a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749012860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2749012
860 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2351575542
Short name T162
Test name
Test status
Simulation time 1210868851 ps
CPU time 16.77 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:16 PM PST 24
Peak memory 206856 kb
Host smart-97a45af0-b5e8-4ce4-a3c6-e5ceab60f39e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351575542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2351575
542 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1100905364
Short name T1175
Test name
Test status
Simulation time 40161194 ps
CPU time 1.16 seconds
Started Jan 21 03:19:00 PM PST 24
Finished Jan 21 03:19:04 PM PST 24
Peak memory 206744 kb
Host smart-534f3eaa-7908-477b-b4fe-5ce871bde237
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100905364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1100905
364 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.315402255
Short name T1245
Test name
Test status
Simulation time 84979021 ps
CPU time 1.32 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:00 PM PST 24
Peak memory 215044 kb
Host smart-3f24f6d3-db78-435a-88ae-a32428e7d48f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315402255 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.315402255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3083432855
Short name T114
Test name
Test status
Simulation time 102567003 ps
CPU time 1.18 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:00 PM PST 24
Peak memory 215264 kb
Host smart-b95abf86-aa6b-43d1-b6c5-722ae7474e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083432855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3083432855 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.2793466407
Short name T60
Test name
Test status
Simulation time 48354369 ps
CPU time 0.75 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:00 PM PST 24
Peak memory 206540 kb
Host smart-641814dd-4285-40be-9867-086915d0221d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793466407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2793466407 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3815732393
Short name T125
Test name
Test status
Simulation time 157453111 ps
CPU time 1.44 seconds
Started Jan 21 03:19:03 PM PST 24
Finished Jan 21 03:19:06 PM PST 24
Peak memory 215000 kb
Host smart-03771c4d-4205-4e5b-a145-d3bb3c45d2de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815732393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3815732393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1031518436
Short name T1253
Test name
Test status
Simulation time 13989253 ps
CPU time 0.78 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:00 PM PST 24
Peak memory 206576 kb
Host smart-f1fb293b-62f2-4412-bb2a-dab1afe74901
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031518436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1031518436
+enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3751421908
Short name T126
Test name
Test status
Simulation time 741880096 ps
CPU time 2.81 seconds
Started Jan 21 03:35:13 PM PST 24
Finished Jan 21 03:35:18 PM PST 24
Peak memory 215068 kb
Host smart-109c57ca-b340-456d-a280-5cc940871d7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751421908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3751421908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3836476586
Short name T97
Test name
Test status
Simulation time 64816542 ps
CPU time 1.01 seconds
Started Jan 21 03:18:53 PM PST 24
Finished Jan 21 03:18:55 PM PST 24
Peak memory 206900 kb
Host smart-116d596a-038c-436e-bbdd-5fe9000d7f3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836476586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.3836476586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4029397478
Short name T1164
Test name
Test status
Simulation time 61181480 ps
CPU time 1.85 seconds
Started Jan 21 03:18:48 PM PST 24
Finished Jan 21 03:18:51 PM PST 24
Peak memory 215308 kb
Host smart-c3b81773-f1b4-4619-b042-63af94bbecb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029397478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.4029397478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.1843730878
Short name T81
Test name
Test status
Simulation time 104455009 ps
CPU time 2.75 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:02 PM PST 24
Peak memory 215120 kb
Host smart-44ccfe33-3461-4fb1-b391-c59387429525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843730878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1843730878 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.75835851
Short name T160
Test name
Test status
Simulation time 44354231 ps
CPU time 0.78 seconds
Started Jan 21 03:20:02 PM PST 24
Finished Jan 21 03:20:04 PM PST 24
Peak memory 206492 kb
Host smart-d4c8b232-656e-4bc0-bf95-e2aa65d503da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75835851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.75835851 +enable_mas
king=0 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.1543635787
Short name T1157
Test name
Test status
Simulation time 40331522 ps
CPU time 0.75 seconds
Started Jan 21 03:20:06 PM PST 24
Finished Jan 21 03:20:08 PM PST 24
Peak memory 206568 kb
Host smart-43694c20-e37e-4865-a082-617eefdca646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543635787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1543635787 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.2423100982
Short name T145
Test name
Test status
Simulation time 15640452 ps
CPU time 0.79 seconds
Started Jan 21 03:20:04 PM PST 24
Finished Jan 21 03:20:06 PM PST 24
Peak memory 206560 kb
Host smart-5408df50-5514-4032-8aa6-e068d3a077a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423100982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2423100982 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.3838577145
Short name T1173
Test name
Test status
Simulation time 23738775 ps
CPU time 0.88 seconds
Started Jan 21 03:20:06 PM PST 24
Finished Jan 21 03:20:08 PM PST 24
Peak memory 206568 kb
Host smart-c4cb4125-dd3c-494d-a05f-32c51ec9a6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838577145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3838577145 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3139131411
Short name T1254
Test name
Test status
Simulation time 167425141 ps
CPU time 0.75 seconds
Started Jan 21 03:20:07 PM PST 24
Finished Jan 21 03:20:09 PM PST 24
Peak memory 206492 kb
Host smart-29360dfe-5b32-44ad-a0df-a5def710d78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139131411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3139131411 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.101552049
Short name T1239
Test name
Test status
Simulation time 15521209 ps
CPU time 0.79 seconds
Started Jan 21 03:20:04 PM PST 24
Finished Jan 21 03:20:06 PM PST 24
Peak memory 206572 kb
Host smart-d1cd7d91-7d5a-4d5f-ac7b-0577cf20f091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101552049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.101552049 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1292854610
Short name T164
Test name
Test status
Simulation time 33317759 ps
CPU time 0.78 seconds
Started Jan 21 03:20:05 PM PST 24
Finished Jan 21 03:20:07 PM PST 24
Peak memory 206516 kb
Host smart-0e34ccfc-ce5f-498f-8b2e-cb4f359b5b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292854610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1292854610 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.3091608580
Short name T1222
Test name
Test status
Simulation time 38961869 ps
CPU time 0.77 seconds
Started Jan 21 03:20:07 PM PST 24
Finished Jan 21 03:20:08 PM PST 24
Peak memory 206548 kb
Host smart-5fab2f68-9054-4e30-9b3c-0d25b07b1996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091608580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3091608580 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.3126747047
Short name T1201
Test name
Test status
Simulation time 11512267 ps
CPU time 0.79 seconds
Started Jan 21 03:20:08 PM PST 24
Finished Jan 21 03:20:10 PM PST 24
Peak memory 206492 kb
Host smart-cf503d1a-f18a-45e2-bcd0-e5d1be69040e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126747047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3126747047 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1102077922
Short name T1160
Test name
Test status
Simulation time 27477870 ps
CPU time 0.82 seconds
Started Jan 21 03:20:03 PM PST 24
Finished Jan 21 03:20:04 PM PST 24
Peak memory 206624 kb
Host smart-156dcd20-0718-4139-aaca-2e0dc154ef67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102077922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1102077922 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2928254391
Short name T1154
Test name
Test status
Simulation time 60311021 ps
CPU time 1.87 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 215044 kb
Host smart-e46d8127-6e8a-4255-8528-120da477e799
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928254391 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.2928254391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2502339013
Short name T1205
Test name
Test status
Simulation time 18428028 ps
CPU time 1.1 seconds
Started Jan 21 03:18:59 PM PST 24
Finished Jan 21 03:19:02 PM PST 24
Peak memory 206824 kb
Host smart-d84c737e-116e-4875-9c8b-1a7c22b614ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502339013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2502339013 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3174904827
Short name T1166
Test name
Test status
Simulation time 22442941 ps
CPU time 0.77 seconds
Started Jan 21 03:18:57 PM PST 24
Finished Jan 21 03:18:58 PM PST 24
Peak memory 206588 kb
Host smart-b874ceb6-887c-454a-8d1f-7dc90c88b065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174904827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3174904827 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.725462678
Short name T115
Test name
Test status
Simulation time 63230849 ps
CPU time 1.7 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 206796 kb
Host smart-344d4839-e7fb-4ba0-a87c-049e462620b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725462678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.725462678 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2366539562
Short name T1235
Test name
Test status
Simulation time 28481873 ps
CPU time 1.62 seconds
Started Jan 21 03:19:03 PM PST 24
Finished Jan 21 03:19:06 PM PST 24
Peak memory 223576 kb
Host smart-5c40acca-e38d-4e41-9e2a-b9172a7b90f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366539562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.2366539562 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3793473975
Short name T83
Test name
Test status
Simulation time 151870673 ps
CPU time 2.79 seconds
Started Jan 21 03:18:59 PM PST 24
Finished Jan 21 03:19:04 PM PST 24
Peak memory 214860 kb
Host smart-8774a338-47e3-41ff-9ebb-67ad74249b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793473975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3793473975 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1368009845
Short name T153
Test name
Test status
Simulation time 97091342 ps
CPU time 2.65 seconds
Started Jan 21 03:30:47 PM PST 24
Finished Jan 21 03:30:52 PM PST 24
Peak memory 215000 kb
Host smart-f8c3e16d-d9fc-4b21-b14b-f96040c4e4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368009845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.13680
09845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3436796675
Short name T1255
Test name
Test status
Simulation time 32413596 ps
CPU time 1.7 seconds
Started Jan 21 03:19:00 PM PST 24
Finished Jan 21 03:19:04 PM PST 24
Peak memory 222960 kb
Host smart-c8112bca-21ed-4086-ad04-0bb203077553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436796675 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3436796675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.729415975
Short name T1183
Test name
Test status
Simulation time 24460429 ps
CPU time 0.93 seconds
Started Jan 21 03:18:57 PM PST 24
Finished Jan 21 03:18:59 PM PST 24
Peak memory 206584 kb
Host smart-71a1c6ea-d4cb-4544-a5dc-81dfdfbbe552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729415975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.729415975 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.3456827630
Short name T1224
Test name
Test status
Simulation time 45429067 ps
CPU time 0.82 seconds
Started Jan 21 03:19:03 PM PST 24
Finished Jan 21 03:19:06 PM PST 24
Peak memory 206620 kb
Host smart-d5dadc3a-5728-46e5-9acc-1e829087e29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456827630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3456827630 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1431187991
Short name T2
Test name
Test status
Simulation time 929515512 ps
CPU time 1.59 seconds
Started Jan 21 03:18:57 PM PST 24
Finished Jan 21 03:19:00 PM PST 24
Peak memory 215072 kb
Host smart-65816f0f-1330-4c31-944d-bfdc886781e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431187991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.1431187991 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.815503344
Short name T53
Test name
Test status
Simulation time 30446225 ps
CPU time 1.11 seconds
Started Jan 21 03:18:58 PM PST 24
Finished Jan 21 03:19:00 PM PST 24
Peak memory 207148 kb
Host smart-1d31bcde-a313-4249-ab18-55bab02da0a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815503344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_e
rrors.815503344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2932662550
Short name T103
Test name
Test status
Simulation time 131985762 ps
CPU time 1.8 seconds
Started Jan 21 03:19:03 PM PST 24
Finished Jan 21 03:19:06 PM PST 24
Peak memory 215456 kb
Host smart-913df0a0-575a-44b3-9c04-02a81e4e596d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932662550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2932662550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2458020660
Short name T105
Test name
Test status
Simulation time 173910892 ps
CPU time 3.13 seconds
Started Jan 21 03:36:37 PM PST 24
Finished Jan 21 03:36:44 PM PST 24
Peak memory 215092 kb
Host smart-86bfec7d-7ffc-4efd-b4d1-b54c4192a6a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458020660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.24580
20660 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2432303981
Short name T1181
Test name
Test status
Simulation time 136571690 ps
CPU time 2.04 seconds
Started Jan 21 03:19:13 PM PST 24
Finished Jan 21 03:19:16 PM PST 24
Peak memory 222904 kb
Host smart-a6f3b6c8-52cb-42d1-85a0-ee59694a7f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432303981 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2432303981 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.4127854461
Short name T1165
Test name
Test status
Simulation time 43393814 ps
CPU time 1.09 seconds
Started Jan 21 03:19:12 PM PST 24
Finished Jan 21 03:19:14 PM PST 24
Peak memory 206652 kb
Host smart-d8747da9-caf5-4b14-aa77-3b4c1f6ed336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127854461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.4127854461 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.2001361885
Short name T1274
Test name
Test status
Simulation time 13162408 ps
CPU time 0.78 seconds
Started Jan 21 03:19:10 PM PST 24
Finished Jan 21 03:19:13 PM PST 24
Peak memory 206516 kb
Host smart-7b6d1518-7915-4608-90c7-9d5499348def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001361885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2001361885 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3300548573
Short name T167
Test name
Test status
Simulation time 195708412 ps
CPU time 1.63 seconds
Started Jan 21 03:19:09 PM PST 24
Finished Jan 21 03:19:11 PM PST 24
Peak memory 215060 kb
Host smart-e0a2828e-71a1-4741-bb4d-921515a2aa26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300548573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3300548573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.909025629
Short name T1198
Test name
Test status
Simulation time 74908784 ps
CPU time 0.96 seconds
Started Jan 21 03:18:59 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 206748 kb
Host smart-2a7443a4-3691-4802-9fcd-e6116451fc6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909025629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e
rrors.909025629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1945421387
Short name T92
Test name
Test status
Simulation time 117514151 ps
CPU time 2.69 seconds
Started Jan 21 03:43:17 PM PST 24
Finished Jan 21 03:43:27 PM PST 24
Peak memory 215144 kb
Host smart-f4233d98-8825-48d4-89b1-e217c7be880f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945421387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1945421387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.63541781
Short name T108
Test name
Test status
Simulation time 32499967 ps
CPU time 1.77 seconds
Started Jan 21 03:18:56 PM PST 24
Finished Jan 21 03:18:58 PM PST 24
Peak memory 215048 kb
Host smart-f6ac3155-de05-4c04-9c47-a2b6d69c01c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63541781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.63541781 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3434076302
Short name T1172
Test name
Test status
Simulation time 37613026 ps
CPU time 2.4 seconds
Started Jan 21 03:19:13 PM PST 24
Finished Jan 21 03:19:16 PM PST 24
Peak memory 215044 kb
Host smart-2f0e8f1f-6eb3-40fd-bf92-65afd8c2e676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434076302 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3434076302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.261795527
Short name T163
Test name
Test status
Simulation time 17414714 ps
CPU time 1.08 seconds
Started Jan 21 03:19:10 PM PST 24
Finished Jan 21 03:19:11 PM PST 24
Peak memory 206856 kb
Host smart-995f2522-f6f0-441e-9e6d-4f839649700c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261795527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.261795527 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.4134716102
Short name T1226
Test name
Test status
Simulation time 110347898 ps
CPU time 0.73 seconds
Started Jan 21 03:19:10 PM PST 24
Finished Jan 21 03:19:12 PM PST 24
Peak memory 206572 kb
Host smart-35d775e9-a6fa-4cfd-9ace-d2a2ff6e4403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134716102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4134716102 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1191645850
Short name T3
Test name
Test status
Simulation time 387126733 ps
CPU time 2.41 seconds
Started Jan 21 03:19:10 PM PST 24
Finished Jan 21 03:19:14 PM PST 24
Peak memory 215096 kb
Host smart-c80acd90-a3d5-4930-9e6f-9e05d1c4fd6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191645850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.1191645850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2942797334
Short name T90
Test name
Test status
Simulation time 199317152 ps
CPU time 1.45 seconds
Started Jan 21 03:19:08 PM PST 24
Finished Jan 21 03:19:10 PM PST 24
Peak memory 215292 kb
Host smart-e4097455-28ac-4f4c-acd0-f43bc4fee90c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942797334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2942797334 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.900201262
Short name T1240
Test name
Test status
Simulation time 143550138 ps
CPU time 1.62 seconds
Started Jan 21 03:19:11 PM PST 24
Finished Jan 21 03:19:14 PM PST 24
Peak memory 215348 kb
Host smart-5ef18ed3-2438-45e6-977d-fad66c3facf6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900201262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_
shadow_reg_errors_with_csr_rw.900201262 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3245229310
Short name T77
Test name
Test status
Simulation time 259458753 ps
CPU time 2.39 seconds
Started Jan 21 03:19:11 PM PST 24
Finished Jan 21 03:19:15 PM PST 24
Peak memory 215124 kb
Host smart-8acb1d51-ea87-44ba-b380-f565c479647e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245229310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3245229310 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1015322327
Short name T1220
Test name
Test status
Simulation time 136257408 ps
CPU time 3 seconds
Started Jan 21 03:19:09 PM PST 24
Finished Jan 21 03:19:12 PM PST 24
Peak memory 214988 kb
Host smart-9f9a26dc-2159-4cca-9464-c297d851f8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015322327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.10153
22327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2546568458
Short name T1208
Test name
Test status
Simulation time 37056107 ps
CPU time 1.81 seconds
Started Jan 21 03:19:24 PM PST 24
Finished Jan 21 03:19:27 PM PST 24
Peak memory 222948 kb
Host smart-256dbb18-dbe1-4691-970d-1a45511864bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546568458 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2546568458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1073220308
Short name T1256
Test name
Test status
Simulation time 86998639 ps
CPU time 1.02 seconds
Started Jan 21 03:19:13 PM PST 24
Finished Jan 21 03:19:15 PM PST 24
Peak memory 206716 kb
Host smart-de7bd864-f2a9-47d7-9cd1-3271ecb62c5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073220308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1073220308 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3911868933
Short name T1204
Test name
Test status
Simulation time 28820640 ps
CPU time 0.82 seconds
Started Jan 21 03:19:09 PM PST 24
Finished Jan 21 03:19:10 PM PST 24
Peak memory 206556 kb
Host smart-79564f97-bd11-4bd0-9223-cbbaf74c63a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911868933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3911868933 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3009101983
Short name T111
Test name
Test status
Simulation time 95109216 ps
CPU time 2.49 seconds
Started Jan 21 03:19:08 PM PST 24
Finished Jan 21 03:19:12 PM PST 24
Peak memory 206788 kb
Host smart-5f6e6d6a-3509-41aa-9b7d-a416130682e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009101983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.3009101983 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1854827020
Short name T98
Test name
Test status
Simulation time 81642509 ps
CPU time 1.04 seconds
Started Jan 21 03:19:11 PM PST 24
Finished Jan 21 03:19:13 PM PST 24
Peak memory 206980 kb
Host smart-c8925b73-420a-49cf-8ced-2219f42a97fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854827020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.1854827020 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1606965896
Short name T99
Test name
Test status
Simulation time 561127400 ps
CPU time 3.1 seconds
Started Jan 21 03:19:10 PM PST 24
Finished Jan 21 03:19:15 PM PST 24
Peak memory 222748 kb
Host smart-d6d8d653-8562-4ca8-bf6b-322efa6c11ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606965896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1606965896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.2331658798
Short name T1196
Test name
Test status
Simulation time 98501312 ps
CPU time 2.94 seconds
Started Jan 21 03:19:13 PM PST 24
Finished Jan 21 03:19:17 PM PST 24
Peak memory 215044 kb
Host smart-61309253-b3dc-41ac-b2ae-79a4c3a1df5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331658798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2331658798 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1847796245
Short name T109
Test name
Test status
Simulation time 516544031 ps
CPU time 3.06 seconds
Started Jan 21 03:19:08 PM PST 24
Finished Jan 21 03:19:11 PM PST 24
Peak memory 214924 kb
Host smart-36dab318-3487-41ba-b611-9ef1fb96c178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847796245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.18477
96245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest


Test location /workspace/coverage/default/0.kmac_alert_test.446909706
Short name T316
Test name
Test status
Simulation time 48606178 ps
CPU time 0.78 seconds
Started Jan 21 01:46:34 PM PST 24
Finished Jan 21 01:46:35 PM PST 24
Peak memory 207248 kb
Host smart-8858d840-e1de-4dee-b045-76c21827f98d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446909706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.446909706 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest


Test location /workspace/coverage/default/0.kmac_app.2815902637
Short name T1052
Test name
Test status
Simulation time 19958403490 ps
CPU time 83.87 seconds
Started Jan 21 01:46:23 PM PST 24
Finished Jan 21 01:47:48 PM PST 24
Peak memory 226404 kb
Host smart-e899e445-d22e-4866-b5e5-29c8a048c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815902637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2815902637 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest


Test location /workspace/coverage/default/0.kmac_app_with_partial_data.2512587232
Short name T925
Test name
Test status
Simulation time 53876811821 ps
CPU time 42.31 seconds
Started Jan 21 01:46:23 PM PST 24
Finished Jan 21 01:47:06 PM PST 24
Peak memory 223900 kb
Host smart-bb530d6c-010e-4e1c-842a-7def9c76b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512587232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2512587232 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/0.kmac_burst_write.2349758287
Short name T772
Test name
Test status
Simulation time 14828216961 ps
CPU time 429.29 seconds
Started Jan 21 01:46:09 PM PST 24
Finished Jan 21 01:53:19 PM PST 24
Peak memory 240212 kb
Host smart-9a9da4ac-850e-44d6-9b5d-1a90c54ea2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349758287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2349758287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest


Test location /workspace/coverage/default/0.kmac_entropy_mode_error.322881651
Short name T290
Test name
Test status
Simulation time 2054737955 ps
CPU time 20.78 seconds
Started Jan 21 01:46:24 PM PST 24
Finished Jan 21 01:46:46 PM PST 24
Peak memory 223536 kb
Host smart-a18a9c5b-9911-47fa-91c7-104510abf6a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=322881651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.322881651 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/0.kmac_entropy_ready_error.449153038
Short name T781
Test name
Test status
Simulation time 5323591999 ps
CPU time 46.39 seconds
Started Jan 21 02:51:34 PM PST 24
Finished Jan 21 02:52:21 PM PST 24
Peak memory 220052 kb
Host smart-a3a32318-d321-43dd-af92-99ee8e5d5d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449153038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.449153038 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/0.kmac_entropy_refresh.3657251493
Short name T611
Test name
Test status
Simulation time 7109604997 ps
CPU time 123.3 seconds
Started Jan 21 01:46:20 PM PST 24
Finished Jan 21 01:48:24 PM PST 24
Peak memory 232672 kb
Host smart-c7eeb5b7-37da-4318-a679-f4db2186fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657251493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3657251493 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/0.kmac_error.1480288305
Short name T640
Test name
Test status
Simulation time 6117059706 ps
CPU time 81.76 seconds
Started Jan 21 01:46:23 PM PST 24
Finished Jan 21 01:47:45 PM PST 24
Peak memory 235760 kb
Host smart-34d2ca3f-8e07-4c79-8355-79f1589c38db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480288305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1480288305 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest


Test location /workspace/coverage/default/0.kmac_key_error.4229755883
Short name T496
Test name
Test status
Simulation time 2172717764 ps
CPU time 2.21 seconds
Started Jan 21 01:46:22 PM PST 24
Finished Jan 21 01:46:26 PM PST 24
Peak memory 207568 kb
Host smart-258e829f-427e-44d5-863c-4f7c72133b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229755883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.4229755883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest


Test location /workspace/coverage/default/0.kmac_lc_escalation.1265987734
Short name T1112
Test name
Test status
Simulation time 45058414 ps
CPU time 1.29 seconds
Started Jan 21 02:04:54 PM PST 24
Finished Jan 21 02:05:00 PM PST 24
Peak memory 219880 kb
Host smart-c6f34222-5c7c-410e-9e5b-f2f67f1ccbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265987734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1265987734 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest


Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3213976758
Short name T295
Test name
Test status
Simulation time 7543422204 ps
CPU time 373.96 seconds
Started Jan 21 01:46:12 PM PST 24
Finished Jan 21 01:52:27 PM PST 24
Peak memory 259144 kb
Host smart-efe4e2a1-4f95-4a76-9b26-886d99225635
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213976758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3213976758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/0.kmac_mubi.3718700443
Short name T667
Test name
Test status
Simulation time 57236896427 ps
CPU time 250.68 seconds
Started Jan 21 01:46:23 PM PST 24
Finished Jan 21 01:50:35 PM PST 24
Peak memory 243844 kb
Host smart-e2dfb166-2fe2-4bd5-8bbf-2a0fe4216be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718700443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3718700443 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest


Test location /workspace/coverage/default/0.kmac_sideload.44359435
Short name T223
Test name
Test status
Simulation time 3357658905 ps
CPU time 92.39 seconds
Started Jan 21 01:46:11 PM PST 24
Finished Jan 21 01:47:45 PM PST 24
Peak memory 232044 kb
Host smart-b31b50d7-c58a-4749-bd22-00c547a58ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44359435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.44359435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest


Test location /workspace/coverage/default/0.kmac_smoke.516382674
Short name T193
Test name
Test status
Simulation time 200457681 ps
CPU time 1.51 seconds
Started Jan 21 01:46:15 PM PST 24
Finished Jan 21 01:46:17 PM PST 24
Peak memory 215980 kb
Host smart-1ae5a092-3ac2-443c-8ab9-20f605c1a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516382674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.516382674 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest


Test location /workspace/coverage/default/0.kmac_stress_all.3750074082
Short name T1074
Test name
Test status
Simulation time 1092775746 ps
CPU time 45.36 seconds
Started Jan 21 01:46:34 PM PST 24
Finished Jan 21 01:47:20 PM PST 24
Peak memory 225240 kb
Host smart-380457ff-42f8-45f3-bf0d-66d5c642e66a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3750074082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3750074082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest


Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.3395404478
Short name T426
Test name
Test status
Simulation time 214485173701 ps
CPU time 1676.88 seconds
Started Jan 21 01:59:23 PM PST 24
Finished Jan 21 02:27:21 PM PST 24
Peak memory 387856 kb
Host smart-5901c2c9-eefd-4657-86a0-5f442706f98f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395404478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.3395404478 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.3558448648
Short name T478
Test name
Test status
Simulation time 336966054 ps
CPU time 4.82 seconds
Started Jan 21 01:46:21 PM PST 24
Finished Jan 21 01:46:27 PM PST 24
Peak memory 217244 kb
Host smart-9a0520bb-c029-4ece-a552-55d8d7806513
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558448648 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.3558448648 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2034100973
Short name T612
Test name
Test status
Simulation time 4775843776 ps
CPU time 6.31 seconds
Started Jan 21 01:46:22 PM PST 24
Finished Jan 21 01:46:30 PM PST 24
Peak memory 217848 kb
Host smart-64280d94-9fc8-4c76-a015-bb7fe02a0146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034100973 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2034100973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.1565433718
Short name T286
Test name
Test status
Simulation time 98416081717 ps
CPU time 1852.41 seconds
Started Jan 21 01:46:10 PM PST 24
Finished Jan 21 02:17:03 PM PST 24
Peak memory 374356 kb
Host smart-4c34d088-427c-49c6-a86a-053104a2537e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1565433718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1565433718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.1970208965
Short name T1017
Test name
Test status
Simulation time 35633978977 ps
CPU time 1508.45 seconds
Started Jan 21 01:46:10 PM PST 24
Finished Jan 21 02:11:19 PM PST 24
Peak memory 368052 kb
Host smart-0edde105-3f0f-4d2d-9c6f-87b67dbdcdff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1970208965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1970208965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.203366883
Short name T985
Test name
Test status
Simulation time 13992725602 ps
CPU time 1122.12 seconds
Started Jan 21 01:46:14 PM PST 24
Finished Jan 21 02:04:57 PM PST 24
Peak memory 333080 kb
Host smart-fc5085ed-970c-4fc4-b523-5034448d720a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=203366883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.203366883 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.2968938108
Short name T190
Test name
Test status
Simulation time 38624852190 ps
CPU time 756.97 seconds
Started Jan 21 01:46:11 PM PST 24
Finished Jan 21 01:58:48 PM PST 24
Peak memory 290000 kb
Host smart-012e0475-f2b9-4eba-a254-8ddace752ece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2968938108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2968938108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.3082681037
Short name T1000
Test name
Test status
Simulation time 557820614093 ps
CPU time 4238.32 seconds
Started Jan 21 01:46:21 PM PST 24
Finished Jan 21 02:57:00 PM PST 24
Peak memory 637384 kb
Host smart-fdc2c9f2-b78a-4754-9171-91f92cdda9e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3082681037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3082681037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.3988262662
Short name T235
Test name
Test status
Simulation time 43274406953 ps
CPU time 3250.17 seconds
Started Jan 21 01:46:21 PM PST 24
Finished Jan 21 02:40:32 PM PST 24
Peak memory 561004 kb
Host smart-791ebda9-217a-4317-ae94-cf5d02e4ff24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3988262662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3988262662 +enable_masking=0 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/1.kmac_alert_test.3035600970
Short name T293
Test name
Test status
Simulation time 16388153 ps
CPU time 0.76 seconds
Started Jan 21 01:46:51 PM PST 24
Finished Jan 21 01:46:54 PM PST 24
Peak memory 207300 kb
Host smart-5c4941f6-fd34-4dcf-874b-71dabcb8938f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035600970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3035600970 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest


Test location /workspace/coverage/default/1.kmac_app.3409237075
Short name T1093
Test name
Test status
Simulation time 1127779882 ps
CPU time 45.79 seconds
Started Jan 21 01:46:43 PM PST 24
Finished Jan 21 01:47:30 PM PST 24
Peak memory 223760 kb
Host smart-6947bddb-23b3-46f4-8166-8b3030ba83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409237075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3409237075 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest


Test location /workspace/coverage/default/1.kmac_burst_write.3377315099
Short name T487
Test name
Test status
Simulation time 29449657437 ps
CPU time 592.95 seconds
Started Jan 21 02:28:21 PM PST 24
Finished Jan 21 02:38:15 PM PST 24
Peak memory 230324 kb
Host smart-f6c9b9b2-d6d8-43d7-a15d-755216209193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377315099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3377315099 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest


Test location /workspace/coverage/default/1.kmac_edn_timeout_error.439961388
Short name T516
Test name
Test status
Simulation time 241563501 ps
CPU time 17.28 seconds
Started Jan 21 01:46:42 PM PST 24
Finished Jan 21 01:47:00 PM PST 24
Peak memory 223568 kb
Host smart-4fad4ef3-cd65-4b88-97c8-550af8ad2742
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=439961388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.439961388 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1308353269
Short name T841
Test name
Test status
Simulation time 95139764 ps
CPU time 3.56 seconds
Started Jan 21 01:46:41 PM PST 24
Finished Jan 21 01:46:45 PM PST 24
Peak memory 218248 kb
Host smart-2883a19d-1afa-42e7-944b-70a26eecdbd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1308353269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1308353269 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/1.kmac_entropy_ready_error.4048306551
Short name T228
Test name
Test status
Simulation time 362907969 ps
CPU time 4.14 seconds
Started Jan 21 01:46:51 PM PST 24
Finished Jan 21 01:46:58 PM PST 24
Peak memory 215868 kb
Host smart-833d5376-dd0a-4a2d-979b-c77c7e874c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048306551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.4048306551 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/1.kmac_entropy_refresh.1646062606
Short name T968
Test name
Test status
Simulation time 11583755989 ps
CPU time 130.24 seconds
Started Jan 21 01:46:41 PM PST 24
Finished Jan 21 01:48:52 PM PST 24
Peak memory 234232 kb
Host smart-b692a1b9-66d0-4132-a5d8-fa910fdbb7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646062606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1646062606 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/1.kmac_error.2254582639
Short name T402
Test name
Test status
Simulation time 1695077551 ps
CPU time 77.31 seconds
Started Jan 21 01:46:42 PM PST 24
Finished Jan 21 01:48:00 PM PST 24
Peak memory 235092 kb
Host smart-65d0fe85-97b3-4952-92a8-af30b81659af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254582639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2254582639 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest


Test location /workspace/coverage/default/1.kmac_key_error.2897499436
Short name T1128
Test name
Test status
Simulation time 1749145888 ps
CPU time 2.32 seconds
Started Jan 21 01:46:40 PM PST 24
Finished Jan 21 01:46:43 PM PST 24
Peak memory 207368 kb
Host smart-f34472e7-826e-4f66-b466-ad1c95be102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897499436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2897499436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest


Test location /workspace/coverage/default/1.kmac_lc_escalation.2339720747
Short name T1038
Test name
Test status
Simulation time 394478143 ps
CPU time 15.89 seconds
Started Jan 21 01:46:55 PM PST 24
Finished Jan 21 01:47:14 PM PST 24
Peak memory 232128 kb
Host smart-93f838b1-accb-44c0-b913-c5db13b42ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339720747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2339720747 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest


Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1628141623
Short name T975
Test name
Test status
Simulation time 60887049180 ps
CPU time 683.32 seconds
Started Jan 21 01:46:33 PM PST 24
Finished Jan 21 01:57:57 PM PST 24
Peak memory 290292 kb
Host smart-e77f3e0d-8c69-4a4b-94ae-15de5926e635
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628141623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1628141623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/1.kmac_mubi.4285790560
Short name T817
Test name
Test status
Simulation time 1296985843 ps
CPU time 38.14 seconds
Started Jan 21 01:46:43 PM PST 24
Finished Jan 21 01:47:22 PM PST 24
Peak memory 224160 kb
Host smart-b03e5df7-8584-405e-a25f-268b0915a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285790560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.4285790560 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest


Test location /workspace/coverage/default/1.kmac_sec_cm.2580179124
Short name T12
Test name
Test status
Simulation time 8708198769 ps
CPU time 51.1 seconds
Started Jan 21 01:46:58 PM PST 24
Finished Jan 21 01:47:50 PM PST 24
Peak memory 258980 kb
Host smart-3e616d3d-2308-420a-919f-f8d2a3f64157
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580179124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2580179124 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest


Test location /workspace/coverage/default/1.kmac_sideload.1399423859
Short name T72
Test name
Test status
Simulation time 7496620347 ps
CPU time 132.3 seconds
Started Jan 21 01:46:30 PM PST 24
Finished Jan 21 01:48:43 PM PST 24
Peak memory 232172 kb
Host smart-78b32c5f-04b8-4601-9c80-cae145ca5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399423859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1399423859 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest


Test location /workspace/coverage/default/1.kmac_smoke.1781903143
Short name T442
Test name
Test status
Simulation time 386096609 ps
CPU time 19.67 seconds
Started Jan 21 01:46:29 PM PST 24
Finished Jan 21 01:46:50 PM PST 24
Peak memory 217688 kb
Host smart-0c9d4a7c-0a88-447c-877a-bc329968dc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781903143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1781903143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest


Test location /workspace/coverage/default/1.kmac_stress_all.3740542557
Short name T891
Test name
Test status
Simulation time 87330338021 ps
CPU time 1312.71 seconds
Started Jan 21 01:46:56 PM PST 24
Finished Jan 21 02:08:51 PM PST 24
Peak memory 387376 kb
Host smart-c184e42b-6b2d-4d63-8056-f4638a03d552
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3740542557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3740542557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest


Test location /workspace/coverage/default/1.kmac_stress_all_with_rand_reset.1621772799
Short name T599
Test name
Test status
Simulation time 58004917070 ps
CPU time 871.72 seconds
Started Jan 21 01:46:55 PM PST 24
Finished Jan 21 02:01:29 PM PST 24
Peak memory 330396 kb
Host smart-f737f408-09a8-472f-b23a-07510e3f265f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621772799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.1621772799 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.1247269658
Short name T981
Test name
Test status
Simulation time 1884108896 ps
CPU time 5.03 seconds
Started Jan 21 01:46:43 PM PST 24
Finished Jan 21 01:46:49 PM PST 24
Peak memory 217104 kb
Host smart-285ad3ec-fc35-4b6a-9b14-8491c5ce58f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247269658 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.1247269658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3152391655
Short name T767
Test name
Test status
Simulation time 168128140 ps
CPU time 4.38 seconds
Started Jan 21 01:46:42 PM PST 24
Finished Jan 21 01:46:47 PM PST 24
Peak memory 217080 kb
Host smart-c6f92364-59d4-4946-93fd-ea905ec943b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152391655 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3152391655 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.1101394839
Short name T258
Test name
Test status
Simulation time 32473099263 ps
CPU time 1538.53 seconds
Started Jan 21 01:46:33 PM PST 24
Finished Jan 21 02:12:13 PM PST 24
Peak memory 398160 kb
Host smart-74c5fb29-8528-47cc-abc5-aaf8e79aaef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1101394839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1101394839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.1540177409
Short name T1001
Test name
Test status
Simulation time 95486954854 ps
CPU time 1815.09 seconds
Started Jan 21 02:19:08 PM PST 24
Finished Jan 21 02:49:24 PM PST 24
Peak memory 373972 kb
Host smart-0d1274a0-36da-4e0c-9866-93badb483f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1540177409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1540177409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.1806307490
Short name T347
Test name
Test status
Simulation time 52750067195 ps
CPU time 1058.46 seconds
Started Jan 21 01:46:31 PM PST 24
Finished Jan 21 02:04:10 PM PST 24
Peak memory 325344 kb
Host smart-a0255aa6-d3de-44ba-bb7e-1e8e0d57d147
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1806307490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1806307490 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.2107961273
Short name T202
Test name
Test status
Simulation time 19346961211 ps
CPU time 759.24 seconds
Started Jan 21 02:29:05 PM PST 24
Finished Jan 21 02:41:46 PM PST 24
Peak memory 290124 kb
Host smart-3413e1df-8b1f-45ae-896c-f8e1dc110e1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2107961273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2107961273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.3343861529
Short name T221
Test name
Test status
Simulation time 529222731642 ps
CPU time 5346.38 seconds
Started Jan 21 01:46:30 PM PST 24
Finished Jan 21 03:15:37 PM PST 24
Peak memory 639272 kb
Host smart-ad32e80d-279f-4da3-8ba7-65f2ce4ea5e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3343861529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3343861529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.1374888704
Short name T401
Test name
Test status
Simulation time 221724365776 ps
CPU time 4167.95 seconds
Started Jan 21 01:46:42 PM PST 24
Finished Jan 21 02:56:11 PM PST 24
Peak memory 566196 kb
Host smart-9065c68e-a85d-4911-8a89-00bdd8cae7dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1374888704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1374888704 +enable_masking=0 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/10.kmac_alert_test.3848706819
Short name T818
Test name
Test status
Simulation time 12801689 ps
CPU time 0.75 seconds
Started Jan 21 01:50:03 PM PST 24
Finished Jan 21 01:50:05 PM PST 24
Peak memory 207188 kb
Host smart-3c439a07-98c8-462f-90f0-f36513cdd6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848706819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3848706819 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest


Test location /workspace/coverage/default/10.kmac_app.4248659159
Short name T14
Test name
Test status
Simulation time 61435924544 ps
CPU time 191.09 seconds
Started Jan 21 01:49:47 PM PST 24
Finished Jan 21 01:53:05 PM PST 24
Peak memory 234636 kb
Host smart-2417ed1f-940e-4ca1-8ac7-806f58d4a845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248659159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.4248659159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest


Test location /workspace/coverage/default/10.kmac_burst_write.832710051
Short name T752
Test name
Test status
Simulation time 10052699462 ps
CPU time 300.75 seconds
Started Jan 21 01:49:36 PM PST 24
Finished Jan 21 01:54:40 PM PST 24
Peak memory 228064 kb
Host smart-1a95e677-33f3-4afb-b5c1-298d2112930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832710051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.832710051 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest


Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2328330756
Short name T774
Test name
Test status
Simulation time 20506191437 ps
CPU time 27.18 seconds
Started Jan 21 01:49:45 PM PST 24
Finished Jan 21 01:50:13 PM PST 24
Peak memory 223732 kb
Host smart-ecb1cd3a-96dc-4656-b7c9-47ac90e08e2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328330756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2328330756 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/10.kmac_entropy_mode_error.3828759062
Short name T849
Test name
Test status
Simulation time 576966255 ps
CPU time 19.4 seconds
Started Jan 21 01:49:45 PM PST 24
Finished Jan 21 01:50:06 PM PST 24
Peak memory 223668 kb
Host smart-1b695e93-f41e-420c-9d5d-e342c3a8f5d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3828759062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3828759062 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/10.kmac_entropy_refresh.114961401
Short name T429
Test name
Test status
Simulation time 19137940374 ps
CPU time 200.79 seconds
Started Jan 21 01:49:44 PM PST 24
Finished Jan 21 01:53:06 PM PST 24
Peak memory 238504 kb
Host smart-e838ef5e-556b-4ae2-ab70-641048a08dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114961401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.114961401 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/10.kmac_error.1917295735
Short name T764
Test name
Test status
Simulation time 14347238442 ps
CPU time 283 seconds
Started Jan 21 01:49:46 PM PST 24
Finished Jan 21 01:54:30 PM PST 24
Peak memory 255824 kb
Host smart-ca9992fa-5a08-42ad-8448-1bdb42d0b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917295735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1917295735 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest


Test location /workspace/coverage/default/10.kmac_key_error.2215443091
Short name T719
Test name
Test status
Simulation time 792237853 ps
CPU time 1.37 seconds
Started Jan 21 01:49:47 PM PST 24
Finished Jan 21 01:49:55 PM PST 24
Peak memory 207412 kb
Host smart-112e85b4-d036-4781-b67c-a8006c723509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215443091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2215443091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest


Test location /workspace/coverage/default/10.kmac_lc_escalation.1922325371
Short name T949
Test name
Test status
Simulation time 38733469 ps
CPU time 1.45 seconds
Started Jan 21 02:32:44 PM PST 24
Finished Jan 21 02:32:46 PM PST 24
Peak memory 215932 kb
Host smart-188fd474-46a7-4113-b30d-8c12464570cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922325371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1922325371 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest


Test location /workspace/coverage/default/10.kmac_long_msg_and_output.1510367797
Short name T70
Test name
Test status
Simulation time 7248155838 ps
CPU time 42.75 seconds
Started Jan 21 01:49:34 PM PST 24
Finished Jan 21 01:50:20 PM PST 24
Peak memory 223892 kb
Host smart-d87f354c-6115-4513-83e2-8bb37aaad55c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510367797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.1510367797 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/10.kmac_sideload.4036400286
Short name T662
Test name
Test status
Simulation time 17506597157 ps
CPU time 333.63 seconds
Started Jan 21 01:49:35 PM PST 24
Finished Jan 21 01:55:12 PM PST 24
Peak memory 244500 kb
Host smart-f5b9450f-fa3d-463d-b913-5b2341a24c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036400286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.4036400286 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest


Test location /workspace/coverage/default/10.kmac_smoke.4039578127
Short name T246
Test name
Test status
Simulation time 4054113245 ps
CPU time 51.09 seconds
Started Jan 21 02:26:29 PM PST 24
Finished Jan 21 02:27:21 PM PST 24
Peak memory 219112 kb
Host smart-a64e6c8d-b6b1-4aa4-994e-8d5f41a7bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039578127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.4039578127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest


Test location /workspace/coverage/default/10.kmac_stress_all.2276614195
Short name T597
Test name
Test status
Simulation time 9327974036 ps
CPU time 254.66 seconds
Started Jan 21 01:49:51 PM PST 24
Finished Jan 21 01:54:10 PM PST 24
Peak memory 247004 kb
Host smart-3efffae3-4267-4771-b53b-dde88e46aa7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2276614195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2276614195 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest


Test location /workspace/coverage/default/10.kmac_stress_all_with_rand_reset.1023485265
Short name T1134
Test name
Test status
Simulation time 15044470502 ps
CPU time 310.43 seconds
Started Jan 21 02:27:15 PM PST 24
Finished Jan 21 02:32:26 PM PST 24
Peak memory 256172 kb
Host smart-ce789823-dc2f-4d62-b422-1ae671a48ecb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023485265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all_with_rand_reset.1023485265 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.594672625
Short name T391
Test name
Test status
Simulation time 124590014 ps
CPU time 4.11 seconds
Started Jan 21 01:49:45 PM PST 24
Finished Jan 21 01:49:50 PM PST 24
Peak memory 216860 kb
Host smart-57e6db02-e3b2-421a-81a8-677c2964b086
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594672625 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.kmac_test_vectors_kmac.594672625 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.2606441972
Short name T592
Test name
Test status
Simulation time 705645882 ps
CPU time 4.65 seconds
Started Jan 21 02:20:30 PM PST 24
Finished Jan 21 02:20:36 PM PST 24
Peak memory 217272 kb
Host smart-b1e0ae36-c20e-448d-8a4b-d6e9d63138fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606441972 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.2606441972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3466446857
Short name T802
Test name
Test status
Simulation time 134544046443 ps
CPU time 1873.93 seconds
Started Jan 21 01:49:39 PM PST 24
Finished Jan 21 02:20:56 PM PST 24
Peak memory 397888 kb
Host smart-0483d8c1-83b6-4d56-b6db-60a056a83017
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3466446857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3466446857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.316560205
Short name T645
Test name
Test status
Simulation time 94483089754 ps
CPU time 1816.08 seconds
Started Jan 21 01:49:33 PM PST 24
Finished Jan 21 02:19:54 PM PST 24
Peak memory 392396 kb
Host smart-af6d9f17-a2cc-4720-b419-3d905c77353a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=316560205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.316560205 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.959452289
Short name T569
Test name
Test status
Simulation time 49847024425 ps
CPU time 1127.73 seconds
Started Jan 21 01:49:33 PM PST 24
Finished Jan 21 02:08:25 PM PST 24
Peak memory 330804 kb
Host smart-95ddf49c-2274-4cdb-bf8b-9e6d617ca45e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=959452289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.959452289 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.93016818
Short name T969
Test name
Test status
Simulation time 33510297071 ps
CPU time 910.77 seconds
Started Jan 21 02:51:36 PM PST 24
Finished Jan 21 03:06:48 PM PST 24
Peak memory 291924 kb
Host smart-bf5e553c-156e-41ea-b3cc-a759160a1206
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=93016818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.93016818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.3629518635
Short name T672
Test name
Test status
Simulation time 53425469651 ps
CPU time 4141.94 seconds
Started Jan 21 01:49:45 PM PST 24
Finished Jan 21 02:58:49 PM PST 24
Peak memory 647948 kb
Host smart-d36edbe5-a812-43ce-bc97-acd34ec87530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3629518635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3629518635 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.863253171
Short name T208
Test name
Test status
Simulation time 193125122193 ps
CPU time 4017.21 seconds
Started Jan 21 01:49:44 PM PST 24
Finished Jan 21 02:56:42 PM PST 24
Peak memory 565528 kb
Host smart-088aff08-dde3-4993-bf36-a63cbc8e308f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=863253171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.863253171 +enable_masking=0 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/11.kmac_app.3629333927
Short name T623
Test name
Test status
Simulation time 2357498752 ps
CPU time 68.16 seconds
Started Jan 21 01:50:10 PM PST 24
Finished Jan 21 01:51:23 PM PST 24
Peak memory 227284 kb
Host smart-7fd8fbeb-4e8c-49ec-80c6-b69ec417efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629333927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3629333927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest


Test location /workspace/coverage/default/11.kmac_burst_write.1238237
Short name T334
Test name
Test status
Simulation time 10679446295 ps
CPU time 268.82 seconds
Started Jan 21 02:37:02 PM PST 24
Finished Jan 21 02:41:32 PM PST 24
Peak memory 227056 kb
Host smart-992b861b-ac29-495f-b499-038c53ba5761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.1238237 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest


Test location /workspace/coverage/default/11.kmac_edn_timeout_error.2525503956
Short name T240
Test name
Test status
Simulation time 730799904 ps
CPU time 9.16 seconds
Started Jan 21 01:50:21 PM PST 24
Finished Jan 21 01:50:34 PM PST 24
Peak memory 223624 kb
Host smart-65013bb3-c716-4782-90b0-36e7d6f2f631
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525503956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2525503956 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2661824921
Short name T444
Test name
Test status
Simulation time 384451998 ps
CPU time 7.31 seconds
Started Jan 21 01:50:27 PM PST 24
Finished Jan 21 01:50:36 PM PST 24
Peak memory 221584 kb
Host smart-6b03b250-8410-4374-9b09-29a9892b4c35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2661824921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2661824921 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/11.kmac_entropy_refresh.31686565
Short name T1139
Test name
Test status
Simulation time 12693932443 ps
CPU time 283.8 seconds
Started Jan 21 01:50:11 PM PST 24
Finished Jan 21 01:54:59 PM PST 24
Peak memory 243384 kb
Host smart-3e88dc9c-69aa-4ee8-b02a-4fd9653b45f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31686565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.31686565 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/11.kmac_error.1700433740
Short name T637
Test name
Test status
Simulation time 45192562760 ps
CPU time 277.76 seconds
Started Jan 21 01:50:09 PM PST 24
Finished Jan 21 01:54:53 PM PST 24
Peak memory 252356 kb
Host smart-3d81a4dd-2340-4916-a66d-8db3a6ea37fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700433740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1700433740 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest


Test location /workspace/coverage/default/11.kmac_key_error.2039877427
Short name T1078
Test name
Test status
Simulation time 3195017020 ps
CPU time 5.27 seconds
Started Jan 21 01:50:20 PM PST 24
Finished Jan 21 01:50:31 PM PST 24
Peak memory 207592 kb
Host smart-848362de-bf86-4f48-94a8-71200a6e5f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039877427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2039877427 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest


Test location /workspace/coverage/default/11.kmac_lc_escalation.542276345
Short name T726
Test name
Test status
Simulation time 55814498 ps
CPU time 1.19 seconds
Started Jan 21 01:50:28 PM PST 24
Finished Jan 21 01:50:30 PM PST 24
Peak memory 215804 kb
Host smart-61ed11c7-e515-44f6-b8e5-6cf7d220cf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542276345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.542276345 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/11.kmac_lc_escalation/latest


Test location /workspace/coverage/default/11.kmac_long_msg_and_output.2712591896
Short name T242
Test name
Test status
Simulation time 10341322868 ps
CPU time 263.67 seconds
Started Jan 21 02:05:47 PM PST 24
Finished Jan 21 02:10:12 PM PST 24
Peak memory 242808 kb
Host smart-38731028-f2c7-4f84-b547-a9993a944b36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712591896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.2712591896 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/11.kmac_sideload.2886271057
Short name T649
Test name
Test status
Simulation time 10089741974 ps
CPU time 297.02 seconds
Started Jan 21 01:50:03 PM PST 24
Finished Jan 21 01:55:01 PM PST 24
Peak memory 246652 kb
Host smart-9d38b545-7174-425f-b902-03b52b0eb3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886271057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2886271057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest


Test location /workspace/coverage/default/11.kmac_smoke.3953219673
Short name T278
Test name
Test status
Simulation time 3026010862 ps
CPU time 39.15 seconds
Started Jan 21 02:12:19 PM PST 24
Finished Jan 21 02:12:59 PM PST 24
Peak memory 219140 kb
Host smart-b27ebe7e-e1af-47ba-910d-d646719151f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953219673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3953219673 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest


Test location /workspace/coverage/default/11.kmac_stress_all_with_rand_reset.3103220355
Short name T41
Test name
Test status
Simulation time 136806611306 ps
CPU time 924.79 seconds
Started Jan 21 01:50:33 PM PST 24
Finished Jan 21 02:06:00 PM PST 24
Peak memory 309664 kb
Host smart-0588c1ee-7efb-41d3-944c-d8bbfc2ffbd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103220355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all_with_rand_reset.3103220355 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.2159848650
Short name T982
Test name
Test status
Simulation time 127070259 ps
CPU time 3.98 seconds
Started Jan 21 02:12:09 PM PST 24
Finished Jan 21 02:12:13 PM PST 24
Peak memory 209024 kb
Host smart-a348e3cb-1e23-45d4-9c77-6966032db819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159848650 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.2159848650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.663476886
Short name T550
Test name
Test status
Simulation time 703455530 ps
CPU time 4.57 seconds
Started Jan 21 01:50:09 PM PST 24
Finished Jan 21 01:50:20 PM PST 24
Peak memory 217180 kb
Host smart-54fadeb3-783f-49ec-8e0e-47a70fb4e896
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663476886 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.kmac_test_vectors_kmac_xof.663476886 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.3188330810
Short name T418
Test name
Test status
Simulation time 77383718116 ps
CPU time 1613.67 seconds
Started Jan 21 01:50:00 PM PST 24
Finished Jan 21 02:16:55 PM PST 24
Peak memory 386792 kb
Host smart-cb3b44cf-79a8-4179-a36e-476c158c17d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3188330810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.3188330810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.1013823853
Short name T252
Test name
Test status
Simulation time 190992766181 ps
CPU time 1942.97 seconds
Started Jan 21 01:50:00 PM PST 24
Finished Jan 21 02:22:24 PM PST 24
Peak memory 374352 kb
Host smart-e0292116-d3f2-4e5e-9c4d-4b53a14f90ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1013823853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.1013823853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.2007492342
Short name T585
Test name
Test status
Simulation time 46342038556 ps
CPU time 1295.07 seconds
Started Jan 21 01:50:00 PM PST 24
Finished Jan 21 02:11:36 PM PST 24
Peak memory 330588 kb
Host smart-44dfd7b6-aab4-4e74-a12f-da60e599fc48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2007492342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.2007492342 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.1975004348
Short name T718
Test name
Test status
Simulation time 99369692376 ps
CPU time 1002.49 seconds
Started Jan 21 01:53:50 PM PST 24
Finished Jan 21 02:10:34 PM PST 24
Peak memory 298088 kb
Host smart-1b0b37a2-82f1-455e-a2e3-65e5c9454a1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1975004348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.1975004348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.4286310390
Short name T869
Test name
Test status
Simulation time 205158718310 ps
CPU time 4269.48 seconds
Started Jan 21 01:55:27 PM PST 24
Finished Jan 21 03:06:41 PM PST 24
Peak memory 659116 kb
Host smart-607142c0-6373-471d-bc61-12f8f96ee311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4286310390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.4286310390 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.3828102406
Short name T747
Test name
Test status
Simulation time 87687123847 ps
CPU time 3550.93 seconds
Started Jan 21 02:32:52 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 554808 kb
Host smart-9f09ad28-91f6-4ce0-bd74-e0e215265186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3828102406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.3828102406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/12.kmac_alert_test.1328272998
Short name T389
Test name
Test status
Simulation time 45508541 ps
CPU time 0.77 seconds
Started Jan 21 01:50:59 PM PST 24
Finished Jan 21 01:51:01 PM PST 24
Peak memory 207184 kb
Host smart-2dc5df95-d5d8-4b18-b800-ce78d6020d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328272998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1328272998 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest


Test location /workspace/coverage/default/12.kmac_app.3886933919
Short name T467
Test name
Test status
Simulation time 21794609435 ps
CPU time 212.04 seconds
Started Jan 21 02:51:04 PM PST 24
Finished Jan 21 02:54:37 PM PST 24
Peak memory 238528 kb
Host smart-f5b058c9-5634-41a9-9fcd-0fbd4ecdf1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886933919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3886933919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest


Test location /workspace/coverage/default/12.kmac_burst_write.4077039104
Short name T773
Test name
Test status
Simulation time 83235343219 ps
CPU time 646.87 seconds
Started Jan 21 01:50:38 PM PST 24
Finished Jan 21 02:01:26 PM PST 24
Peak memory 231660 kb
Host smart-ce7f50e6-4286-4eac-be56-3c56406dba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077039104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.4077039104 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest


Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3106807427
Short name T528
Test name
Test status
Simulation time 266247107 ps
CPU time 18.21 seconds
Started Jan 21 01:50:47 PM PST 24
Finished Jan 21 01:51:06 PM PST 24
Peak memory 223804 kb
Host smart-82938177-74af-41e1-b81c-f562f858b77e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106807427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3106807427 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/12.kmac_entropy_mode_error.3563938530
Short name T1100
Test name
Test status
Simulation time 1869431614 ps
CPU time 23 seconds
Started Jan 21 01:50:48 PM PST 24
Finished Jan 21 01:51:12 PM PST 24
Peak memory 223576 kb
Host smart-19294b0a-0770-4878-a6f1-e3a1a8fb27e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3563938530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3563938530 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/12.kmac_entropy_refresh.3520721093
Short name T233
Test name
Test status
Simulation time 4328376814 ps
CPU time 163.17 seconds
Started Jan 21 01:50:51 PM PST 24
Finished Jan 21 01:53:35 PM PST 24
Peak memory 237132 kb
Host smart-75e0d6c0-d4b4-4b82-9883-c4175946604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520721093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3520721093 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/12.kmac_error.1465239044
Short name T749
Test name
Test status
Simulation time 968482992 ps
CPU time 73.15 seconds
Started Jan 21 01:50:48 PM PST 24
Finished Jan 21 01:52:01 PM PST 24
Peak memory 235404 kb
Host smart-3dfddb23-9ded-4d00-a3fe-fcb6a12fa069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465239044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1465239044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest


Test location /workspace/coverage/default/12.kmac_key_error.3200846737
Short name T786
Test name
Test status
Simulation time 545153128 ps
CPU time 3.26 seconds
Started Jan 21 01:50:50 PM PST 24
Finished Jan 21 01:50:55 PM PST 24
Peak memory 207396 kb
Host smart-b7d2a405-d5af-45c0-a086-8f92081bd060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200846737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3200846737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest


Test location /workspace/coverage/default/12.kmac_lc_escalation.1715064066
Short name T674
Test name
Test status
Simulation time 74006707 ps
CPU time 1.21 seconds
Started Jan 21 01:50:47 PM PST 24
Finished Jan 21 01:50:49 PM PST 24
Peak memory 215772 kb
Host smart-b03b8117-7330-4a6c-bd3f-2253ae42128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715064066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1715064066 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest


Test location /workspace/coverage/default/12.kmac_long_msg_and_output.3911835493
Short name T657
Test name
Test status
Simulation time 121273189097 ps
CPU time 2612.39 seconds
Started Jan 21 01:50:30 PM PST 24
Finished Jan 21 02:34:04 PM PST 24
Peak memory 445592 kb
Host smart-dde9040a-add0-4fb9-b1b7-c81668dba658
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911835493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.3911835493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/12.kmac_sideload.3970154302
Short name T664
Test name
Test status
Simulation time 27119527208 ps
CPU time 328.58 seconds
Started Jan 21 01:50:33 PM PST 24
Finished Jan 21 01:56:03 PM PST 24
Peak memory 247376 kb
Host smart-a2f62006-41a1-4c99-a6b4-e5b9b9e6414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970154302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3970154302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest


Test location /workspace/coverage/default/12.kmac_smoke.489321436
Short name T450
Test name
Test status
Simulation time 5456235137 ps
CPU time 18.28 seconds
Started Jan 21 01:50:29 PM PST 24
Finished Jan 21 01:50:49 PM PST 24
Peak memory 218288 kb
Host smart-fab05fef-db5b-4289-95eb-2a42ab3031bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489321436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.489321436 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest


Test location /workspace/coverage/default/12.kmac_stress_all.899625406
Short name T708
Test name
Test status
Simulation time 77610477736 ps
CPU time 1658.44 seconds
Started Jan 21 01:51:00 PM PST 24
Finished Jan 21 02:18:40 PM PST 24
Peak memory 411860 kb
Host smart-503affe5-5e28-43a0-beb1-73e69e9eee1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=899625406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.899625406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.445266770
Short name T1056
Test name
Test status
Simulation time 3427629657 ps
CPU time 4.97 seconds
Started Jan 21 01:50:39 PM PST 24
Finished Jan 21 01:50:45 PM PST 24
Peak memory 216992 kb
Host smart-70e9bd1a-51d0-44a0-aae2-9001c9535b45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445266770 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.kmac_test_vectors_kmac.445266770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.3791167736
Short name T907
Test name
Test status
Simulation time 434246193 ps
CPU time 4.65 seconds
Started Jan 21 01:50:38 PM PST 24
Finished Jan 21 01:50:44 PM PST 24
Peak memory 217316 kb
Host smart-13aab90a-4ddd-4b5a-a648-337e0b6e2714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791167736 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.3791167736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1103752552
Short name T1002
Test name
Test status
Simulation time 75718862885 ps
CPU time 1604.45 seconds
Started Jan 21 02:38:25 PM PST 24
Finished Jan 21 03:05:10 PM PST 24
Peak memory 393040 kb
Host smart-0eb00594-b1d9-49b3-bb26-2d851c1f919f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1103752552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1103752552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3504863831
Short name T1130
Test name
Test status
Simulation time 243879902016 ps
CPU time 1783.16 seconds
Started Jan 21 01:50:38 PM PST 24
Finished Jan 21 02:20:23 PM PST 24
Peak memory 372104 kb
Host smart-dcc07571-4650-48f0-9a70-4b8eb47be40c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3504863831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3504863831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.47685782
Short name T957
Test name
Test status
Simulation time 218306266762 ps
CPU time 1350.73 seconds
Started Jan 21 01:50:39 PM PST 24
Finished Jan 21 02:13:11 PM PST 24
Peak memory 328420 kb
Host smart-94a9cfb6-042a-4abd-a958-75cc95f95440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=47685782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.47685782 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.3491604056
Short name T738
Test name
Test status
Simulation time 38139268365 ps
CPU time 771.93 seconds
Started Jan 21 01:50:39 PM PST 24
Finished Jan 21 02:03:32 PM PST 24
Peak memory 294244 kb
Host smart-fd416ae9-b606-4eae-ab76-c70e0fcc2760
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3491604056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.3491604056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.3796988567
Short name T248
Test name
Test status
Simulation time 886567681854 ps
CPU time 5102.88 seconds
Started Jan 21 01:50:40 PM PST 24
Finished Jan 21 03:15:44 PM PST 24
Peak memory 644508 kb
Host smart-8b34d233-8b5a-47d8-bf2a-3fa3decbfa90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3796988567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.3796988567 +enable_masking=0 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/13.kmac_alert_test.3908735987
Short name T276
Test name
Test status
Simulation time 13040622 ps
CPU time 0.81 seconds
Started Jan 21 01:51:28 PM PST 24
Finished Jan 21 01:51:30 PM PST 24
Peak memory 207320 kb
Host smart-edc5b906-0633-4333-99f4-6a915cb58078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908735987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3908735987 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest


Test location /workspace/coverage/default/13.kmac_app.3412092709
Short name T269
Test name
Test status
Simulation time 915442158 ps
CPU time 6.95 seconds
Started Jan 21 02:10:46 PM PST 24
Finished Jan 21 02:10:54 PM PST 24
Peak memory 218640 kb
Host smart-381a3b3e-4e4b-49f8-8da6-7cfca2f31531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412092709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3412092709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest


Test location /workspace/coverage/default/13.kmac_burst_write.2268734730
Short name T18
Test name
Test status
Simulation time 5601400966 ps
CPU time 240.61 seconds
Started Jan 21 01:51:10 PM PST 24
Finished Jan 21 01:55:12 PM PST 24
Peak memory 225444 kb
Host smart-d9d29390-c022-440f-9df0-4e32264343f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268734730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2268734730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest


Test location /workspace/coverage/default/13.kmac_edn_timeout_error.3595603954
Short name T1105
Test name
Test status
Simulation time 323509974 ps
CPU time 5.9 seconds
Started Jan 21 01:51:29 PM PST 24
Finished Jan 21 01:51:36 PM PST 24
Peak memory 219808 kb
Host smart-6724249e-760d-41cd-bcef-74a0dae4bb28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3595603954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3595603954 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2497342814
Short name T398
Test name
Test status
Simulation time 183184282 ps
CPU time 13.26 seconds
Started Jan 21 01:51:27 PM PST 24
Finished Jan 21 01:51:40 PM PST 24
Peak memory 221780 kb
Host smart-9073675a-57cf-4577-9e84-3a1a0711513e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2497342814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2497342814 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/13.kmac_entropy_refresh.3035224678
Short name T1141
Test name
Test status
Simulation time 35605657327 ps
CPU time 313.62 seconds
Started Jan 21 01:51:24 PM PST 24
Finished Jan 21 01:56:38 PM PST 24
Peak memory 245896 kb
Host smart-333213d5-2ea9-4e22-a1c5-4e1b81691a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035224678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3035224678 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/13.kmac_error.871203227
Short name T74
Test name
Test status
Simulation time 4127993620 ps
CPU time 282.48 seconds
Started Jan 21 01:51:18 PM PST 24
Finished Jan 21 01:56:01 PM PST 24
Peak memory 256620 kb
Host smart-928e8e72-7be2-4e3f-ac0f-ff0932a472b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871203227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.871203227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest


Test location /workspace/coverage/default/13.kmac_key_error.1886138026
Short name T22
Test name
Test status
Simulation time 135496107 ps
CPU time 1.07 seconds
Started Jan 21 01:51:28 PM PST 24
Finished Jan 21 01:51:30 PM PST 24
Peak memory 207328 kb
Host smart-3ec272c5-de2e-44ef-bb04-c37e26ca41c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886138026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1886138026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest


Test location /workspace/coverage/default/13.kmac_lc_escalation.1923055760
Short name T963
Test name
Test status
Simulation time 47874198 ps
CPU time 1.35 seconds
Started Jan 21 01:51:30 PM PST 24
Finished Jan 21 01:51:32 PM PST 24
Peak memory 215676 kb
Host smart-12ea924a-e492-44d8-a29c-a66cfb482556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923055760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1923055760 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest


Test location /workspace/coverage/default/13.kmac_long_msg_and_output.3135838311
Short name T874
Test name
Test status
Simulation time 36841339261 ps
CPU time 810.41 seconds
Started Jan 21 01:51:00 PM PST 24
Finished Jan 21 02:04:32 PM PST 24
Peak memory 287324 kb
Host smart-16180588-03c5-4645-9510-f6645826dc5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135838311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.3135838311 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/13.kmac_sideload.1890652017
Short name T563
Test name
Test status
Simulation time 6429689791 ps
CPU time 185.18 seconds
Started Jan 21 01:51:06 PM PST 24
Finished Jan 21 01:54:12 PM PST 24
Peak memory 234508 kb
Host smart-0dd6e69f-59fa-4437-8e69-2c29d8587797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890652017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1890652017 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest


Test location /workspace/coverage/default/13.kmac_smoke.3457590431
Short name T835
Test name
Test status
Simulation time 2419543429 ps
CPU time 40.82 seconds
Started Jan 21 01:50:57 PM PST 24
Finished Jan 21 01:51:40 PM PST 24
Peak memory 218760 kb
Host smart-ad9f30d4-1350-4f51-9277-923b058e619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457590431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3457590431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest


Test location /workspace/coverage/default/13.kmac_stress_all.1091578533
Short name T858
Test name
Test status
Simulation time 177311845842 ps
CPU time 906.72 seconds
Started Jan 21 01:51:29 PM PST 24
Finished Jan 21 02:06:37 PM PST 24
Peak memory 353928 kb
Host smart-859d0e8d-29ca-4344-a15e-372e67f99374
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1091578533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1091578533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.1298693919
Short name T186
Test name
Test status
Simulation time 383806757 ps
CPU time 4.14 seconds
Started Jan 21 01:51:17 PM PST 24
Finished Jan 21 01:51:22 PM PST 24
Peak memory 217116 kb
Host smart-80bfcae4-d621-4224-8c40-ca611d9e637e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298693919 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.1298693919 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.693668939
Short name T717
Test name
Test status
Simulation time 1038990232 ps
CPU time 3.86 seconds
Started Jan 21 01:51:16 PM PST 24
Finished Jan 21 01:51:20 PM PST 24
Peak memory 217220 kb
Host smart-1542bf8e-fc75-4c80-802c-2a54d5a51b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693668939 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.kmac_test_vectors_kmac_xof.693668939 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.17888349
Short name T918
Test name
Test status
Simulation time 205027290513 ps
CPU time 2083.43 seconds
Started Jan 21 01:51:07 PM PST 24
Finished Jan 21 02:25:51 PM PST 24
Peak memory 396232 kb
Host smart-ff7e1ac5-168a-496f-a63d-c833bfe01f1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=17888349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.17888349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.3468888785
Short name T488
Test name
Test status
Simulation time 330755182575 ps
CPU time 1799.34 seconds
Started Jan 21 01:51:06 PM PST 24
Finished Jan 21 02:21:07 PM PST 24
Peak memory 373600 kb
Host smart-39c51315-41b0-4d08-a214-899a7937c37a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3468888785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.3468888785 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.3722526355
Short name T292
Test name
Test status
Simulation time 71190717223 ps
CPU time 1002.18 seconds
Started Jan 21 01:51:20 PM PST 24
Finished Jan 21 02:08:03 PM PST 24
Peak memory 298004 kb
Host smart-7d0b0d3f-2508-41a4-a105-f64b1871d84d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3722526355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.3722526355 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.2230939216
Short name T466
Test name
Test status
Simulation time 1126411065791 ps
CPU time 4998.33 seconds
Started Jan 21 01:51:20 PM PST 24
Finished Jan 21 03:14:39 PM PST 24
Peak memory 661544 kb
Host smart-cf5e8694-b81e-428c-8ce3-c9106980d53d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2230939216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2230939216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.4112158843
Short name T327
Test name
Test status
Simulation time 42747194776 ps
CPU time 3361.61 seconds
Started Jan 21 01:51:26 PM PST 24
Finished Jan 21 02:47:28 PM PST 24
Peak memory 551272 kb
Host smart-0a782c0e-df9d-4653-b4e4-31b2a0b39d40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4112158843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.4112158843 +enable_masking=0 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/14.kmac_alert_test.2411664943
Short name T540
Test name
Test status
Simulation time 15592683 ps
CPU time 0.79 seconds
Started Jan 21 02:18:40 PM PST 24
Finished Jan 21 02:18:42 PM PST 24
Peak memory 207340 kb
Host smart-0feb0739-26de-4606-9fec-fd555b057e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411664943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2411664943 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest


Test location /workspace/coverage/default/14.kmac_app.796227229
Short name T750
Test name
Test status
Simulation time 29063387 ps
CPU time 2.09 seconds
Started Jan 21 01:51:45 PM PST 24
Finished Jan 21 01:51:48 PM PST 24
Peak memory 215936 kb
Host smart-59162e79-70af-4151-8b20-0f88e2784a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796227229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.796227229 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest


Test location /workspace/coverage/default/14.kmac_burst_write.716758864
Short name T353
Test name
Test status
Simulation time 8449636732 ps
CPU time 366.28 seconds
Started Jan 21 01:51:27 PM PST 24
Finished Jan 21 01:57:34 PM PST 24
Peak memory 227620 kb
Host smart-da7a6e79-22d6-4774-8d03-cf22b2bd0fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716758864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.716758864 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest


Test location /workspace/coverage/default/14.kmac_edn_timeout_error.220694249
Short name T739
Test name
Test status
Simulation time 926271873 ps
CPU time 12.94 seconds
Started Jan 21 01:51:48 PM PST 24
Finished Jan 21 01:52:02 PM PST 24
Peak memory 220600 kb
Host smart-f83fbc5e-b5d7-4899-8ee0-da2ffbe8f72e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=220694249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.220694249 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/14.kmac_entropy_mode_error.3067192834
Short name T1109
Test name
Test status
Simulation time 847988209 ps
CPU time 11.41 seconds
Started Jan 21 01:51:46 PM PST 24
Finished Jan 21 01:51:58 PM PST 24
Peak memory 223628 kb
Host smart-10a6dea2-cd96-4153-a993-946305f8a58a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3067192834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3067192834 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/14.kmac_entropy_refresh.1619913559
Short name T573
Test name
Test status
Simulation time 302766610 ps
CPU time 8.21 seconds
Started Jan 21 01:51:45 PM PST 24
Finished Jan 21 01:51:54 PM PST 24
Peak memory 220872 kb
Host smart-33a26a1b-f242-4fc7-96aa-85a6482ffe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619913559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1619913559 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/14.kmac_error.3491224173
Short name T482
Test name
Test status
Simulation time 9070653078 ps
CPU time 203.44 seconds
Started Jan 21 03:01:22 PM PST 24
Finished Jan 21 03:04:47 PM PST 24
Peak memory 256496 kb
Host smart-3016bfd9-0f64-4c58-a4e5-636d387d8807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491224173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3491224173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest


Test location /workspace/coverage/default/14.kmac_key_error.2268597223
Short name T546
Test name
Test status
Simulation time 2204963728 ps
CPU time 3.79 seconds
Started Jan 21 01:51:47 PM PST 24
Finished Jan 21 01:51:52 PM PST 24
Peak memory 207576 kb
Host smart-ac68fc9f-7f4e-4284-9797-fa3d9fe31ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268597223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2268597223 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest


Test location /workspace/coverage/default/14.kmac_lc_escalation.3777526033
Short name T659
Test name
Test status
Simulation time 47499268 ps
CPU time 1.36 seconds
Started Jan 21 02:14:53 PM PST 24
Finished Jan 21 02:14:56 PM PST 24
Peak memory 215940 kb
Host smart-c3b1c971-36d9-4f46-8fe6-a19a6a97e934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777526033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3777526033 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest


Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3866405813
Short name T987
Test name
Test status
Simulation time 36526659724 ps
CPU time 1056.31 seconds
Started Jan 21 01:51:28 PM PST 24
Finished Jan 21 02:09:06 PM PST 24
Peak memory 321692 kb
Host smart-c596e622-145e-4dbb-862a-42c77779e366
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866405813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3866405813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/14.kmac_sideload.607186161
Short name T1015
Test name
Test status
Simulation time 2443829259 ps
CPU time 12.96 seconds
Started Jan 21 01:51:31 PM PST 24
Finished Jan 21 01:51:45 PM PST 24
Peak memory 223808 kb
Host smart-ad8870d0-325b-4d1d-ac10-c247238d80a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607186161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.607186161 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest


Test location /workspace/coverage/default/14.kmac_smoke.1751701645
Short name T1083
Test name
Test status
Simulation time 2689945297 ps
CPU time 35.66 seconds
Started Jan 21 01:51:29 PM PST 24
Finished Jan 21 01:52:05 PM PST 24
Peak memory 218716 kb
Host smart-7794fabb-4a4c-4b4d-b165-4b2d4c74c14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751701645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1751701645 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest


Test location /workspace/coverage/default/14.kmac_stress_all.1376054653
Short name T541
Test name
Test status
Simulation time 190131723525 ps
CPU time 1132.94 seconds
Started Jan 21 02:17:57 PM PST 24
Finished Jan 21 02:36:51 PM PST 24
Peak memory 363116 kb
Host smart-ca035e5f-4df3-429f-81a1-05701dec650d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1376054653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1376054653 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest


Test location /workspace/coverage/default/14.kmac_stress_all_with_rand_reset.1447670844
Short name T932
Test name
Test status
Simulation time 76045822397 ps
CPU time 1498.65 seconds
Started Jan 21 02:42:08 PM PST 24
Finished Jan 21 03:07:07 PM PST 24
Peak memory 322496 kb
Host smart-4f544c13-2223-4635-90aa-caef61d7c064
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447670844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.1447670844 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.4170876026
Short name T350
Test name
Test status
Simulation time 416398091 ps
CPU time 4.63 seconds
Started Jan 21 01:51:38 PM PST 24
Finished Jan 21 01:51:44 PM PST 24
Peak memory 216648 kb
Host smart-ff81ce2e-1918-4785-adad-04c46d8ce156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170876026 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.4170876026 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.3265296982
Short name T1084
Test name
Test status
Simulation time 882550101 ps
CPU time 4.73 seconds
Started Jan 21 01:51:45 PM PST 24
Finished Jan 21 01:51:50 PM PST 24
Peak memory 216812 kb
Host smart-209de964-b068-4a29-97cd-f84902045b47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265296982 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.3265296982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.160019937
Short name T695
Test name
Test status
Simulation time 1064349159016 ps
CPU time 2165.08 seconds
Started Jan 21 01:51:44 PM PST 24
Finished Jan 21 02:27:51 PM PST 24
Peak memory 377968 kb
Host smart-21d69bed-181b-43ec-adee-c076081af3f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=160019937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.160019937 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.415318742
Short name T771
Test name
Test status
Simulation time 72982945256 ps
CPU time 1490.95 seconds
Started Jan 21 01:51:39 PM PST 24
Finished Jan 21 02:16:31 PM PST 24
Peak memory 369164 kb
Host smart-38656428-7cd5-4b32-8d80-3c6aeeb7db51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=415318742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.415318742 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.4040499574
Short name T782
Test name
Test status
Simulation time 138497522971 ps
CPU time 1475.51 seconds
Started Jan 21 01:51:40 PM PST 24
Finished Jan 21 02:16:17 PM PST 24
Peak memory 331132 kb
Host smart-8f5f3aa4-3992-415b-a7c9-f19b021b5679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4040499574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.4040499574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.1384286808
Short name T900
Test name
Test status
Simulation time 67566991375 ps
CPU time 920.82 seconds
Started Jan 21 01:51:44 PM PST 24
Finished Jan 21 02:07:06 PM PST 24
Peak memory 293368 kb
Host smart-c69e8b14-81ee-4350-b788-d01ab011fe71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1384286808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.1384286808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.2969628524
Short name T847
Test name
Test status
Simulation time 236993882828 ps
CPU time 4855.89 seconds
Started Jan 21 01:51:43 PM PST 24
Finished Jan 21 03:12:41 PM PST 24
Peak memory 659628 kb
Host smart-dfc5cf89-6550-4d9d-87e4-05b581db99be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2969628524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.2969628524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.725317057
Short name T794
Test name
Test status
Simulation time 640298823666 ps
CPU time 4084.3 seconds
Started Jan 21 01:51:45 PM PST 24
Finished Jan 21 02:59:50 PM PST 24
Peak memory 572044 kb
Host smart-e3e68068-666e-4d64-abd2-52612f7255de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=725317057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.725317057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/15.kmac_alert_test.321898844
Short name T340
Test name
Test status
Simulation time 58440422 ps
CPU time 0.85 seconds
Started Jan 21 02:17:46 PM PST 24
Finished Jan 21 02:17:48 PM PST 24
Peak memory 207192 kb
Host smart-041d3d2a-b455-4120-ba32-1f6d11218b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321898844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.321898844 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest


Test location /workspace/coverage/default/15.kmac_app.2793997122
Short name T938
Test name
Test status
Simulation time 28655890761 ps
CPU time 64.17 seconds
Started Jan 21 01:52:20 PM PST 24
Finished Jan 21 01:53:25 PM PST 24
Peak memory 225660 kb
Host smart-32f82a6e-1904-46c1-a2cf-3869f68e1c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793997122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2793997122 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest


Test location /workspace/coverage/default/15.kmac_burst_write.1746974381
Short name T832
Test name
Test status
Simulation time 13125617177 ps
CPU time 390.08 seconds
Started Jan 21 01:51:53 PM PST 24
Finished Jan 21 01:58:24 PM PST 24
Peak memory 227732 kb
Host smart-7bc2c613-a85f-4bab-ae2b-8135e9cd3e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746974381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1746974381 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest


Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1920126175
Short name T561
Test name
Test status
Simulation time 282275620 ps
CPU time 11.41 seconds
Started Jan 21 01:52:20 PM PST 24
Finished Jan 21 01:52:32 PM PST 24
Peak memory 220804 kb
Host smart-be782592-f29b-41a8-abe6-d84bd045f9ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1920126175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1920126175 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/15.kmac_entropy_mode_error.525926821
Short name T709
Test name
Test status
Simulation time 3182609413 ps
CPU time 25.18 seconds
Started Jan 21 01:52:27 PM PST 24
Finished Jan 21 01:53:04 PM PST 24
Peak memory 223560 kb
Host smart-8c8ef0ce-44e1-4221-8ed1-0ad801429682
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=525926821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.525926821 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/15.kmac_entropy_refresh.3481498181
Short name T733
Test name
Test status
Simulation time 15953461744 ps
CPU time 166.4 seconds
Started Jan 21 01:52:21 PM PST 24
Finished Jan 21 01:55:10 PM PST 24
Peak memory 238532 kb
Host smart-eadb1ab7-b35a-4818-94fc-8795cb3b5e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481498181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3481498181 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/15.kmac_error.1933414874
Short name T598
Test name
Test status
Simulation time 2019822184 ps
CPU time 73.64 seconds
Started Jan 21 01:52:19 PM PST 24
Finished Jan 21 01:53:34 PM PST 24
Peak memory 235864 kb
Host smart-d17f50ce-70ae-44d0-98be-3c5679332765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933414874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1933414874 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest


Test location /workspace/coverage/default/15.kmac_key_error.2922896904
Short name T66
Test name
Test status
Simulation time 3119047741 ps
CPU time 5.5 seconds
Started Jan 21 01:52:19 PM PST 24
Finished Jan 21 01:52:26 PM PST 24
Peak memory 207860 kb
Host smart-193bd5bd-a106-460e-86b1-ac0c1ee28d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922896904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2922896904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest


Test location /workspace/coverage/default/15.kmac_lc_escalation.2286036634
Short name T254
Test name
Test status
Simulation time 111252872 ps
CPU time 1.11 seconds
Started Jan 21 01:52:28 PM PST 24
Finished Jan 21 01:52:40 PM PST 24
Peak memory 219324 kb
Host smart-15a5d2f1-dc78-4f4c-bcc1-61e9faf8d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286036634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2286036634 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest


Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1442130341
Short name T226
Test name
Test status
Simulation time 26883024283 ps
CPU time 573.78 seconds
Started Jan 21 02:31:14 PM PST 24
Finished Jan 21 02:40:49 PM PST 24
Peak memory 282716 kb
Host smart-7aef7f6c-c7d7-45ea-8f1d-1cf1f11d0f99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442130341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1442130341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/15.kmac_sideload.3521639953
Short name T753
Test name
Test status
Simulation time 976745540 ps
CPU time 71.27 seconds
Started Jan 21 01:51:53 PM PST 24
Finished Jan 21 01:53:05 PM PST 24
Peak memory 224152 kb
Host smart-1a1ab2df-3d07-4c7e-ba13-0a4a9dfb4597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521639953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3521639953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest


Test location /workspace/coverage/default/15.kmac_smoke.3894579352
Short name T1086
Test name
Test status
Simulation time 2536935348 ps
CPU time 21.33 seconds
Started Jan 21 01:51:54 PM PST 24
Finished Jan 21 01:52:16 PM PST 24
Peak memory 218104 kb
Host smart-93633768-e358-49f9-89a1-9bca51450eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894579352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3894579352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest


Test location /workspace/coverage/default/15.kmac_stress_all.4050626884
Short name T720
Test name
Test status
Simulation time 20592582989 ps
CPU time 812.72 seconds
Started Jan 21 01:52:28 PM PST 24
Finished Jan 21 02:06:12 PM PST 24
Peak memory 314404 kb
Host smart-54bb10b8-0440-4c5f-889f-a1476f4eba9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4050626884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.4050626884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.2595116314
Short name T801
Test name
Test status
Simulation time 182326389 ps
CPU time 4.97 seconds
Started Jan 21 01:52:14 PM PST 24
Finished Jan 21 01:52:20 PM PST 24
Peak memory 217172 kb
Host smart-65d0e946-2935-4a06-81e1-7b62843d3aaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595116314 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.2595116314 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.317211231
Short name T682
Test name
Test status
Simulation time 85317802 ps
CPU time 3.87 seconds
Started Jan 21 01:52:20 PM PST 24
Finished Jan 21 01:52:25 PM PST 24
Peak memory 208744 kb
Host smart-0166785b-c2f2-4e13-8d56-e126c05555df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317211231 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.kmac_test_vectors_kmac_xof.317211231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.2893780303
Short name T1008
Test name
Test status
Simulation time 18790320674 ps
CPU time 1588.26 seconds
Started Jan 21 02:30:24 PM PST 24
Finished Jan 21 02:56:53 PM PST 24
Peak memory 391340 kb
Host smart-568830c2-232d-4a6a-b03e-efa4b288cb4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2893780303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.2893780303 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.1569374152
Short name T896
Test name
Test status
Simulation time 366932481094 ps
CPU time 1935.51 seconds
Started Jan 21 02:12:10 PM PST 24
Finished Jan 21 02:44:26 PM PST 24
Peak memory 387152 kb
Host smart-83686ff4-1a05-4d6c-be41-190ddf9bee55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1569374152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.1569374152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.4178351162
Short name T798
Test name
Test status
Simulation time 54276608362 ps
CPU time 1184.87 seconds
Started Jan 21 03:23:23 PM PST 24
Finished Jan 21 03:43:08 PM PST 24
Peak memory 333568 kb
Host smart-09a71e01-2b2f-4592-b785-461c41a7e02c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4178351162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.4178351162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2675323616
Short name T636
Test name
Test status
Simulation time 38623359535 ps
CPU time 786.98 seconds
Started Jan 21 02:42:13 PM PST 24
Finished Jan 21 02:55:20 PM PST 24
Peak memory 290212 kb
Host smart-f2156ae2-cb4d-4e59-bf0f-b36a7671886f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2675323616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2675323616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.2448267203
Short name T885
Test name
Test status
Simulation time 53851553854 ps
CPU time 4174.89 seconds
Started Jan 21 01:52:11 PM PST 24
Finished Jan 21 03:01:47 PM PST 24
Peak memory 645292 kb
Host smart-e16a0369-16c5-4738-a339-058e1b53aba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2448267203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.2448267203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.171940652
Short name T225
Test name
Test status
Simulation time 84960576532 ps
CPU time 3469.21 seconds
Started Jan 21 02:42:05 PM PST 24
Finished Jan 21 03:39:55 PM PST 24
Peak memory 546276 kb
Host smart-fe22e4cc-ca9b-4270-8aa0-599a346d1b06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=171940652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.171940652 +enable_masking=0 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/16.kmac_alert_test.2634696086
Short name T205
Test name
Test status
Simulation time 34181039 ps
CPU time 0.82 seconds
Started Jan 21 01:53:01 PM PST 24
Finished Jan 21 01:53:07 PM PST 24
Peak memory 207316 kb
Host smart-24ddcc6e-b606-484a-8624-382e6f01c9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634696086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2634696086 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest


Test location /workspace/coverage/default/16.kmac_app.1611305091
Short name T878
Test name
Test status
Simulation time 19329380129 ps
CPU time 42.62 seconds
Started Jan 21 01:52:54 PM PST 24
Finished Jan 21 01:53:38 PM PST 24
Peak memory 223792 kb
Host smart-d69004a5-c14b-4780-bc62-7a5e4dab0ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611305091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1611305091 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest


Test location /workspace/coverage/default/16.kmac_burst_write.3740146869
Short name T536
Test name
Test status
Simulation time 15788646606 ps
CPU time 652.57 seconds
Started Jan 21 03:15:57 PM PST 24
Finished Jan 21 03:26:52 PM PST 24
Peak memory 230804 kb
Host smart-794b821a-639a-40e7-bdbd-a3cceebd9d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740146869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3740146869 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest


Test location /workspace/coverage/default/16.kmac_edn_timeout_error.2432656231
Short name T253
Test name
Test status
Simulation time 2276028337 ps
CPU time 34.16 seconds
Started Jan 21 01:52:57 PM PST 24
Finished Jan 21 01:53:32 PM PST 24
Peak memory 237016 kb
Host smart-ccfe6039-452c-43ad-afc9-12beaea72011
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2432656231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2432656231 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3949921472
Short name T552
Test name
Test status
Simulation time 3117159851 ps
CPU time 18.19 seconds
Started Jan 21 01:52:55 PM PST 24
Finished Jan 21 01:53:16 PM PST 24
Peak memory 223732 kb
Host smart-46f60062-ac74-4bfd-b214-56ed1ea3c2d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3949921472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3949921472 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/16.kmac_entropy_refresh.1881382619
Short name T737
Test name
Test status
Simulation time 16873622407 ps
CPU time 71.08 seconds
Started Jan 21 01:52:57 PM PST 24
Finished Jan 21 01:54:13 PM PST 24
Peak memory 224364 kb
Host smart-32664587-c90b-4a7c-84f2-5e2f093ffd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881382619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1881382619 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/16.kmac_error.2702981989
Short name T1098
Test name
Test status
Simulation time 2539481480 ps
CPU time 72.03 seconds
Started Jan 21 01:52:55 PM PST 24
Finished Jan 21 01:54:09 PM PST 24
Peak memory 235160 kb
Host smart-323f2f72-0609-47d0-a140-2c57c479481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702981989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2702981989 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest


Test location /workspace/coverage/default/16.kmac_key_error.3860277521
Short name T23
Test name
Test status
Simulation time 1076230952 ps
CPU time 3.01 seconds
Started Jan 21 01:52:57 PM PST 24
Finished Jan 21 01:53:01 PM PST 24
Peak memory 207496 kb
Host smart-f8f10438-d80a-4f67-a232-e6df72c57769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860277521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3860277521 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest


Test location /workspace/coverage/default/16.kmac_lc_escalation.2331159324
Short name T594
Test name
Test status
Simulation time 47074699 ps
CPU time 1.34 seconds
Started Jan 21 02:17:35 PM PST 24
Finished Jan 21 02:17:41 PM PST 24
Peak memory 215792 kb
Host smart-70a7c8a0-be46-406a-9280-9b95e75c5bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331159324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2331159324 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest


Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3590999118
Short name T903
Test name
Test status
Simulation time 50201764085 ps
CPU time 718.27 seconds
Started Jan 21 01:52:29 PM PST 24
Finished Jan 21 02:04:38 PM PST 24
Peak memory 286036 kb
Host smart-ef05d0d6-9c66-4a00-b5ef-1ccca71c456f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590999118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3590999118 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/16.kmac_sideload.764023220
Short name T576
Test name
Test status
Simulation time 2842888572 ps
CPU time 202.92 seconds
Started Jan 21 01:52:29 PM PST 24
Finished Jan 21 01:56:02 PM PST 24
Peak memory 239564 kb
Host smart-b86fcf98-99fd-4ca2-ace6-274af3a6bd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764023220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.764023220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest


Test location /workspace/coverage/default/16.kmac_smoke.769028061
Short name T1117
Test name
Test status
Simulation time 4818181646 ps
CPU time 25.19 seconds
Started Jan 21 01:52:28 PM PST 24
Finished Jan 21 01:53:04 PM PST 24
Peak memory 218500 kb
Host smart-fef06be7-6f83-43b4-b3ee-ca807fef0048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769028061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.769028061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest


Test location /workspace/coverage/default/16.kmac_stress_all.847396128
Short name T814
Test name
Test status
Simulation time 3457053456 ps
CPU time 170.58 seconds
Started Jan 21 01:52:58 PM PST 24
Finished Jan 21 01:55:56 PM PST 24
Peak memory 265120 kb
Host smart-fdeba91b-90b6-4fa4-b7d6-12771633170c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=847396128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.847396128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest


Test location /workspace/coverage/default/16.kmac_stress_all_with_rand_reset.207920935
Short name T629
Test name
Test status
Simulation time 69058193480 ps
CPU time 421.76 seconds
Started Jan 21 01:52:52 PM PST 24
Finished Jan 21 01:59:55 PM PST 24
Peak memory 265084 kb
Host smart-b5668221-4998-49ec-bce9-be3bd3c31679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207920935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.207920935 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.2056497082
Short name T207
Test name
Test status
Simulation time 164708365 ps
CPU time 4.44 seconds
Started Jan 21 01:52:45 PM PST 24
Finished Jan 21 01:52:55 PM PST 24
Peak memory 208864 kb
Host smart-96e443a9-a452-4bc6-8732-f54710cfbe5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056497082 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.2056497082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2989736685
Short name T378
Test name
Test status
Simulation time 176842966 ps
CPU time 3.53 seconds
Started Jan 21 02:04:15 PM PST 24
Finished Jan 21 02:04:21 PM PST 24
Peak memory 209048 kb
Host smart-2814cced-1638-43e7-9dc3-ca0b66ff9e53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989736685 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2989736685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.4268189090
Short name T492
Test name
Test status
Simulation time 75007525144 ps
CPU time 1605.35 seconds
Started Jan 21 01:52:39 PM PST 24
Finished Jan 21 02:19:32 PM PST 24
Peak memory 390240 kb
Host smart-7d3e54f5-8a23-4362-8014-c4cc508c25e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4268189090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.4268189090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.1750442165
Short name T311
Test name
Test status
Simulation time 18182824921 ps
CPU time 1494.38 seconds
Started Jan 21 01:52:38 PM PST 24
Finished Jan 21 02:17:41 PM PST 24
Peak memory 390072 kb
Host smart-f7ae01b3-12e9-4526-a415-7e42bb16ba67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1750442165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1750442165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1573576302
Short name T267
Test name
Test status
Simulation time 194961673432 ps
CPU time 1391.41 seconds
Started Jan 21 02:35:40 PM PST 24
Finished Jan 21 02:58:53 PM PST 24
Peak memory 333488 kb
Host smart-cdbe60c4-2237-43e2-9fdf-dee2c2ed374b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1573576302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1573576302 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.17870513
Short name T964
Test name
Test status
Simulation time 9517695994 ps
CPU time 782.64 seconds
Started Jan 21 02:22:36 PM PST 24
Finished Jan 21 02:35:39 PM PST 24
Peak memory 294112 kb
Host smart-a08a4612-c3c8-4f7a-9729-b1b509eda415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=17870513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.17870513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.2570184770
Short name T250
Test name
Test status
Simulation time 213822354122 ps
CPU time 4324.75 seconds
Started Jan 21 01:52:43 PM PST 24
Finished Jan 21 03:04:55 PM PST 24
Peak memory 658540 kb
Host smart-57951206-2dd6-4a26-9300-3a9d60375cfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2570184770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.2570184770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.1091650210
Short name T619
Test name
Test status
Simulation time 149704451993 ps
CPU time 3983.18 seconds
Started Jan 21 01:52:44 PM PST 24
Finished Jan 21 02:59:14 PM PST 24
Peak memory 568472 kb
Host smart-ace91333-b5a8-458e-84d5-7741cd2e9310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1091650210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.1091650210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/17.kmac_alert_test.1745395713
Short name T766
Test name
Test status
Simulation time 54109726 ps
CPU time 0.78 seconds
Started Jan 21 01:53:54 PM PST 24
Finished Jan 21 01:53:55 PM PST 24
Peak memory 207308 kb
Host smart-ae83bc20-31d9-4727-bd19-bc8a668f9634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745395713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1745395713 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest


Test location /workspace/coverage/default/17.kmac_app.2800275774
Short name T1131
Test name
Test status
Simulation time 296956423 ps
CPU time 8.81 seconds
Started Jan 21 02:17:37 PM PST 24
Finished Jan 21 02:17:48 PM PST 24
Peak memory 223732 kb
Host smart-0de23b1b-45f5-4d8c-94f1-1bb46931d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800275774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2800275774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest


Test location /workspace/coverage/default/17.kmac_burst_write.3374448959
Short name T603
Test name
Test status
Simulation time 10853540347 ps
CPU time 64.12 seconds
Started Jan 21 01:53:08 PM PST 24
Finished Jan 21 01:54:14 PM PST 24
Peak memory 223924 kb
Host smart-43d7af8e-d67a-42a7-afb1-d3dd793b4ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374448959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3374448959 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest


Test location /workspace/coverage/default/17.kmac_edn_timeout_error.2241485219
Short name T1120
Test name
Test status
Simulation time 302343140 ps
CPU time 11.64 seconds
Started Jan 21 01:53:47 PM PST 24
Finished Jan 21 01:53:59 PM PST 24
Peak memory 220572 kb
Host smart-e390d104-f4c8-4f03-b4cd-b0d0ab76f3e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2241485219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2241485219 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/17.kmac_entropy_mode_error.3466463880
Short name T277
Test name
Test status
Simulation time 284339364 ps
CPU time 18.24 seconds
Started Jan 21 01:53:44 PM PST 24
Finished Jan 21 01:54:03 PM PST 24
Peak memory 223592 kb
Host smart-8caac1f2-36b3-4dc1-930f-4fc38b1047c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3466463880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3466463880 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/17.kmac_entropy_refresh.263788489
Short name T593
Test name
Test status
Simulation time 95585018584 ps
CPU time 132.84 seconds
Started Jan 21 02:23:39 PM PST 24
Finished Jan 21 02:25:53 PM PST 24
Peak memory 228020 kb
Host smart-56786c48-ce03-45d4-a3fc-fb225916ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263788489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.263788489 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/17.kmac_error.3068418457
Short name T571
Test name
Test status
Simulation time 13326902600 ps
CPU time 378.01 seconds
Started Jan 21 01:53:37 PM PST 24
Finished Jan 21 01:59:56 PM PST 24
Peak memory 256588 kb
Host smart-170a5266-b84c-4391-b110-8012b0b612d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068418457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3068418457 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest


Test location /workspace/coverage/default/17.kmac_lc_escalation.913764612
Short name T740
Test name
Test status
Simulation time 35507277 ps
CPU time 1.26 seconds
Started Jan 21 01:53:45 PM PST 24
Finished Jan 21 01:53:47 PM PST 24
Peak memory 219632 kb
Host smart-4c57f09f-cbd3-488c-a4d8-9ed271ff2609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913764612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.913764612 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/17.kmac_lc_escalation/latest


Test location /workspace/coverage/default/17.kmac_long_msg_and_output.3811216748
Short name T1012
Test name
Test status
Simulation time 48641070736 ps
CPU time 1138.94 seconds
Started Jan 21 01:53:01 PM PST 24
Finished Jan 21 02:12:05 PM PST 24
Peak memory 340416 kb
Host smart-1e48e35e-105a-4fb9-874a-08a0d0ec62fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811216748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.3811216748 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/17.kmac_sideload.2904621895
Short name T827
Test name
Test status
Simulation time 22175656453 ps
CPU time 271.13 seconds
Started Jan 21 01:52:59 PM PST 24
Finished Jan 21 01:57:37 PM PST 24
Peak memory 242676 kb
Host smart-19638cdd-e177-4aee-9e86-f5fb75240c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904621895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2904621895 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest


Test location /workspace/coverage/default/17.kmac_smoke.1569125532
Short name T998
Test name
Test status
Simulation time 15758045366 ps
CPU time 67.4 seconds
Started Jan 21 01:53:02 PM PST 24
Finished Jan 21 01:54:13 PM PST 24
Peak memory 219048 kb
Host smart-5aa23715-46ec-4a6d-acdf-f76caee6985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569125532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1569125532 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest


Test location /workspace/coverage/default/17.kmac_stress_all.627227852
Short name T40
Test name
Test status
Simulation time 76551168158 ps
CPU time 242.13 seconds
Started Jan 21 01:53:46 PM PST 24
Finished Jan 21 01:57:49 PM PST 24
Peak memory 269440 kb
Host smart-ac5cedb1-9b14-4065-9be8-3bb093c7f680
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=627227852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.627227852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.3050693622
Short name T843
Test name
Test status
Simulation time 260606531 ps
CPU time 5.03 seconds
Started Jan 21 01:53:25 PM PST 24
Finished Jan 21 01:53:31 PM PST 24
Peak memory 216980 kb
Host smart-0dc1eb96-e7fc-4f0a-9784-0a8273aa1830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050693622 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.3050693622 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.2436559931
Short name T1031
Test name
Test status
Simulation time 1026684337 ps
CPU time 4.37 seconds
Started Jan 21 01:53:26 PM PST 24
Finished Jan 21 01:53:32 PM PST 24
Peak memory 208924 kb
Host smart-a3a3b2d4-6e16-4b00-8157-55c22380e309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436559931 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.2436559931 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.1556472866
Short name T17
Test name
Test status
Simulation time 129149750030 ps
CPU time 1812.64 seconds
Started Jan 21 02:21:15 PM PST 24
Finished Jan 21 02:51:29 PM PST 24
Peak memory 375420 kb
Host smart-d1a327cf-c425-478a-96f6-9d21e6e49284
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1556472866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1556472866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.308309823
Short name T866
Test name
Test status
Simulation time 18263439372 ps
CPU time 1529.49 seconds
Started Jan 21 01:53:19 PM PST 24
Finished Jan 21 02:18:49 PM PST 24
Peak memory 377384 kb
Host smart-b0672fb6-da43-400c-89b8-167a225c43e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=308309823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.308309823 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.351692259
Short name T503
Test name
Test status
Simulation time 119621690510 ps
CPU time 1335.79 seconds
Started Jan 21 01:53:19 PM PST 24
Finished Jan 21 02:15:37 PM PST 24
Peak memory 334336 kb
Host smart-053242ea-728b-41ee-a69f-b670d1393fad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=351692259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.351692259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.1673613882
Short name T716
Test name
Test status
Simulation time 33979982548 ps
CPU time 939.26 seconds
Started Jan 21 01:53:17 PM PST 24
Finished Jan 21 02:08:58 PM PST 24
Peak memory 298000 kb
Host smart-e3792c8a-b531-4f4e-8b34-74b08ee5622b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1673613882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1673613882 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.882656082
Short name T1029
Test name
Test status
Simulation time 457694044252 ps
CPU time 4236.22 seconds
Started Jan 21 01:53:19 PM PST 24
Finished Jan 21 03:03:57 PM PST 24
Peak memory 640124 kb
Host smart-a30e86ed-da63-42ad-891e-7a7dfdefbcca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=882656082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.882656082 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.2945838469
Short name T875
Test name
Test status
Simulation time 393013677237 ps
CPU time 3624.36 seconds
Started Jan 21 01:53:18 PM PST 24
Finished Jan 21 02:53:44 PM PST 24
Peak memory 560040 kb
Host smart-49455b3f-3f80-4908-b490-b759870bf73d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2945838469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.2945838469 +enable_masking=0 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/18.kmac_alert_test.1245101524
Short name T945
Test name
Test status
Simulation time 16352507 ps
CPU time 0.78 seconds
Started Jan 21 01:54:13 PM PST 24
Finished Jan 21 01:54:14 PM PST 24
Peak memory 207220 kb
Host smart-9180bbf1-db87-4404-92ad-e8610ba4450b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245101524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1245101524 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest


Test location /workspace/coverage/default/18.kmac_app.667683327
Short name T876
Test name
Test status
Simulation time 63819257288 ps
CPU time 304.48 seconds
Started Jan 21 01:54:03 PM PST 24
Finished Jan 21 01:59:08 PM PST 24
Peak memory 245240 kb
Host smart-46531026-b9e9-43a4-a3b9-b3e429a76e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667683327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.667683327 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest


Test location /workspace/coverage/default/18.kmac_burst_write.787468389
Short name T780
Test name
Test status
Simulation time 25489819892 ps
CPU time 430.79 seconds
Started Jan 21 01:53:54 PM PST 24
Finished Jan 21 02:01:05 PM PST 24
Peak memory 227112 kb
Host smart-88dd71e0-be9b-4d40-ba6a-fcc78b97de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787468389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.787468389 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest


Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1525776042
Short name T816
Test name
Test status
Simulation time 447971645 ps
CPU time 34.6 seconds
Started Jan 21 01:54:12 PM PST 24
Finished Jan 21 01:54:47 PM PST 24
Peak memory 223496 kb
Host smart-0bcd0ee4-0708-44b3-a4f3-608ae88d62cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1525776042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1525776042 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/18.kmac_entropy_mode_error.800362759
Short name T934
Test name
Test status
Simulation time 1454092371 ps
CPU time 6.63 seconds
Started Jan 21 01:54:12 PM PST 24
Finished Jan 21 01:54:19 PM PST 24
Peak memory 217668 kb
Host smart-aef05d4e-2b42-416b-88e5-4c91d9c76488
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800362759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.800362759 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/18.kmac_entropy_refresh.517195464
Short name T134
Test name
Test status
Simulation time 13413544062 ps
CPU time 278.58 seconds
Started Jan 21 01:54:04 PM PST 24
Finished Jan 21 01:58:44 PM PST 24
Peak memory 243784 kb
Host smart-9ddc3f7e-489a-4593-aaa4-8002cd5079a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517195464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.517195464 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/18.kmac_error.369606212
Short name T542
Test name
Test status
Simulation time 3076310270 ps
CPU time 194.9 seconds
Started Jan 21 01:54:02 PM PST 24
Finished Jan 21 01:57:17 PM PST 24
Peak memory 248696 kb
Host smart-b6d7f12c-cbda-4724-8581-709a773f2790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369606212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.369606212 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest


Test location /workspace/coverage/default/18.kmac_key_error.2118113337
Short name T727
Test name
Test status
Simulation time 3087557002 ps
CPU time 4.62 seconds
Started Jan 21 01:54:01 PM PST 24
Finished Jan 21 01:54:06 PM PST 24
Peak memory 207528 kb
Host smart-67ae7fbd-0b86-4645-afe8-851e5b312837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118113337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2118113337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest


Test location /workspace/coverage/default/18.kmac_lc_escalation.3250581159
Short name T805
Test name
Test status
Simulation time 75542465 ps
CPU time 1.3 seconds
Started Jan 21 02:18:07 PM PST 24
Finished Jan 21 02:18:09 PM PST 24
Peak memory 215848 kb
Host smart-540e164b-540e-434e-a397-0b9783b6d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250581159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3250581159 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest


Test location /workspace/coverage/default/18.kmac_long_msg_and_output.3625101167
Short name T449
Test name
Test status
Simulation time 46469267528 ps
CPU time 2039.66 seconds
Started Jan 21 02:05:08 PM PST 24
Finished Jan 21 02:39:09 PM PST 24
Peak memory 440964 kb
Host smart-11e500b8-2c4c-40eb-b2de-776fd22dddc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625101167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.3625101167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/18.kmac_sideload.2383579857
Short name T1091
Test name
Test status
Simulation time 30059924031 ps
CPU time 150.09 seconds
Started Jan 21 01:53:54 PM PST 24
Finished Jan 21 01:56:25 PM PST 24
Peak memory 229236 kb
Host smart-a9c0a915-632d-4206-8564-7ca07e21c78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383579857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2383579857 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest


Test location /workspace/coverage/default/18.kmac_smoke.757458416
Short name T484
Test name
Test status
Simulation time 4199223761 ps
CPU time 25 seconds
Started Jan 21 01:53:53 PM PST 24
Finished Jan 21 01:54:19 PM PST 24
Peak memory 218512 kb
Host smart-2940a01e-0f93-4a41-adef-a9bb1856baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757458416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.757458416 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest


Test location /workspace/coverage/default/18.kmac_stress_all.534453513
Short name T768
Test name
Test status
Simulation time 13154992180 ps
CPU time 988.15 seconds
Started Jan 21 02:52:49 PM PST 24
Finished Jan 21 03:09:22 PM PST 24
Peak memory 338852 kb
Host smart-0dd532a9-111d-4216-af97-0d2749ca6900
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=534453513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.534453513 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest


Test location /workspace/coverage/default/18.kmac_stress_all_with_rand_reset.3918884155
Short name T602
Test name
Test status
Simulation time 32683727115 ps
CPU time 979.89 seconds
Started Jan 21 01:54:12 PM PST 24
Finished Jan 21 02:10:33 PM PST 24
Peak memory 325688 kb
Host smart-92c77748-75e0-4948-89b2-3680fa10a7b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918884155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all_with_rand_reset.3918884155 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.49927143
Short name T217
Test name
Test status
Simulation time 127199165 ps
CPU time 3.78 seconds
Started Jan 21 01:53:53 PM PST 24
Finished Jan 21 01:53:58 PM PST 24
Peak memory 208984 kb
Host smart-5ca15ecc-3dcf-4c0d-8826-1d55650df8de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49927143 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.kmac_test_vectors_kmac.49927143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.954190257
Short name T1020
Test name
Test status
Simulation time 324487208 ps
CPU time 4.3 seconds
Started Jan 21 01:54:05 PM PST 24
Finished Jan 21 01:54:10 PM PST 24
Peak memory 208888 kb
Host smart-ae36b952-ce66-4a07-ae62-7321841c4419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954190257 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.kmac_test_vectors_kmac_xof.954190257 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.1808993685
Short name T133
Test name
Test status
Simulation time 19444174893 ps
CPU time 1592.97 seconds
Started Jan 21 01:53:54 PM PST 24
Finished Jan 21 02:20:28 PM PST 24
Peak memory 388112 kb
Host smart-45c8216b-e6ea-4ef5-9dbf-47c20e33921d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1808993685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.1808993685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.2132872309
Short name T437
Test name
Test status
Simulation time 307998197565 ps
CPU time 1899.64 seconds
Started Jan 21 02:17:06 PM PST 24
Finished Jan 21 02:48:47 PM PST 24
Peak memory 376616 kb
Host smart-e4864b59-e8c3-4051-a7b6-b39f5a5e585d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2132872309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.2132872309 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3764860709
Short name T930
Test name
Test status
Simulation time 78845957841 ps
CPU time 1172.44 seconds
Started Jan 21 01:53:53 PM PST 24
Finished Jan 21 02:13:26 PM PST 24
Peak memory 330548 kb
Host smart-c6eddc35-ea6b-4eed-a110-2e32fa3b8c66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3764860709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3764860709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1721511455
Short name T472
Test name
Test status
Simulation time 51773061771 ps
CPU time 1077.07 seconds
Started Jan 21 01:53:53 PM PST 24
Finished Jan 21 02:11:50 PM PST 24
Peak memory 301876 kb
Host smart-998e0b24-e921-4794-a789-72dc25225134
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1721511455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1721511455 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.1717307671
Short name T284
Test name
Test status
Simulation time 1010573109563 ps
CPU time 4464.33 seconds
Started Jan 21 01:53:53 PM PST 24
Finished Jan 21 03:08:18 PM PST 24
Peak memory 643248 kb
Host smart-a39de0cb-bea4-4ab2-b99a-b564b9aeb59c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1717307671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.1717307671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.353172839
Short name T940
Test name
Test status
Simulation time 150426662838 ps
CPU time 4046.29 seconds
Started Jan 21 02:18:28 PM PST 24
Finished Jan 21 03:25:55 PM PST 24
Peak memory 564568 kb
Host smart-c885f0c6-8501-44f0-98e2-5f684179bd7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=353172839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.353172839 +enable_masking=0 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/19.kmac_alert_test.4109062101
Short name T991
Test name
Test status
Simulation time 17434092 ps
CPU time 0.81 seconds
Started Jan 21 02:23:21 PM PST 24
Finished Jan 21 02:23:23 PM PST 24
Peak memory 207240 kb
Host smart-58abd2b8-7efc-49b3-b9ff-983f819807f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109062101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4109062101 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest


Test location /workspace/coverage/default/19.kmac_app.3417799803
Short name T382
Test name
Test status
Simulation time 38922764812 ps
CPU time 185.54 seconds
Started Jan 21 02:46:08 PM PST 24
Finished Jan 21 02:49:22 PM PST 24
Peak memory 235088 kb
Host smart-b2ae9748-7312-4dae-aa1d-7ec5f3610f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417799803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3417799803 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest


Test location /workspace/coverage/default/19.kmac_burst_write.3282813395
Short name T879
Test name
Test status
Simulation time 3496161551 ps
CPU time 171.52 seconds
Started Jan 21 01:54:15 PM PST 24
Finished Jan 21 01:57:08 PM PST 24
Peak memory 224808 kb
Host smart-cef3cd53-8d58-4eab-8687-9ccde597beeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282813395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3282813395 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest


Test location /workspace/coverage/default/19.kmac_edn_timeout_error.1200804216
Short name T1138
Test name
Test status
Simulation time 366216093 ps
CPU time 25.71 seconds
Started Jan 21 02:43:21 PM PST 24
Finished Jan 21 02:43:47 PM PST 24
Peak memory 223672 kb
Host smart-2a5302e7-ce00-43e7-a9f7-5d571e02002f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200804216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1200804216 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3263688930
Short name T480
Test name
Test status
Simulation time 1494553692 ps
CPU time 8.63 seconds
Started Jan 21 01:54:44 PM PST 24
Finished Jan 21 01:54:56 PM PST 24
Peak memory 219172 kb
Host smart-d4f3d2d8-7953-406c-909e-71d07ad42ebd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3263688930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3263688930 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/19.kmac_entropy_refresh.3805853511
Short name T493
Test name
Test status
Simulation time 3961960565 ps
CPU time 61.71 seconds
Started Jan 21 02:39:56 PM PST 24
Finished Jan 21 02:40:59 PM PST 24
Peak memory 225000 kb
Host smart-8d1c1904-8db0-4832-b3c3-8b037820d65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805853511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3805853511 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/19.kmac_error.1467629763
Short name T332
Test name
Test status
Simulation time 38974012772 ps
CPU time 213.29 seconds
Started Jan 21 01:54:47 PM PST 24
Finished Jan 21 01:58:24 PM PST 24
Peak memory 256372 kb
Host smart-29dcec65-d47b-4d1e-823d-fd6eb7b88632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467629763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1467629763 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest


Test location /workspace/coverage/default/19.kmac_key_error.1631761917
Short name T562
Test name
Test status
Simulation time 5725869261 ps
CPU time 5.72 seconds
Started Jan 21 01:54:47 PM PST 24
Finished Jan 21 01:54:57 PM PST 24
Peak memory 207456 kb
Host smart-9aec10e5-9a1f-49be-be87-ed23f7046908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631761917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1631761917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest


Test location /workspace/coverage/default/19.kmac_lc_escalation.2377369671
Short name T980
Test name
Test status
Simulation time 45749023 ps
CPU time 1.28 seconds
Started Jan 21 01:54:45 PM PST 24
Finished Jan 21 01:54:48 PM PST 24
Peak memory 215884 kb
Host smart-e420e2a2-f77e-482b-b4ab-11ab92ff0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377369671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2377369671 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest


Test location /workspace/coverage/default/19.kmac_long_msg_and_output.2752484409
Short name T535
Test name
Test status
Simulation time 43167870094 ps
CPU time 1330.88 seconds
Started Jan 21 01:54:10 PM PST 24
Finished Jan 21 02:16:22 PM PST 24
Peak memory 336312 kb
Host smart-d3b8a03a-1ba2-4875-b083-b74a798f6311
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752484409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.2752484409 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/19.kmac_sideload.4146160323
Short name T608
Test name
Test status
Simulation time 12509485393 ps
CPU time 146.91 seconds
Started Jan 21 01:54:17 PM PST 24
Finished Jan 21 01:56:44 PM PST 24
Peak memory 233104 kb
Host smart-45007f6a-ddb6-467b-b350-e9564d8d102f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146160323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.4146160323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest


Test location /workspace/coverage/default/19.kmac_smoke.1734701866
Short name T1013
Test name
Test status
Simulation time 11493340326 ps
CPU time 57.8 seconds
Started Jan 21 02:18:37 PM PST 24
Finished Jan 21 02:19:39 PM PST 24
Peak memory 219260 kb
Host smart-9c80126e-f5fb-4f1d-9d57-438b69b45d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734701866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1734701866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest


Test location /workspace/coverage/default/19.kmac_stress_all.728560515
Short name T937
Test name
Test status
Simulation time 16610944690 ps
CPU time 378.43 seconds
Started Jan 21 01:54:45 PM PST 24
Finished Jan 21 02:01:06 PM PST 24
Peak memory 268352 kb
Host smart-6ed6007e-dc1e-4a95-b646-587d14c9e287
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=728560515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.728560515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest


Test location /workspace/coverage/default/19.kmac_stress_all_with_rand_reset.131430157
Short name T1116
Test name
Test status
Simulation time 394395416717 ps
CPU time 1918.99 seconds
Started Jan 21 02:18:41 PM PST 24
Finished Jan 21 02:50:42 PM PST 24
Peak memory 369632 kb
Host smart-ea101ec5-09bf-4e7a-a368-fd05e1aea6bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131430157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.131430157 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.802215113
Short name T317
Test name
Test status
Simulation time 647061279 ps
CPU time 4.17 seconds
Started Jan 21 03:59:31 PM PST 24
Finished Jan 21 03:59:37 PM PST 24
Peak memory 208464 kb
Host smart-36d43352-58ae-41d9-82f8-885c429760f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802215113 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.802215113 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.123513385
Short name T1102
Test name
Test status
Simulation time 180590328 ps
CPU time 4.86 seconds
Started Jan 21 02:37:07 PM PST 24
Finished Jan 21 02:37:13 PM PST 24
Peak memory 216680 kb
Host smart-33aab9a5-3dc9-47e2-8485-4928045930ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123513385 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.kmac_test_vectors_kmac_xof.123513385 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.3046365950
Short name T241
Test name
Test status
Simulation time 487357720909 ps
CPU time 1873.72 seconds
Started Jan 21 01:54:16 PM PST 24
Finished Jan 21 02:25:31 PM PST 24
Peak memory 378288 kb
Host smart-0eebf714-cbf0-483b-aa4f-73d0a6702711
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3046365950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3046365950 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.852070585
Short name T1049
Test name
Test status
Simulation time 18888651336 ps
CPU time 1509.22 seconds
Started Jan 21 02:23:22 PM PST 24
Finished Jan 21 02:48:37 PM PST 24
Peak memory 373976 kb
Host smart-f31eaab6-6309-4257-b5eb-c1df977ab659
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=852070585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.852070585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.1168608140
Short name T1064
Test name
Test status
Simulation time 143499271477 ps
CPU time 1371.45 seconds
Started Jan 21 01:54:18 PM PST 24
Finished Jan 21 02:17:10 PM PST 24
Peak memory 329268 kb
Host smart-0ee079e9-ce0a-4907-aef8-08a7defb884f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1168608140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.1168608140 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.4289209668
Short name T337
Test name
Test status
Simulation time 136084411624 ps
CPU time 873.05 seconds
Started Jan 21 01:54:19 PM PST 24
Finished Jan 21 02:08:53 PM PST 24
Peak memory 294148 kb
Host smart-e9718875-da32-4274-a05f-7d0e867ae168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4289209668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.4289209668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.3322802736
Short name T1053
Test name
Test status
Simulation time 1625189117979 ps
CPU time 5681.15 seconds
Started Jan 21 01:54:17 PM PST 24
Finished Jan 21 03:28:59 PM PST 24
Peak memory 663072 kb
Host smart-30810e63-8afe-4325-af18-324b85de5260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3322802736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3322802736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.3652147958
Short name T156
Test name
Test status
Simulation time 152709596275 ps
CPU time 3877 seconds
Started Jan 21 01:54:25 PM PST 24
Finished Jan 21 02:59:03 PM PST 24
Peak memory 550616 kb
Host smart-654c6bff-4908-4f96-ac13-974d19a1fbd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3652147958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.3652147958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/2.kmac_alert_test.1061226184
Short name T590
Test name
Test status
Simulation time 21538324 ps
CPU time 0.87 seconds
Started Jan 21 01:47:07 PM PST 24
Finished Jan 21 01:47:11 PM PST 24
Peak memory 207272 kb
Host smart-f943e9f1-3d29-4468-b14e-4a0d50b9bf5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061226184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1061226184 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest


Test location /workspace/coverage/default/2.kmac_app.3496322209
Short name T280
Test name
Test status
Simulation time 902196279 ps
CPU time 9.3 seconds
Started Jan 21 01:47:04 PM PST 24
Finished Jan 21 01:47:19 PM PST 24
Peak memory 223788 kb
Host smart-ba9a1833-d3c5-4755-a04a-ec2c4e29aeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496322209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3496322209 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest


Test location /workspace/coverage/default/2.kmac_app_with_partial_data.3237933479
Short name T868
Test name
Test status
Simulation time 10423422170 ps
CPU time 58.95 seconds
Started Jan 21 02:35:00 PM PST 24
Finished Jan 21 02:36:01 PM PST 24
Peak memory 224128 kb
Host smart-dc640e01-6d44-4929-a8c6-98fc257a5b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237933479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3237933479 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/2.kmac_burst_write.886216906
Short name T232
Test name
Test status
Simulation time 14267163172 ps
CPU time 606.42 seconds
Started Jan 21 01:46:57 PM PST 24
Finished Jan 21 01:57:05 PM PST 24
Peak memory 232404 kb
Host smart-6c79e212-41db-4054-b921-28d4c2eb010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886216906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.886216906 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest


Test location /workspace/coverage/default/2.kmac_edn_timeout_error.3053678583
Short name T533
Test name
Test status
Simulation time 1495944024 ps
CPU time 19.85 seconds
Started Jan 21 01:47:07 PM PST 24
Finished Jan 21 01:47:30 PM PST 24
Peak memory 223596 kb
Host smart-a9987902-604c-4c9d-910b-7af359202b3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3053678583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3053678583 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1391083135
Short name T357
Test name
Test status
Simulation time 155905407 ps
CPU time 5.89 seconds
Started Jan 21 01:47:04 PM PST 24
Finished Jan 21 01:47:16 PM PST 24
Peak memory 220624 kb
Host smart-a4908830-ad1d-4814-844f-7ccfb87d168f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1391083135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1391083135 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/2.kmac_entropy_ready_error.773243425
Short name T1106
Test name
Test status
Simulation time 8239083677 ps
CPU time 20.52 seconds
Started Jan 21 01:47:04 PM PST 24
Finished Jan 21 01:47:30 PM PST 24
Peak memory 218004 kb
Host smart-e288fb92-607d-4446-ad53-c2d285b4e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773243425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.773243425 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/2.kmac_entropy_refresh.1599782921
Short name T440
Test name
Test status
Simulation time 16028518209 ps
CPU time 247.17 seconds
Started Jan 21 01:47:01 PM PST 24
Finished Jan 21 01:51:10 PM PST 24
Peak memory 239776 kb
Host smart-5b5ad277-ac96-45cc-8152-0a8e01d1c70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599782921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1599782921 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/2.kmac_error.218681573
Short name T679
Test name
Test status
Simulation time 26209798728 ps
CPU time 163.98 seconds
Started Jan 21 01:47:03 PM PST 24
Finished Jan 21 01:49:52 PM PST 24
Peak memory 247608 kb
Host smart-a3df4342-4af2-4f0f-a90e-f3023beb1f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218681573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.218681573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest


Test location /workspace/coverage/default/2.kmac_lc_escalation.3620750420
Short name T989
Test name
Test status
Simulation time 251462989 ps
CPU time 1.23 seconds
Started Jan 21 01:47:06 PM PST 24
Finished Jan 21 01:47:11 PM PST 24
Peak memory 220248 kb
Host smart-9e5f38c0-f6ca-4c61-b583-95cc398d31a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620750420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3620750420 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest


Test location /workspace/coverage/default/2.kmac_long_msg_and_output.1767717256
Short name T351
Test name
Test status
Simulation time 16811514514 ps
CPU time 1479.88 seconds
Started Jan 21 01:46:51 PM PST 24
Finished Jan 21 02:11:34 PM PST 24
Peak memory 373676 kb
Host smart-b7d12570-3223-4620-8d18-34573fd406b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767717256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.1767717256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/2.kmac_sec_cm.1026995871
Short name T69
Test name
Test status
Simulation time 4776870027 ps
CPU time 59.55 seconds
Started Jan 21 01:47:03 PM PST 24
Finished Jan 21 01:48:07 PM PST 24
Peak memory 261848 kb
Host smart-bb237c3d-11f1-43bc-bb79-4d662ccf2cfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026995871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1026995871 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest


Test location /workspace/coverage/default/2.kmac_sideload.1760571811
Short name T685
Test name
Test status
Simulation time 3653399643 ps
CPU time 277.29 seconds
Started Jan 21 01:46:49 PM PST 24
Finished Jan 21 01:51:31 PM PST 24
Peak memory 243180 kb
Host smart-33297613-27bb-42f5-a83c-9f8c79a278cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760571811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1760571811 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest


Test location /workspace/coverage/default/2.kmac_smoke.666243650
Short name T630
Test name
Test status
Simulation time 1048895715 ps
CPU time 55.17 seconds
Started Jan 21 01:46:57 PM PST 24
Finished Jan 21 01:47:54 PM PST 24
Peak memory 218464 kb
Host smart-1a9b2f3f-9e58-4b37-ba81-cc5a721e9d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666243650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.666243650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest


Test location /workspace/coverage/default/2.kmac_stress_all.4274288629
Short name T404
Test name
Test status
Simulation time 17969357975 ps
CPU time 1511.23 seconds
Started Jan 21 01:47:05 PM PST 24
Finished Jan 21 02:12:21 PM PST 24
Peak memory 421872 kb
Host smart-be521517-71e0-4cd5-aaec-9af2c2ff058a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4274288629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.4274288629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest


Test location /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.2369561343
Short name T959
Test name
Test status
Simulation time 84332933561 ps
CPU time 1852.26 seconds
Started Jan 21 01:47:03 PM PST 24
Finished Jan 21 02:18:02 PM PST 24
Peak memory 369264 kb
Host smart-89e96005-c5c5-46ce-b542-7eae77b1e23a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369561343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.2369561343 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.2444376813
Short name T933
Test name
Test status
Simulation time 1023538936 ps
CPU time 5.32 seconds
Started Jan 21 01:47:02 PM PST 24
Finished Jan 21 01:47:08 PM PST 24
Peak memory 208980 kb
Host smart-5b544a55-58e4-486c-9bc2-ddbf2eafe475
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444376813 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.2444376813 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.274538117
Short name T197
Test name
Test status
Simulation time 214479066 ps
CPU time 4.72 seconds
Started Jan 21 01:47:01 PM PST 24
Finished Jan 21 01:47:07 PM PST 24
Peak memory 208404 kb
Host smart-6bc37f4c-045b-44ae-878d-fd184ab08947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274538117 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.274538117 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.1866887008
Short name T1023
Test name
Test status
Simulation time 18735813629 ps
CPU time 1596.38 seconds
Started Jan 21 01:46:51 PM PST 24
Finished Jan 21 02:13:30 PM PST 24
Peak memory 378560 kb
Host smart-eb242526-87ac-4123-8dea-fcb046b8b1b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1866887008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1866887008 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.1772540799
Short name T1046
Test name
Test status
Simulation time 127669269791 ps
CPU time 1723.74 seconds
Started Jan 21 01:46:51 PM PST 24
Finished Jan 21 02:15:38 PM PST 24
Peak memory 374464 kb
Host smart-d91e0a26-dde7-435a-a8d3-b48f286bfdec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1772540799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1772540799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2639836504
Short name T928
Test name
Test status
Simulation time 97784699953 ps
CPU time 1149.52 seconds
Started Jan 21 01:46:57 PM PST 24
Finished Jan 21 02:06:08 PM PST 24
Peak memory 335752 kb
Host smart-19406dd1-afb9-4682-ac88-ac2bb41471fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2639836504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2639836504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1302016481
Short name T1034
Test name
Test status
Simulation time 37611645814 ps
CPU time 762.02 seconds
Started Jan 21 01:46:51 PM PST 24
Finished Jan 21 01:59:36 PM PST 24
Peak memory 292120 kb
Host smart-67558bea-5848-440a-bb2b-73a869d9d64b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1302016481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1302016481 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.910808166
Short name T302
Test name
Test status
Simulation time 204938786812 ps
CPU time 3987.31 seconds
Started Jan 21 01:46:55 PM PST 24
Finished Jan 21 02:53:26 PM PST 24
Peak memory 616396 kb
Host smart-030ba610-58ea-4635-9a72-b7ec671653b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=910808166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.910808166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.3216784679
Short name T852
Test name
Test status
Simulation time 299956725885 ps
CPU time 4108.45 seconds
Started Jan 21 01:47:02 PM PST 24
Finished Jan 21 02:55:32 PM PST 24
Peak memory 553112 kb
Host smart-09888044-b41b-4d87-9531-44ffc77f00e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3216784679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3216784679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/20.kmac_alert_test.3292767431
Short name T995
Test name
Test status
Simulation time 47575153 ps
CPU time 0.82 seconds
Started Jan 21 01:55:36 PM PST 24
Finished Jan 21 01:55:37 PM PST 24
Peak memory 207304 kb
Host smart-da78fed2-0c3d-4adf-b946-f5c8031ed710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292767431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3292767431 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest


Test location /workspace/coverage/default/20.kmac_app.1340293487
Short name T30
Test name
Test status
Simulation time 4323860407 ps
CPU time 252.68 seconds
Started Jan 21 01:55:00 PM PST 24
Finished Jan 21 01:59:19 PM PST 24
Peak memory 245044 kb
Host smart-5bab4ae6-882c-4532-8ef5-c594b19c63bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340293487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1340293487 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest


Test location /workspace/coverage/default/20.kmac_burst_write.3357118821
Short name T1133
Test name
Test status
Simulation time 165673411688 ps
CPU time 859.15 seconds
Started Jan 21 01:54:50 PM PST 24
Finished Jan 21 02:09:11 PM PST 24
Peak memory 232104 kb
Host smart-c5d6a7be-b30e-499f-a579-4a630a558a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357118821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3357118821 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest


Test location /workspace/coverage/default/20.kmac_entropy_refresh.4085754345
Short name T370
Test name
Test status
Simulation time 21891702196 ps
CPU time 216.56 seconds
Started Jan 21 01:55:01 PM PST 24
Finished Jan 21 01:58:45 PM PST 24
Peak memory 243012 kb
Host smart-629b9106-e70c-4cf3-86e4-7b6083d82e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085754345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4085754345 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/20.kmac_error.2257064996
Short name T86
Test name
Test status
Simulation time 2463362109 ps
CPU time 89.16 seconds
Started Jan 21 02:17:33 PM PST 24
Finished Jan 21 02:19:08 PM PST 24
Peak memory 237332 kb
Host smart-a11945ed-79cc-4332-9f75-ecad0f047ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257064996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2257064996 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest


Test location /workspace/coverage/default/20.kmac_key_error.3646619190
Short name T834
Test name
Test status
Simulation time 1547784387 ps
CPU time 2.98 seconds
Started Jan 21 01:55:09 PM PST 24
Finished Jan 21 01:55:15 PM PST 24
Peak memory 207456 kb
Host smart-6c36a5ae-6631-479c-a9fd-fb22f0ed0725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646619190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3646619190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest


Test location /workspace/coverage/default/20.kmac_long_msg_and_output.409943992
Short name T1026
Test name
Test status
Simulation time 14312007650 ps
CPU time 414.88 seconds
Started Jan 21 01:54:51 PM PST 24
Finished Jan 21 02:01:47 PM PST 24
Peak memory 255892 kb
Host smart-ffb31cae-29cf-42f2-b698-6ee71a5981f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409943992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an
d_output.409943992 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/20.kmac_sideload.2082186339
Short name T628
Test name
Test status
Simulation time 13555118576 ps
CPU time 357.25 seconds
Started Jan 21 01:54:51 PM PST 24
Finished Jan 21 02:00:49 PM PST 24
Peak memory 246944 kb
Host smart-89e3dd04-5806-45b9-bb7c-8ae757d0e140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082186339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2082186339 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest


Test location /workspace/coverage/default/20.kmac_smoke.1899612269
Short name T266
Test name
Test status
Simulation time 3803076058 ps
CPU time 64.16 seconds
Started Jan 21 01:54:51 PM PST 24
Finished Jan 21 01:55:57 PM PST 24
Peak memory 219264 kb
Host smart-3d882224-9087-4f64-8010-0903dcfce550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899612269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1899612269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest


Test location /workspace/coverage/default/20.kmac_stress_all.2561859167
Short name T993
Test name
Test status
Simulation time 382708871785 ps
CPU time 2238.66 seconds
Started Jan 21 01:55:24 PM PST 24
Finished Jan 21 02:32:47 PM PST 24
Peak memory 447056 kb
Host smart-2135eff8-2552-46e1-8342-c8d156608b9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2561859167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2561859167 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest


Test location /workspace/coverage/default/20.kmac_stress_all_with_rand_reset.1370507953
Short name T1097
Test name
Test status
Simulation time 27797577055 ps
CPU time 673.41 seconds
Started Jan 21 01:55:33 PM PST 24
Finished Jan 21 02:06:48 PM PST 24
Peak memory 298012 kb
Host smart-74a293b7-65ea-40af-bd26-c647765c34f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370507953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all_with_rand_reset.1370507953 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.3176769178
Short name T407
Test name
Test status
Simulation time 301268031 ps
CPU time 4.26 seconds
Started Jan 21 01:55:00 PM PST 24
Finished Jan 21 01:55:10 PM PST 24
Peak memory 216648 kb
Host smart-29344c1b-23cc-4531-b27c-4a92f5f12dd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176769178 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.3176769178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.3529894628
Short name T543
Test name
Test status
Simulation time 185889515 ps
CPU time 4.37 seconds
Started Jan 21 01:54:58 PM PST 24
Finished Jan 21 01:55:03 PM PST 24
Peak memory 208492 kb
Host smart-9984bba7-19df-43d4-a99b-fc36be006bfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529894628 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.3529894628 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.3111784828
Short name T675
Test name
Test status
Simulation time 388439768045 ps
CPU time 2076.55 seconds
Started Jan 21 01:54:58 PM PST 24
Finished Jan 21 02:29:36 PM PST 24
Peak memory 391476 kb
Host smart-efc3e5c9-519a-497e-a8b2-f2fdc52f7bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3111784828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3111784828 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.2773776983
Short name T20
Test name
Test status
Simulation time 18298543570 ps
CPU time 1529.16 seconds
Started Jan 21 02:35:37 PM PST 24
Finished Jan 21 03:01:07 PM PST 24
Peak memory 370132 kb
Host smart-682a8e75-fad4-47c2-bd37-cd941d1106a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2773776983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2773776983 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.2241254580
Short name T262
Test name
Test status
Simulation time 277904309805 ps
CPU time 1390.63 seconds
Started Jan 21 01:55:01 PM PST 24
Finished Jan 21 02:18:19 PM PST 24
Peak memory 331120 kb
Host smart-5c169366-a1e3-4152-aad6-0ff552853407
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2241254580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.2241254580 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.1971662208
Short name T1067
Test name
Test status
Simulation time 9504992796 ps
CPU time 792.7 seconds
Started Jan 21 01:55:00 PM PST 24
Finished Jan 21 02:08:19 PM PST 24
Peak memory 290832 kb
Host smart-7bb84361-6c42-407a-97d9-fa04198c0d2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1971662208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1971662208 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.2091550178
Short name T961
Test name
Test status
Simulation time 212061336508 ps
CPU time 3934.64 seconds
Started Jan 21 01:55:00 PM PST 24
Finished Jan 21 03:00:43 PM PST 24
Peak memory 650332 kb
Host smart-00050dc5-4c38-41bf-a9fe-5dbdae3e36ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2091550178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.2091550178 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.4180910445
Short name T792
Test name
Test status
Simulation time 43884127839 ps
CPU time 3434.91 seconds
Started Jan 21 01:55:00 PM PST 24
Finished Jan 21 02:52:21 PM PST 24
Peak memory 564988 kb
Host smart-6389b135-2bdf-4a95-bcd9-3b9862fbf776
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4180910445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.4180910445 +enable_masking=0 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/21.kmac_alert_test.1659343030
Short name T385
Test name
Test status
Simulation time 37161321 ps
CPU time 0.8 seconds
Started Jan 21 02:04:18 PM PST 24
Finished Jan 21 02:04:19 PM PST 24
Peak memory 207288 kb
Host smart-7349d152-ac47-44ba-bc61-2ab64ba8dca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659343030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1659343030 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest


Test location /workspace/coverage/default/21.kmac_app.2969915479
Short name T906
Test name
Test status
Simulation time 12795032486 ps
CPU time 153.98 seconds
Started Jan 21 01:56:00 PM PST 24
Finished Jan 21 01:58:35 PM PST 24
Peak memory 236324 kb
Host smart-f096545e-0222-4e55-8925-43e1042700df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969915479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2969915479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest


Test location /workspace/coverage/default/21.kmac_burst_write.1197541917
Short name T778
Test name
Test status
Simulation time 52755778505 ps
CPU time 269.7 seconds
Started Jan 21 01:55:43 PM PST 24
Finished Jan 21 02:00:14 PM PST 24
Peak memory 224508 kb
Host smart-11224e36-d2eb-478b-9fba-11c7bb354cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197541917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1197541917 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest


Test location /workspace/coverage/default/21.kmac_entropy_refresh.796877496
Short name T912
Test name
Test status
Simulation time 20286957207 ps
CPU time 136.43 seconds
Started Jan 21 01:55:59 PM PST 24
Finished Jan 21 01:58:17 PM PST 24
Peak memory 233532 kb
Host smart-866babcb-fd36-4bc7-92b1-13e12851f625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796877496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.796877496 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/21.kmac_error.1633231201
Short name T920
Test name
Test status
Simulation time 19847928251 ps
CPU time 102.21 seconds
Started Jan 21 01:55:59 PM PST 24
Finished Jan 21 01:57:42 PM PST 24
Peak memory 236936 kb
Host smart-78b66ccd-55c0-4c04-b8f8-086d7589df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633231201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1633231201 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest


Test location /workspace/coverage/default/21.kmac_key_error.3832528878
Short name T927
Test name
Test status
Simulation time 654685950 ps
CPU time 2.29 seconds
Started Jan 21 01:56:06 PM PST 24
Finished Jan 21 01:56:09 PM PST 24
Peak memory 207836 kb
Host smart-e9beb1af-27c0-4b59-9973-74c96a3229d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832528878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3832528878 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest


Test location /workspace/coverage/default/21.kmac_lc_escalation.2927575376
Short name T400
Test name
Test status
Simulation time 40074431 ps
CPU time 1.16 seconds
Started Jan 21 02:42:08 PM PST 24
Finished Jan 21 02:42:10 PM PST 24
Peak memory 207588 kb
Host smart-31f74df8-b3e3-47b1-a696-67beb8e7d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927575376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2927575376 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest


Test location /workspace/coverage/default/21.kmac_long_msg_and_output.3049003915
Short name T584
Test name
Test status
Simulation time 71173694685 ps
CPU time 1418.6 seconds
Started Jan 21 01:55:41 PM PST 24
Finished Jan 21 02:19:21 PM PST 24
Peak memory 365396 kb
Host smart-9affab3c-090d-43b0-9661-443288a6efd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049003915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.3049003915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/21.kmac_sideload.2408150210
Short name T755
Test name
Test status
Simulation time 10181246397 ps
CPU time 147.19 seconds
Started Jan 21 01:55:44 PM PST 24
Finished Jan 21 01:58:12 PM PST 24
Peak memory 231020 kb
Host smart-d423e007-9af5-482d-923d-ed8a8bc636eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408150210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2408150210 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest


Test location /workspace/coverage/default/21.kmac_smoke.3012729341
Short name T414
Test name
Test status
Simulation time 349422237 ps
CPU time 6.74 seconds
Started Jan 21 02:38:33 PM PST 24
Finished Jan 21 02:38:40 PM PST 24
Peak memory 217208 kb
Host smart-77f2db48-5d05-4161-accd-e1f33cb4cf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012729341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3012729341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest


Test location /workspace/coverage/default/21.kmac_stress_all_with_rand_reset.1698790705
Short name T358
Test name
Test status
Simulation time 209595940397 ps
CPU time 681.83 seconds
Started Jan 21 02:24:14 PM PST 24
Finished Jan 21 02:35:37 PM PST 24
Peak memory 269436 kb
Host smart-2f8c9fd9-39c2-4db9-b750-468bd7357599
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698790705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.1698790705 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3771958359
Short name T454
Test name
Test status
Simulation time 185731927 ps
CPU time 4.05 seconds
Started Jan 21 01:56:03 PM PST 24
Finished Jan 21 01:56:07 PM PST 24
Peak memory 208592 kb
Host smart-ef5078d6-ad7d-45a4-8794-d1dfec019ec2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771958359 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3771958359 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.224268238
Short name T513
Test name
Test status
Simulation time 173579280 ps
CPU time 4.48 seconds
Started Jan 21 01:55:57 PM PST 24
Finished Jan 21 01:56:02 PM PST 24
Peak memory 217136 kb
Host smart-6297a09e-f42f-421e-a95a-9d3187064a62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224268238 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.kmac_test_vectors_kmac_xof.224268238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.3361742768
Short name T919
Test name
Test status
Simulation time 65453173199 ps
CPU time 1860.29 seconds
Started Jan 21 01:55:42 PM PST 24
Finished Jan 21 02:26:44 PM PST 24
Peak memory 394980 kb
Host smart-4edd0ac5-8df6-44cf-9055-f18ef457efde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3361742768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3361742768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3513926508
Short name T958
Test name
Test status
Simulation time 64495911664 ps
CPU time 1840.49 seconds
Started Jan 21 02:26:04 PM PST 24
Finished Jan 21 02:56:46 PM PST 24
Peak memory 389308 kb
Host smart-f8423930-18e1-47af-86d2-a3f5373b2c33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3513926508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3513926508 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.2458378998
Short name T409
Test name
Test status
Simulation time 93253998130 ps
CPU time 1199.36 seconds
Started Jan 21 01:55:41 PM PST 24
Finished Jan 21 02:15:41 PM PST 24
Peak memory 341832 kb
Host smart-f4409396-6216-4ab4-8472-e5315fb1d66f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2458378998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2458378998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.3021967458
Short name T572
Test name
Test status
Simulation time 34901047141 ps
CPU time 934.85 seconds
Started Jan 21 01:56:02 PM PST 24
Finished Jan 21 02:11:38 PM PST 24
Peak memory 299480 kb
Host smart-bfd9bf59-a8c1-434c-966a-5bf03b87424d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3021967458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3021967458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.3935450837
Short name T504
Test name
Test status
Simulation time 175000175203 ps
CPU time 4910.38 seconds
Started Jan 21 01:56:01 PM PST 24
Finished Jan 21 03:17:53 PM PST 24
Peak memory 646888 kb
Host smart-11522b51-98b6-471a-9ff5-c0e169997c04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3935450837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3935450837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.3050768413
Short name T763
Test name
Test status
Simulation time 304755576678 ps
CPU time 4074.33 seconds
Started Jan 21 01:55:57 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 566028 kb
Host smart-8a7309d4-7847-478c-9cf7-8dce34c312a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3050768413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3050768413 +enable_masking=0 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/22.kmac_alert_test.1429523649
Short name T787
Test name
Test status
Simulation time 18006506 ps
CPU time 0.76 seconds
Started Jan 21 01:56:48 PM PST 24
Finished Jan 21 01:56:49 PM PST 24
Peak memory 207160 kb
Host smart-ab7f232a-0170-4d3c-abfe-65975e72166c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429523649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1429523649 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest


Test location /workspace/coverage/default/22.kmac_app.3235911725
Short name T283
Test name
Test status
Simulation time 12588191869 ps
CPU time 237.77 seconds
Started Jan 21 01:56:39 PM PST 24
Finished Jan 21 02:00:37 PM PST 24
Peak memory 239120 kb
Host smart-10e9ea0f-a9f3-4a4d-8f55-a4b61158c61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235911725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3235911725 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest


Test location /workspace/coverage/default/22.kmac_burst_write.2345622171
Short name T438
Test name
Test status
Simulation time 18989888920 ps
CPU time 403.74 seconds
Started Jan 21 01:56:06 PM PST 24
Finished Jan 21 02:02:50 PM PST 24
Peak memory 228456 kb
Host smart-f8dd6585-9af0-455f-8623-c9f1781a85c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345622171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2345622171 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest


Test location /workspace/coverage/default/22.kmac_entropy_refresh.1623215244
Short name T715
Test name
Test status
Simulation time 6382732323 ps
CPU time 106.09 seconds
Started Jan 21 01:56:47 PM PST 24
Finished Jan 21 01:58:34 PM PST 24
Peak memory 229684 kb
Host smart-cc0445eb-7c0d-4ea7-aa02-b9172d9dda3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623215244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1623215244 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/22.kmac_error.1708890747
Short name T490
Test name
Test status
Simulation time 45650576231 ps
CPU time 324.64 seconds
Started Jan 21 02:12:24 PM PST 24
Finished Jan 21 02:17:50 PM PST 24
Peak memory 254884 kb
Host smart-db6471b6-9961-4f3c-ae97-bb30f1c45917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708890747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1708890747 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest


Test location /workspace/coverage/default/22.kmac_key_error.1508675773
Short name T363
Test name
Test status
Simulation time 3514359435 ps
CPU time 5.1 seconds
Started Jan 21 01:56:47 PM PST 24
Finished Jan 21 01:56:53 PM PST 24
Peak memory 207592 kb
Host smart-70474f5a-c2fd-4e4d-84cb-8c489384cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508675773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1508675773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest


Test location /workspace/coverage/default/22.kmac_lc_escalation.3557557320
Short name T325
Test name
Test status
Simulation time 57414017 ps
CPU time 1.28 seconds
Started Jan 21 01:56:47 PM PST 24
Finished Jan 21 01:56:49 PM PST 24
Peak memory 215964 kb
Host smart-07cac986-cab0-41bf-acf9-3ef74f93aefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557557320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3557557320 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest


Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1399221663
Short name T689
Test name
Test status
Simulation time 1062477320222 ps
CPU time 2822.34 seconds
Started Jan 21 01:56:08 PM PST 24
Finished Jan 21 02:43:11 PM PST 24
Peak memory 465272 kb
Host smart-e768d116-9973-4b8b-8b21-25a8a3f52e68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399221663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1399221663 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/22.kmac_sideload.1250052269
Short name T1070
Test name
Test status
Simulation time 7347331442 ps
CPU time 137.75 seconds
Started Jan 21 01:56:07 PM PST 24
Finished Jan 21 01:58:26 PM PST 24
Peak memory 232208 kb
Host smart-a611a59e-c5e5-4124-af3c-685f91a0b1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250052269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1250052269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest


Test location /workspace/coverage/default/22.kmac_smoke.167096462
Short name T273
Test name
Test status
Simulation time 4029133982 ps
CPU time 41.81 seconds
Started Jan 21 01:56:06 PM PST 24
Finished Jan 21 01:56:49 PM PST 24
Peak memory 218964 kb
Host smart-86c61c0f-eec2-4eee-baa8-09fdf879ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167096462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.167096462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest


Test location /workspace/coverage/default/22.kmac_stress_all.1567095817
Short name T31
Test name
Test status
Simulation time 22259378553 ps
CPU time 646.66 seconds
Started Jan 21 01:56:48 PM PST 24
Finished Jan 21 02:07:35 PM PST 24
Peak memory 305824 kb
Host smart-3180cfc1-2b02-4869-ad5e-272a5f5612ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1567095817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1567095817 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest


Test location /workspace/coverage/default/22.kmac_stress_all_with_rand_reset.2605440913
Short name T647
Test name
Test status
Simulation time 113465206383 ps
CPU time 1404.03 seconds
Started Jan 21 01:56:47 PM PST 24
Finished Jan 21 02:20:11 PM PST 24
Peak memory 391476 kb
Host smart-4ae9b83c-1a82-4cdf-955a-1165752da00b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605440913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all_with_rand_reset.2605440913 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.2817135480
Short name T586
Test name
Test status
Simulation time 251453794 ps
CPU time 3.81 seconds
Started Jan 21 01:56:39 PM PST 24
Finished Jan 21 01:56:44 PM PST 24
Peak memory 208972 kb
Host smart-0844aa36-e61e-457a-914d-f30aabc1d3b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817135480 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.2817135480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1887645422
Short name T644
Test name
Test status
Simulation time 169534921 ps
CPU time 4.21 seconds
Started Jan 21 01:56:40 PM PST 24
Finished Jan 21 01:56:45 PM PST 24
Peak memory 216628 kb
Host smart-0fe9f853-15c8-4756-a6e8-33cc6ed0f107
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887645422 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1887645422 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.2785707524
Short name T181
Test name
Test status
Simulation time 240058500887 ps
CPU time 1749.97 seconds
Started Jan 21 01:56:06 PM PST 24
Finished Jan 21 02:25:16 PM PST 24
Peak memory 391780 kb
Host smart-d421b8ad-338a-438d-8aa2-684727dc1c4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2785707524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2785707524 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.4274415196
Short name T557
Test name
Test status
Simulation time 37543125770 ps
CPU time 1540.45 seconds
Started Jan 21 02:49:47 PM PST 24
Finished Jan 21 03:15:28 PM PST 24
Peak memory 386700 kb
Host smart-2d72ccca-8007-41fa-b4c0-06b834559d55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4274415196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.4274415196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.3686387807
Short name T422
Test name
Test status
Simulation time 46577806372 ps
CPU time 1227.82 seconds
Started Jan 21 01:56:22 PM PST 24
Finished Jan 21 02:16:51 PM PST 24
Peak memory 329660 kb
Host smart-993d6201-07be-4452-b5e7-fb3919f450ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3686387807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.3686387807 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.502912368
Short name T977
Test name
Test status
Simulation time 128116813834 ps
CPU time 944.65 seconds
Started Jan 21 01:56:23 PM PST 24
Finished Jan 21 02:12:09 PM PST 24
Peak memory 291176 kb
Host smart-dc1486cc-4020-49f6-b028-1e4ef2aaadbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=502912368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.502912368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.693196507
Short name T688
Test name
Test status
Simulation time 785540094564 ps
CPU time 4799.25 seconds
Started Jan 21 01:56:24 PM PST 24
Finished Jan 21 03:16:25 PM PST 24
Peak memory 655100 kb
Host smart-c72d3d5d-7c80-46b7-90c6-2696ab3f16a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=693196507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.693196507 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.3192934809
Short name T910
Test name
Test status
Simulation time 164814803193 ps
CPU time 3550.67 seconds
Started Jan 21 02:17:50 PM PST 24
Finished Jan 21 03:17:02 PM PST 24
Peak memory 552992 kb
Host smart-739ef41f-d0e8-4842-9a29-008c6d9664ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3192934809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3192934809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/23.kmac_alert_test.1038621885
Short name T229
Test name
Test status
Simulation time 31179755 ps
CPU time 0.92 seconds
Started Jan 21 01:57:53 PM PST 24
Finished Jan 21 01:58:02 PM PST 24
Peak memory 207336 kb
Host smart-9418cabf-3101-4535-93a5-4787c6527d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038621885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1038621885 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest


Test location /workspace/coverage/default/23.kmac_app.1983199113
Short name T188
Test name
Test status
Simulation time 5770023592 ps
CPU time 62.47 seconds
Started Jan 21 01:57:34 PM PST 24
Finished Jan 21 01:58:38 PM PST 24
Peak memory 225004 kb
Host smart-02aa14bd-7751-419a-8a7d-c7ccd1abd791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983199113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1983199113 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest


Test location /workspace/coverage/default/23.kmac_burst_write.320985535
Short name T724
Test name
Test status
Simulation time 118727584414 ps
CPU time 626.89 seconds
Started Jan 21 01:57:02 PM PST 24
Finished Jan 21 02:07:30 PM PST 24
Peak memory 230100 kb
Host smart-edaa3e16-b59a-46cf-8b3e-2d4ebc7dfb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320985535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.320985535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest


Test location /workspace/coverage/default/23.kmac_entropy_refresh.4138195691
Short name T905
Test name
Test status
Simulation time 17158150610 ps
CPU time 289.45 seconds
Started Jan 21 01:57:35 PM PST 24
Finished Jan 21 02:02:27 PM PST 24
Peak memory 242372 kb
Host smart-44768fbc-8dfe-40af-820e-820ee1270263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138195691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.4138195691 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/23.kmac_error.3238951793
Short name T463
Test name
Test status
Simulation time 5181512708 ps
CPU time 186.9 seconds
Started Jan 21 01:57:35 PM PST 24
Finished Jan 21 02:00:44 PM PST 24
Peak memory 241968 kb
Host smart-a731f812-d66c-4d68-9bbb-a6c171d7f8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238951793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3238951793 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest


Test location /workspace/coverage/default/23.kmac_key_error.1332592750
Short name T427
Test name
Test status
Simulation time 13861140749 ps
CPU time 4.89 seconds
Started Jan 21 01:57:34 PM PST 24
Finished Jan 21 01:57:40 PM PST 24
Peak memory 207476 kb
Host smart-0a359cae-5641-4868-a0ef-97d72df9611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332592750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1332592750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest


Test location /workspace/coverage/default/23.kmac_lc_escalation.2410765302
Short name T811
Test name
Test status
Simulation time 130936284 ps
CPU time 1.29 seconds
Started Jan 21 01:57:35 PM PST 24
Finished Jan 21 01:57:39 PM PST 24
Peak memory 215936 kb
Host smart-3a66c5f0-f96e-4a80-be76-46d555cf8fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410765302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2410765302 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest


Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1849055675
Short name T451
Test name
Test status
Simulation time 59821039413 ps
CPU time 1772.29 seconds
Started Jan 21 01:56:57 PM PST 24
Finished Jan 21 02:26:30 PM PST 24
Peak memory 389440 kb
Host smart-bb902e88-4f80-4256-ae5f-f458f875c5f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849055675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1849055675 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/23.kmac_sideload.191797908
Short name T260
Test name
Test status
Simulation time 11873570491 ps
CPU time 205.66 seconds
Started Jan 21 02:25:19 PM PST 24
Finished Jan 21 02:28:46 PM PST 24
Peak memory 239748 kb
Host smart-0b49edd2-ed17-477e-a1ad-cff31d9f877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191797908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.191797908 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest


Test location /workspace/coverage/default/23.kmac_smoke.2458589913
Short name T1069
Test name
Test status
Simulation time 173686257 ps
CPU time 1.59 seconds
Started Jan 21 01:56:54 PM PST 24
Finished Jan 21 01:56:57 PM PST 24
Peak memory 216164 kb
Host smart-a6964cb3-81d7-4172-8444-ea9dc8eb62cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458589913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2458589913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest


Test location /workspace/coverage/default/23.kmac_stress_all.1250738108
Short name T425
Test name
Test status
Simulation time 62167273557 ps
CPU time 1845.71 seconds
Started Jan 21 01:57:36 PM PST 24
Finished Jan 21 02:28:23 PM PST 24
Peak memory 408568 kb
Host smart-f30ba350-6e2c-412a-a42f-45aa3bdf2d7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1250738108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1250738108 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest


Test location /workspace/coverage/default/23.kmac_stress_all_with_rand_reset.2226452340
Short name T42
Test name
Test status
Simulation time 214920853854 ps
CPU time 1139.74 seconds
Started Jan 21 01:57:40 PM PST 24
Finished Jan 21 02:16:44 PM PST 24
Peak memory 322428 kb
Host smart-bb473571-bc6f-46f3-b8e8-4fdfe877ace7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226452340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.2226452340 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.4135894993
Short name T583
Test name
Test status
Simulation time 69086672 ps
CPU time 3.96 seconds
Started Jan 21 01:57:30 PM PST 24
Finished Jan 21 01:57:37 PM PST 24
Peak memory 217140 kb
Host smart-5d9885e1-e36c-4b8a-b6b1-ed3e17d9dfaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135894993 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.4135894993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.635926798
Short name T743
Test name
Test status
Simulation time 977470716 ps
CPU time 5.28 seconds
Started Jan 21 01:57:30 PM PST 24
Finished Jan 21 01:57:38 PM PST 24
Peak memory 208968 kb
Host smart-a944b4c3-d2de-4026-b2fa-1780c61b6991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635926798 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.kmac_test_vectors_kmac_xof.635926798 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.3961561227
Short name T670
Test name
Test status
Simulation time 40515129294 ps
CPU time 1586.46 seconds
Started Jan 21 02:42:04 PM PST 24
Finished Jan 21 03:08:31 PM PST 24
Peak memory 396172 kb
Host smart-105699e8-d90d-4aca-9a05-fa7de6216340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3961561227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.3961561227 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.667534679
Short name T892
Test name
Test status
Simulation time 74479764972 ps
CPU time 1550.73 seconds
Started Jan 21 01:57:14 PM PST 24
Finished Jan 21 02:23:05 PM PST 24
Peak memory 376556 kb
Host smart-e075aa95-25ad-46ab-bbe8-a340454d9e94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=667534679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.667534679 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2970553595
Short name T178
Test name
Test status
Simulation time 14143922990 ps
CPU time 1158.48 seconds
Started Jan 21 01:57:13 PM PST 24
Finished Jan 21 02:16:32 PM PST 24
Peak memory 333264 kb
Host smart-d268b8d7-bafe-47b2-b7e1-877ec86ea0a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2970553595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2970553595 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.4027540406
Short name T195
Test name
Test status
Simulation time 9917606440 ps
CPU time 795.77 seconds
Started Jan 21 02:26:18 PM PST 24
Finished Jan 21 02:39:35 PM PST 24
Peak memory 292852 kb
Host smart-b10be596-a86c-45cc-8abc-f0c3033d60af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4027540406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.4027540406 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.1496891240
Short name T406
Test name
Test status
Simulation time 104366109060 ps
CPU time 4229.21 seconds
Started Jan 21 01:57:23 PM PST 24
Finished Jan 21 03:07:54 PM PST 24
Peak memory 655864 kb
Host smart-aba4328e-6354-4d2e-84ef-665dcbdf4e6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1496891240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.1496891240 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.4016180571
Short name T213
Test name
Test status
Simulation time 615841098223 ps
CPU time 4148.42 seconds
Started Jan 21 02:19:35 PM PST 24
Finished Jan 21 03:28:44 PM PST 24
Peak memory 574944 kb
Host smart-5c8d1290-6247-47ce-8073-f69c858a86b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4016180571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.4016180571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/24.kmac_alert_test.3973952275
Short name T624
Test name
Test status
Simulation time 50032456 ps
CPU time 0.85 seconds
Started Jan 21 01:58:28 PM PST 24
Finished Jan 21 01:58:29 PM PST 24
Peak memory 207332 kb
Host smart-d1fbb09c-6bdc-4d86-a570-d4086773c6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973952275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3973952275 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest


Test location /workspace/coverage/default/24.kmac_app.2175041629
Short name T423
Test name
Test status
Simulation time 181903681 ps
CPU time 12.52 seconds
Started Jan 21 01:58:10 PM PST 24
Finished Jan 21 01:58:24 PM PST 24
Peak memory 222212 kb
Host smart-2d413887-1a2c-4d2f-8b1e-204a50af0f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175041629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2175041629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest


Test location /workspace/coverage/default/24.kmac_burst_write.3057048749
Short name T722
Test name
Test status
Simulation time 3560179236 ps
CPU time 285.11 seconds
Started Jan 21 01:57:54 PM PST 24
Finished Jan 21 02:02:46 PM PST 24
Peak memory 227072 kb
Host smart-cefe406a-530f-42a0-9c40-90b96184f621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057048749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3057048749 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest


Test location /workspace/coverage/default/24.kmac_entropy_refresh.3055661834
Short name T723
Test name
Test status
Simulation time 16329221009 ps
CPU time 172.5 seconds
Started Jan 21 01:58:10 PM PST 24
Finished Jan 21 02:01:05 PM PST 24
Peak memory 238712 kb
Host smart-e0eb9d2e-0fa9-4173-a3db-221104074f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055661834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3055661834 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/24.kmac_error.1243358338
Short name T944
Test name
Test status
Simulation time 3143500817 ps
CPU time 61.61 seconds
Started Jan 21 01:58:13 PM PST 24
Finished Jan 21 01:59:15 PM PST 24
Peak memory 233244 kb
Host smart-b06526e0-702a-464a-adbd-1bc07bdad827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243358338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1243358338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest


Test location /workspace/coverage/default/24.kmac_key_error.2166155809
Short name T1081
Test name
Test status
Simulation time 3256652126 ps
CPU time 4.95 seconds
Started Jan 21 02:32:53 PM PST 24
Finished Jan 21 02:33:00 PM PST 24
Peak memory 207640 kb
Host smart-50c18b1f-c111-4226-984e-9a03bc3cc7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166155809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2166155809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest


Test location /workspace/coverage/default/24.kmac_lc_escalation.3230595186
Short name T289
Test name
Test status
Simulation time 830287380 ps
CPU time 14.38 seconds
Started Jan 21 01:58:17 PM PST 24
Finished Jan 21 01:58:33 PM PST 24
Peak memory 222740 kb
Host smart-eb10b204-0cee-4f86-bfcf-3c7e2bf648b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230595186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3230595186 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest


Test location /workspace/coverage/default/24.kmac_long_msg_and_output.2603494957
Short name T1005
Test name
Test status
Simulation time 26578218596 ps
CPU time 2223.78 seconds
Started Jan 21 01:57:47 PM PST 24
Finished Jan 21 02:34:53 PM PST 24
Peak memory 462436 kb
Host smart-35723665-1792-46b1-915f-87911302ef6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603494957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.2603494957 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/24.kmac_sideload.1733381232
Short name T384
Test name
Test status
Simulation time 19511702796 ps
CPU time 239.24 seconds
Started Jan 21 01:57:54 PM PST 24
Finished Jan 21 02:02:00 PM PST 24
Peak memory 241180 kb
Host smart-5cf2f9a9-d9d2-40b2-bf7f-1435d30fc615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733381232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1733381232 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest


Test location /workspace/coverage/default/24.kmac_smoke.1993757068
Short name T806
Test name
Test status
Simulation time 466849929 ps
CPU time 10.43 seconds
Started Jan 21 01:57:47 PM PST 24
Finished Jan 21 01:57:59 PM PST 24
Peak memory 223624 kb
Host smart-847f5352-238e-4cee-bfb7-8d3a8b306fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993757068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1993757068 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest


Test location /workspace/coverage/default/24.kmac_stress_all.1788131998
Short name T971
Test name
Test status
Simulation time 3169338124 ps
CPU time 13.52 seconds
Started Jan 21 01:58:25 PM PST 24
Finished Jan 21 01:58:40 PM PST 24
Peak memory 223516 kb
Host smart-9480043f-a599-4095-95b9-d8fc648d2070
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1788131998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1788131998 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3715607974
Short name T655
Test name
Test status
Simulation time 64859116 ps
CPU time 3.71 seconds
Started Jan 21 02:14:28 PM PST 24
Finished Jan 21 02:14:33 PM PST 24
Peak memory 208612 kb
Host smart-3aaaa0bc-c953-4a02-b254-f9f2e3276ff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715607974 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3715607974 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.3282467692
Short name T234
Test name
Test status
Simulation time 963465415 ps
CPU time 4.7 seconds
Started Jan 21 01:58:11 PM PST 24
Finished Jan 21 01:58:17 PM PST 24
Peak memory 208400 kb
Host smart-ad72a326-a692-479d-81ca-c46b9d08ddc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282467692 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.3282467692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1569995273
Short name T1016
Test name
Test status
Simulation time 272235285654 ps
CPU time 1955.96 seconds
Started Jan 21 01:57:53 PM PST 24
Finished Jan 21 02:30:37 PM PST 24
Peak memory 394200 kb
Host smart-615beb0e-d8ce-40de-9ddb-091d5c2a3626
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1569995273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1569995273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.3553134576
Short name T760
Test name
Test status
Simulation time 385517807976 ps
CPU time 1943.73 seconds
Started Jan 21 01:58:03 PM PST 24
Finished Jan 21 02:30:29 PM PST 24
Peak memory 377992 kb
Host smart-e22d878f-21da-4a9e-beff-e71305e55ab5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3553134576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.3553134576 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.3636958376
Short name T529
Test name
Test status
Simulation time 14017122841 ps
CPU time 1138.83 seconds
Started Jan 21 01:58:04 PM PST 24
Finished Jan 21 02:17:04 PM PST 24
Peak memory 341400 kb
Host smart-a43c0e61-4723-48ef-9999-4eb6fb9560ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3636958376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.3636958376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.3986086631
Short name T650
Test name
Test status
Simulation time 9422889062 ps
CPU time 748.38 seconds
Started Jan 21 01:58:02 PM PST 24
Finished Jan 21 02:10:33 PM PST 24
Peak memory 291152 kb
Host smart-57be4a01-4d04-4db2-ae09-e4413f57d35e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3986086631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3986086631 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3024720435
Short name T1066
Test name
Test status
Simulation time 340173311183 ps
CPU time 4696.55 seconds
Started Jan 21 01:58:10 PM PST 24
Finished Jan 21 03:16:30 PM PST 24
Peak memory 638460 kb
Host smart-693321e6-ccd0-45bf-80ae-8138701f4db6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3024720435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3024720435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.905977391
Short name T1099
Test name
Test status
Simulation time 604903709313 ps
CPU time 3794.24 seconds
Started Jan 21 02:37:39 PM PST 24
Finished Jan 21 03:40:54 PM PST 24
Peak memory 560104 kb
Host smart-edd44f1e-1c79-4284-a3da-b2ce9c67b855
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=905977391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.905977391 +enable_masking=0 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/25.kmac_alert_test.1217310503
Short name T822
Test name
Test status
Simulation time 25909044 ps
CPU time 0.76 seconds
Started Jan 21 02:29:27 PM PST 24
Finished Jan 21 02:29:28 PM PST 24
Peak memory 207244 kb
Host smart-26e654d2-25bf-476c-bf8c-70a84a4f797c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217310503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1217310503 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest


Test location /workspace/coverage/default/25.kmac_app.2860478328
Short name T259
Test name
Test status
Simulation time 6096896526 ps
CPU time 100.81 seconds
Started Jan 21 01:58:54 PM PST 24
Finished Jan 21 02:00:35 PM PST 24
Peak memory 229356 kb
Host smart-3c670fba-71ef-46b9-ac2a-74c95646ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860478328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2860478328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest


Test location /workspace/coverage/default/25.kmac_burst_write.2204661683
Short name T374
Test name
Test status
Simulation time 72193601862 ps
CPU time 543.56 seconds
Started Jan 21 01:58:30 PM PST 24
Finished Jan 21 02:07:34 PM PST 24
Peak memory 229064 kb
Host smart-8c5311f3-efe6-4591-811a-483b5860f89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204661683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2204661683 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest


Test location /workspace/coverage/default/25.kmac_entropy_refresh.1540414580
Short name T436
Test name
Test status
Simulation time 119863492046 ps
CPU time 210.7 seconds
Started Jan 21 01:58:52 PM PST 24
Finished Jan 21 02:02:24 PM PST 24
Peak memory 235648 kb
Host smart-75c3fae6-90c6-4853-9933-e1c88886961e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540414580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1540414580 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/25.kmac_error.1454708968
Short name T36
Test name
Test status
Simulation time 4865442604 ps
CPU time 327.16 seconds
Started Jan 21 01:58:52 PM PST 24
Finished Jan 21 02:04:20 PM PST 24
Peak memory 256540 kb
Host smart-fbb37642-6c02-4be2-8f35-4bd8afb65618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454708968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1454708968 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest


Test location /workspace/coverage/default/25.kmac_key_error.1977889545
Short name T473
Test name
Test status
Simulation time 420221845 ps
CPU time 1.23 seconds
Started Jan 21 01:59:01 PM PST 24
Finished Jan 21 01:59:03 PM PST 24
Peak memory 207300 kb
Host smart-d965f5c9-ea6e-442e-a5c4-ae156e189c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977889545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1977889545 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest


Test location /workspace/coverage/default/25.kmac_lc_escalation.244728237
Short name T271
Test name
Test status
Simulation time 61984955 ps
CPU time 1.38 seconds
Started Jan 21 01:59:03 PM PST 24
Finished Jan 21 01:59:05 PM PST 24
Peak memory 215768 kb
Host smart-db61d05c-7727-4431-ae6d-26e1baa89c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244728237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.244728237 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/25.kmac_lc_escalation/latest


Test location /workspace/coverage/default/25.kmac_long_msg_and_output.2016513626
Short name T215
Test name
Test status
Simulation time 147784416688 ps
CPU time 2273.1 seconds
Started Jan 21 01:58:25 PM PST 24
Finished Jan 21 02:36:20 PM PST 24
Peak memory 414612 kb
Host smart-2a90a77f-8cbb-46f0-b52e-09f160e17167
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016513626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.2016513626 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/25.kmac_sideload.3576814888
Short name T231
Test name
Test status
Simulation time 3856469947 ps
CPU time 78.64 seconds
Started Jan 21 01:58:26 PM PST 24
Finished Jan 21 01:59:45 PM PST 24
Peak memory 225388 kb
Host smart-eb1f738c-9927-4d1b-9cba-1953bcab8de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576814888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3576814888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest


Test location /workspace/coverage/default/25.kmac_smoke.4204361030
Short name T457
Test name
Test status
Simulation time 1041152918 ps
CPU time 48.88 seconds
Started Jan 21 02:32:06 PM PST 24
Finished Jan 21 02:32:56 PM PST 24
Peak memory 218688 kb
Host smart-fa4bc83e-ca5d-4f31-b1d4-7268e8de0482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204361030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.4204361030 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest


Test location /workspace/coverage/default/25.kmac_stress_all.717341997
Short name T395
Test name
Test status
Simulation time 6014796433 ps
CPU time 358.29 seconds
Started Jan 21 01:59:01 PM PST 24
Finished Jan 21 02:05:00 PM PST 24
Peak memory 273328 kb
Host smart-5162f879-6091-4c82-98e1-5ebe7619b298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=717341997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.717341997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest


Test location /workspace/coverage/default/25.kmac_stress_all_with_rand_reset.850046713
Short name T751
Test name
Test status
Simulation time 15876783880 ps
CPU time 366.1 seconds
Started Jan 21 01:59:04 PM PST 24
Finished Jan 21 02:05:11 PM PST 24
Peak memory 266300 kb
Host smart-36e23071-1ad7-4dc6-a457-e5b6d6c89bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850046713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.850046713 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.1404650548
Short name T1030
Test name
Test status
Simulation time 659983092 ps
CPU time 4.9 seconds
Started Jan 21 03:20:52 PM PST 24
Finished Jan 21 03:21:03 PM PST 24
Peak memory 209020 kb
Host smart-8b1cdb5a-9861-44b3-8c5f-650446832169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404650548 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.1404650548 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.2825864376
Short name T888
Test name
Test status
Simulation time 168606484 ps
CPU time 4.08 seconds
Started Jan 21 01:58:53 PM PST 24
Finished Jan 21 01:58:58 PM PST 24
Peak memory 216900 kb
Host smart-56276313-4ccc-4051-a2f7-e6b08f3d5d3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825864376 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.2825864376 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.779866669
Short name T948
Test name
Test status
Simulation time 87871307355 ps
CPU time 1926.35 seconds
Started Jan 21 02:29:14 PM PST 24
Finished Jan 21 03:01:21 PM PST 24
Peak memory 392112 kb
Host smart-153fbcd8-d87d-48f3-8a38-44ccfa34e6a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=779866669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.779866669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.2577254478
Short name T247
Test name
Test status
Simulation time 178035676522 ps
CPU time 1747.64 seconds
Started Jan 21 01:58:34 PM PST 24
Finished Jan 21 02:27:43 PM PST 24
Peak memory 370316 kb
Host smart-0b965802-6ee3-477e-bf46-2d7d96e4a8a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2577254478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.2577254478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.2334608987
Short name T596
Test name
Test status
Simulation time 14418448172 ps
CPU time 1133.48 seconds
Started Jan 21 01:58:35 PM PST 24
Finished Jan 21 02:17:29 PM PST 24
Peak memory 335844 kb
Host smart-63d39460-d204-48f3-9c2b-f53146f55cf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2334608987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.2334608987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.3942279750
Short name T1101
Test name
Test status
Simulation time 9440632399 ps
CPU time 774.52 seconds
Started Jan 21 01:58:41 PM PST 24
Finished Jan 21 02:11:37 PM PST 24
Peak memory 293084 kb
Host smart-f499738a-96bc-4cb3-a4d7-d811bc478405
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3942279750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3942279750 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.1265700884
Short name T236
Test name
Test status
Simulation time 357265620038 ps
CPU time 5023.42 seconds
Started Jan 21 01:58:45 PM PST 24
Finished Jan 21 03:22:30 PM PST 24
Peak memory 668832 kb
Host smart-52671333-f45a-4a24-997a-88fa8bc6f4ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1265700884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.1265700884 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.3677760621
Short name T789
Test name
Test status
Simulation time 152806286667 ps
CPU time 3947.96 seconds
Started Jan 21 01:58:55 PM PST 24
Finished Jan 21 03:04:44 PM PST 24
Peak memory 559272 kb
Host smart-fc9c23a4-4ba4-4541-980c-fa652ad0ecf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3677760621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.3677760621 +enable_masking=0 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/26.kmac_alert_test.4206287652
Short name T312
Test name
Test status
Simulation time 49767023 ps
CPU time 0.78 seconds
Started Jan 21 01:59:42 PM PST 24
Finished Jan 21 01:59:44 PM PST 24
Peak memory 207328 kb
Host smart-c2ae0622-29c3-450e-b751-3c9d9e4bee37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206287652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.4206287652 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest


Test location /workspace/coverage/default/26.kmac_app.127048888
Short name T706
Test name
Test status
Simulation time 19812861728 ps
CPU time 174.89 seconds
Started Jan 21 03:46:44 PM PST 24
Finished Jan 21 03:49:41 PM PST 24
Peak memory 236592 kb
Host smart-c6967f7e-9592-4664-833b-dc80eab4c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127048888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.127048888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest


Test location /workspace/coverage/default/26.kmac_burst_write.3433478810
Short name T946
Test name
Test status
Simulation time 88250095394 ps
CPU time 395.25 seconds
Started Jan 21 01:59:15 PM PST 24
Finished Jan 21 02:05:51 PM PST 24
Peak memory 235644 kb
Host smart-f8b816ee-663e-45a8-b058-10a56f68852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433478810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3433478810 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest


Test location /workspace/coverage/default/26.kmac_entropy_refresh.3308507844
Short name T1065
Test name
Test status
Simulation time 17608309525 ps
CPU time 306.32 seconds
Started Jan 21 01:59:24 PM PST 24
Finished Jan 21 02:04:31 PM PST 24
Peak memory 243616 kb
Host smart-8d863d76-8118-42cf-b2f5-7cd96ad1109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308507844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3308507844 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/26.kmac_error.49105616
Short name T140
Test name
Test status
Simulation time 18015322864 ps
CPU time 260.2 seconds
Started Jan 21 01:59:23 PM PST 24
Finished Jan 21 02:03:44 PM PST 24
Peak memory 250372 kb
Host smart-54cea794-1bf0-4757-9e06-411882c353d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49105616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.49105616 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest


Test location /workspace/coverage/default/26.kmac_key_error.3558736752
Short name T686
Test name
Test status
Simulation time 30024412 ps
CPU time 0.85 seconds
Started Jan 21 02:18:00 PM PST 24
Finished Jan 21 02:18:02 PM PST 24
Peak memory 207300 kb
Host smart-36a18d8b-d6d4-4431-aa26-9f19453b654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558736752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3558736752 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest


Test location /workspace/coverage/default/26.kmac_lc_escalation.3827546907
Short name T219
Test name
Test status
Simulation time 74816624 ps
CPU time 1.2 seconds
Started Jan 21 01:59:31 PM PST 24
Finished Jan 21 01:59:33 PM PST 24
Peak memory 215776 kb
Host smart-34403849-7c4c-4819-bc89-28ede01a17cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827546907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3827546907 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest


Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3844198402
Short name T176
Test name
Test status
Simulation time 4135549827 ps
CPU time 169.82 seconds
Started Jan 21 02:20:15 PM PST 24
Finished Jan 21 02:23:14 PM PST 24
Peak memory 240136 kb
Host smart-14237e72-9796-4e07-9ea5-e2349ed9fb28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844198402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3844198402 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/26.kmac_sideload.3855878737
Short name T1149
Test name
Test status
Simulation time 19765068171 ps
CPU time 158.3 seconds
Started Jan 21 01:59:09 PM PST 24
Finished Jan 21 02:01:48 PM PST 24
Peak memory 234404 kb
Host smart-d6f77a53-a9e3-42d3-b058-3a9e6eb4b7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855878737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3855878737 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest


Test location /workspace/coverage/default/26.kmac_smoke.791839301
Short name T1050
Test name
Test status
Simulation time 1513991939 ps
CPU time 18.56 seconds
Started Jan 21 02:56:16 PM PST 24
Finished Jan 21 02:56:41 PM PST 24
Peak memory 223732 kb
Host smart-84975f54-5e4d-43dd-8aae-d1ae7d65d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791839301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.791839301 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest


Test location /workspace/coverage/default/26.kmac_stress_all.3099814781
Short name T136
Test name
Test status
Simulation time 17069077040 ps
CPU time 784.85 seconds
Started Jan 21 01:59:32 PM PST 24
Finished Jan 21 02:12:37 PM PST 24
Peak memory 347112 kb
Host smart-6bcb1827-60ee-47f3-b183-10c850e3aa3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3099814781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3099814781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest


Test location /workspace/coverage/default/26.kmac_stress_all_with_rand_reset.307514649
Short name T864
Test name
Test status
Simulation time 47142979820 ps
CPU time 1092.11 seconds
Started Jan 21 02:41:41 PM PST 24
Finished Jan 21 02:59:54 PM PST 24
Peak memory 353576 kb
Host smart-6346d013-2203-43d1-9fe2-436c559744b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307514649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.307514649 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.2361819015
Short name T872
Test name
Test status
Simulation time 1073453251 ps
CPU time 5.05 seconds
Started Jan 21 01:59:25 PM PST 24
Finished Jan 21 01:59:31 PM PST 24
Peak memory 208808 kb
Host smart-884c55aa-d69d-41b2-8926-f25c49ef24bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361819015 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.2361819015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1765963668
Short name T735
Test name
Test status
Simulation time 66495025 ps
CPU time 3.95 seconds
Started Jan 21 01:59:24 PM PST 24
Finished Jan 21 01:59:29 PM PST 24
Peak memory 216976 kb
Host smart-d803ddb9-01de-459e-aedd-728bbe2573c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765963668 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1765963668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.566900901
Short name T519
Test name
Test status
Simulation time 64671845560 ps
CPU time 1828.19 seconds
Started Jan 21 01:59:15 PM PST 24
Finished Jan 21 02:29:44 PM PST 24
Peak memory 375724 kb
Host smart-47746454-6f75-4244-b1cc-6a39d9635e33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=566900901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.566900901 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.504319380
Short name T997
Test name
Test status
Simulation time 62992275787 ps
CPU time 1517.67 seconds
Started Jan 21 01:59:14 PM PST 24
Finished Jan 21 02:24:33 PM PST 24
Peak memory 371280 kb
Host smart-cdbac9b5-7fa0-4135-a1dd-32aebbd3fed6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=504319380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.504319380 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.324637219
Short name T962
Test name
Test status
Simulation time 72911719455 ps
CPU time 1524.88 seconds
Started Jan 21 01:59:15 PM PST 24
Finished Jan 21 02:24:41 PM PST 24
Peak memory 344600 kb
Host smart-413135f6-57dc-4928-9071-80b0becc9245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=324637219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.324637219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3794609831
Short name T1040
Test name
Test status
Simulation time 67495729520 ps
CPU time 948.18 seconds
Started Jan 21 01:59:14 PM PST 24
Finished Jan 21 02:15:03 PM PST 24
Peak memory 292608 kb
Host smart-cacf0b59-154e-40c9-9718-49d44c37fef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3794609831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3794609831 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.1236031770
Short name T917
Test name
Test status
Simulation time 1070143586601 ps
CPU time 5049.81 seconds
Started Jan 21 01:59:14 PM PST 24
Finished Jan 21 03:23:25 PM PST 24
Peak memory 651152 kb
Host smart-1d36aea2-7d95-40dc-8536-5c7905cd27c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1236031770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.1236031770 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.435852185
Short name T898
Test name
Test status
Simulation time 143973079849 ps
CPU time 3944.4 seconds
Started Jan 21 01:59:21 PM PST 24
Finished Jan 21 03:05:07 PM PST 24
Peak memory 552288 kb
Host smart-b8ea56af-c868-4c0b-8e01-4da6a59fdada
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=435852185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.435852185 +enable_masking=0 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/27.kmac_alert_test.3381564426
Short name T1076
Test name
Test status
Simulation time 165881071 ps
CPU time 0.76 seconds
Started Jan 21 02:00:17 PM PST 24
Finished Jan 21 02:00:24 PM PST 24
Peak memory 207276 kb
Host smart-4d0d2810-1e22-47d0-b5d3-2ad025f1035a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381564426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3381564426 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest


Test location /workspace/coverage/default/27.kmac_burst_write.1932176353
Short name T1035
Test name
Test status
Simulation time 53252374808 ps
CPU time 662.09 seconds
Started Jan 21 01:59:46 PM PST 24
Finished Jan 21 02:10:48 PM PST 24
Peak memory 231172 kb
Host smart-3d74a5fb-b410-43cc-a6b5-d7b57b3a0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932176353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1932176353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest


Test location /workspace/coverage/default/27.kmac_entropy_refresh.550331579
Short name T1126
Test name
Test status
Simulation time 8695129846 ps
CPU time 251.78 seconds
Started Jan 21 02:00:03 PM PST 24
Finished Jan 21 02:04:16 PM PST 24
Peak memory 244988 kb
Host smart-11a8c0e7-c483-4d19-ae8d-e3ae4c098a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550331579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.550331579 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/27.kmac_error.2300130480
Short name T502
Test name
Test status
Simulation time 12335012985 ps
CPU time 237.8 seconds
Started Jan 21 02:00:04 PM PST 24
Finished Jan 21 02:04:04 PM PST 24
Peak memory 256420 kb
Host smart-c6cbef95-f1d5-43c6-978b-7014ec2ae4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300130480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2300130480 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest


Test location /workspace/coverage/default/27.kmac_key_error.2300519044
Short name T255
Test name
Test status
Simulation time 1542970033 ps
CPU time 3.52 seconds
Started Jan 21 02:00:17 PM PST 24
Finished Jan 21 02:00:27 PM PST 24
Peak memory 207376 kb
Host smart-c32004ab-00f6-4a59-b229-1a5980da956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300519044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2300519044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest


Test location /workspace/coverage/default/27.kmac_lc_escalation.734084811
Short name T453
Test name
Test status
Simulation time 33859510 ps
CPU time 1.28 seconds
Started Jan 21 02:00:19 PM PST 24
Finished Jan 21 02:00:24 PM PST 24
Peak memory 215920 kb
Host smart-c95d4a69-5619-4c98-a03c-7efa604afb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734084811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.734084811 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest


Test location /workspace/coverage/default/27.kmac_long_msg_and_output.2258500287
Short name T377
Test name
Test status
Simulation time 15644572117 ps
CPU time 1339.57 seconds
Started Jan 21 01:59:47 PM PST 24
Finished Jan 21 02:22:08 PM PST 24
Peak memory 358584 kb
Host smart-1a2dd19d-b115-4ca1-ae72-ff39a9959ff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258500287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.2258500287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/27.kmac_sideload.1571837147
Short name T494
Test name
Test status
Simulation time 3174553770 ps
CPU time 60.81 seconds
Started Jan 21 01:59:46 PM PST 24
Finished Jan 21 02:00:48 PM PST 24
Peak memory 223856 kb
Host smart-76087ea5-2e2a-4e04-ab9c-00aa76ac0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571837147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1571837147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest


Test location /workspace/coverage/default/27.kmac_smoke.2980407004
Short name T461
Test name
Test status
Simulation time 1483259404 ps
CPU time 23.85 seconds
Started Jan 21 01:59:48 PM PST 24
Finished Jan 21 02:00:12 PM PST 24
Peak memory 223612 kb
Host smart-1464d65a-e22b-42d4-be5a-8155e2f128e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980407004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2980407004 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest


Test location /workspace/coverage/default/27.kmac_stress_all.2107747910
Short name T881
Test name
Test status
Simulation time 1401201165 ps
CPU time 65.26 seconds
Started Jan 21 02:00:17 PM PST 24
Finished Jan 21 02:01:28 PM PST 24
Peak memory 228084 kb
Host smart-db83243c-b23e-4d19-8a1b-e9db1d090ff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2107747910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2107747910 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest


Test location /workspace/coverage/default/27.kmac_stress_all_with_rand_reset.3095370861
Short name T769
Test name
Test status
Simulation time 165828282202 ps
CPU time 930.45 seconds
Started Jan 21 02:00:19 PM PST 24
Finished Jan 21 02:15:54 PM PST 24
Peak memory 300700 kb
Host smart-444d9fbb-8fa6-476f-a737-64b6094636ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095370861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.3095370861 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.2813474586
Short name T307
Test name
Test status
Simulation time 703710156 ps
CPU time 5.04 seconds
Started Jan 21 01:59:55 PM PST 24
Finished Jan 21 02:00:05 PM PST 24
Peak memory 208432 kb
Host smart-230b931a-d3ad-4eac-afb7-fb16d93f2117
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813474586 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.2813474586 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3985514515
Short name T854
Test name
Test status
Simulation time 1593353941 ps
CPU time 4.97 seconds
Started Jan 21 02:13:00 PM PST 24
Finished Jan 21 02:13:06 PM PST 24
Peak memory 216664 kb
Host smart-b86efe96-a9cc-4428-ba1c-462b171633c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985514515 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3985514515 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.115963612
Short name T172
Test name
Test status
Simulation time 67621449345 ps
CPU time 1860.27 seconds
Started Jan 21 01:59:46 PM PST 24
Finished Jan 21 02:30:47 PM PST 24
Peak memory 391560 kb
Host smart-d10d5b7f-d141-4d44-af53-22f98636c0b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=115963612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.115963612 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.2415704525
Short name T1119
Test name
Test status
Simulation time 23290948371 ps
CPU time 1573.43 seconds
Started Jan 21 02:33:45 PM PST 24
Finished Jan 21 02:59:59 PM PST 24
Peak memory 373316 kb
Host smart-b861edb5-1475-443a-b9db-6e0f16a2973c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2415704525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.2415704525 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.2653789792
Short name T342
Test name
Test status
Simulation time 71360189078 ps
CPU time 1460.5 seconds
Started Jan 21 01:59:46 PM PST 24
Finished Jan 21 02:24:07 PM PST 24
Peak memory 333852 kb
Host smart-1beb1aa7-5d18-416e-b565-9a0329d1e683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2653789792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.2653789792 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.218439986
Short name T1059
Test name
Test status
Simulation time 143406343735 ps
CPU time 986.75 seconds
Started Jan 21 01:59:45 PM PST 24
Finished Jan 21 02:16:13 PM PST 24
Peak memory 296636 kb
Host smart-4208130c-616b-4cde-81f0-7e137e4d6945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=218439986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.218439986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.3899230753
Short name T257
Test name
Test status
Simulation time 438349948491 ps
CPU time 5330.68 seconds
Started Jan 21 01:59:46 PM PST 24
Finished Jan 21 03:28:38 PM PST 24
Peak memory 659168 kb
Host smart-11af7e39-b3d0-425a-bd7a-fdb2422ee0ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3899230753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.3899230753 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.3085177429
Short name T315
Test name
Test status
Simulation time 63220417645 ps
CPU time 3396.24 seconds
Started Jan 21 02:32:22 PM PST 24
Finished Jan 21 03:28:59 PM PST 24
Peak memory 567336 kb
Host smart-4680b2ab-1057-41b0-948a-be96fcff6f14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3085177429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3085177429 +enable_masking=0 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/28.kmac_alert_test.2646831580
Short name T446
Test name
Test status
Simulation time 99660297 ps
CPU time 0.8 seconds
Started Jan 21 02:01:05 PM PST 24
Finished Jan 21 02:01:07 PM PST 24
Peak memory 207320 kb
Host smart-bda7cb3e-cd75-42df-b73b-0e285fcd61be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646831580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2646831580 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest


Test location /workspace/coverage/default/28.kmac_app.987412594
Short name T681
Test name
Test status
Simulation time 4544613971 ps
CPU time 210.25 seconds
Started Jan 21 02:00:30 PM PST 24
Finished Jan 21 02:04:04 PM PST 24
Peak memory 241364 kb
Host smart-170c3f95-33c5-473f-b8c2-50e43372a2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987412594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.987412594 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest


Test location /workspace/coverage/default/28.kmac_burst_write.695587565
Short name T639
Test name
Test status
Simulation time 6989683282 ps
CPU time 164.57 seconds
Started Jan 21 02:00:22 PM PST 24
Finished Jan 21 02:03:08 PM PST 24
Peak memory 223912 kb
Host smart-e56c9c90-caaa-4043-a31e-89357ff4fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695587565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.695587565 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest


Test location /workspace/coverage/default/28.kmac_entropy_refresh.364803753
Short name T274
Test name
Test status
Simulation time 4512899728 ps
CPU time 36.93 seconds
Started Jan 21 02:00:42 PM PST 24
Finished Jan 21 02:01:21 PM PST 24
Peak memory 223872 kb
Host smart-640abaf3-0c85-45b1-8a4d-3e1bb12217ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364803753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.364803753 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/28.kmac_error.3979310796
Short name T443
Test name
Test status
Simulation time 7691938685 ps
CPU time 285.94 seconds
Started Jan 21 02:00:41 PM PST 24
Finished Jan 21 02:05:28 PM PST 24
Peak memory 256652 kb
Host smart-94203010-7248-4dd4-ad5c-c52890dbd71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979310796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3979310796 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest


Test location /workspace/coverage/default/28.kmac_key_error.1652204963
Short name T539
Test name
Test status
Simulation time 408980652 ps
CPU time 2.61 seconds
Started Jan 21 02:23:25 PM PST 24
Finished Jan 21 02:23:33 PM PST 24
Peak memory 207620 kb
Host smart-93db783b-fa5c-4c81-a67f-b38c1db53383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652204963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1652204963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest


Test location /workspace/coverage/default/28.kmac_lc_escalation.2175365499
Short name T7
Test name
Test status
Simulation time 70925282 ps
CPU time 1.23 seconds
Started Jan 21 02:00:47 PM PST 24
Finished Jan 21 02:00:49 PM PST 24
Peak memory 215856 kb
Host smart-63e59124-ea62-405d-b6e4-761638e9f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175365499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2175365499 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest


Test location /workspace/coverage/default/28.kmac_long_msg_and_output.1343023947
Short name T788
Test name
Test status
Simulation time 15180815661 ps
CPU time 364.97 seconds
Started Jan 21 02:00:20 PM PST 24
Finished Jan 21 02:06:28 PM PST 24
Peak memory 249732 kb
Host smart-821bd2cb-3eb4-4122-b3eb-5afd6ece270a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343023947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.1343023947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/28.kmac_sideload.4264711522
Short name T840
Test name
Test status
Simulation time 9381938597 ps
CPU time 235 seconds
Started Jan 21 02:57:08 PM PST 24
Finished Jan 21 03:01:04 PM PST 24
Peak memory 240888 kb
Host smart-6a17054d-e02c-4350-88a4-c16f0d226654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264711522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.4264711522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest


Test location /workspace/coverage/default/28.kmac_smoke.4004211494
Short name T929
Test name
Test status
Simulation time 1767927029 ps
CPU time 44.83 seconds
Started Jan 21 02:00:20 PM PST 24
Finished Jan 21 02:01:08 PM PST 24
Peak memory 223708 kb
Host smart-3844f198-b5e8-4f87-9510-00e4030edb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004211494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.4004211494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest


Test location /workspace/coverage/default/28.kmac_stress_all.1752554324
Short name T1085
Test name
Test status
Simulation time 12140028253 ps
CPU time 960.84 seconds
Started Jan 21 02:00:56 PM PST 24
Finished Jan 21 02:16:58 PM PST 24
Peak memory 354136 kb
Host smart-6821f98d-efb6-4d94-880f-f1caffe5c232
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1752554324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1752554324 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.1649522388
Short name T713
Test name
Test status
Simulation time 173803934 ps
CPU time 4.31 seconds
Started Jan 21 02:00:34 PM PST 24
Finished Jan 21 02:00:39 PM PST 24
Peak memory 208392 kb
Host smart-16be94d2-2497-40b8-99c4-0b3b150f0de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649522388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.1649522388 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.20116057
Short name T996
Test name
Test status
Simulation time 234900215 ps
CPU time 4.46 seconds
Started Jan 21 02:00:33 PM PST 24
Finished Jan 21 02:00:39 PM PST 24
Peak memory 208892 kb
Host smart-0c634394-2799-4113-bbcf-580bbbdc5f24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20116057 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.kmac_test_vectors_kmac_xof.20116057 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.797937654
Short name T288
Test name
Test status
Simulation time 47361133230 ps
CPU time 1579.78 seconds
Started Jan 21 02:00:21 PM PST 24
Finished Jan 21 02:26:43 PM PST 24
Peak memory 393408 kb
Host smart-94022a5c-a9f9-4ac7-905c-f5d7b220eee3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=797937654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.797937654 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.4152165855
Short name T220
Test name
Test status
Simulation time 72445175420 ps
CPU time 1404.21 seconds
Started Jan 21 02:00:25 PM PST 24
Finished Jan 21 02:23:51 PM PST 24
Peak memory 365752 kb
Host smart-69b23b57-6286-497b-b8cf-4540047f59ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4152165855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.4152165855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.3926687893
Short name T335
Test name
Test status
Simulation time 848389509541 ps
CPU time 1281.19 seconds
Started Jan 21 02:00:21 PM PST 24
Finished Jan 21 02:21:45 PM PST 24
Peak memory 327844 kb
Host smart-936297b2-c061-4876-8397-3517c9244c8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3926687893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3926687893 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.835490953
Short name T748
Test name
Test status
Simulation time 34274636626 ps
CPU time 955.66 seconds
Started Jan 21 02:00:26 PM PST 24
Finished Jan 21 02:16:23 PM PST 24
Peak memory 296360 kb
Host smart-09da8455-48ab-4ef8-8a62-132234dd2167
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=835490953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.835490953 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.3503999383
Short name T976
Test name
Test status
Simulation time 176326260310 ps
CPU time 4718.77 seconds
Started Jan 21 02:00:33 PM PST 24
Finished Jan 21 03:19:14 PM PST 24
Peak memory 655076 kb
Host smart-85c9ac6b-697a-4fb8-b294-11f9f1ed6be0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3503999383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.3503999383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.3024145404
Short name T1132
Test name
Test status
Simulation time 436335882104 ps
CPU time 4384.12 seconds
Started Jan 21 02:00:32 PM PST 24
Finished Jan 21 03:13:39 PM PST 24
Peak memory 565576 kb
Host smart-333e7862-53aa-4202-affa-65638a6f0281
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3024145404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.3024145404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/29.kmac_alert_test.524895690
Short name T990
Test name
Test status
Simulation time 97074927 ps
CPU time 0.75 seconds
Started Jan 21 02:01:48 PM PST 24
Finished Jan 21 02:01:49 PM PST 24
Peak memory 207280 kb
Host smart-8195f242-a035-41ce-96e6-804afd1d2b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524895690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.524895690 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest


Test location /workspace/coverage/default/29.kmac_app.1663937535
Short name T791
Test name
Test status
Simulation time 548064135 ps
CPU time 27.27 seconds
Started Jan 21 02:01:33 PM PST 24
Finished Jan 21 02:02:01 PM PST 24
Peak memory 223772 kb
Host smart-e12a4e67-3ac5-40b2-be84-91e958522cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663937535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1663937535 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest


Test location /workspace/coverage/default/29.kmac_entropy_refresh.1407976414
Short name T730
Test name
Test status
Simulation time 7127666686 ps
CPU time 111.26 seconds
Started Jan 21 02:30:39 PM PST 24
Finished Jan 21 02:32:31 PM PST 24
Peak memory 228880 kb
Host smart-7480fe4e-e0a9-4ead-9ee3-1cc8eb7c1490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407976414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1407976414 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/29.kmac_error.639410758
Short name T1096
Test name
Test status
Simulation time 1757248186 ps
CPU time 132.45 seconds
Started Jan 21 02:01:33 PM PST 24
Finished Jan 21 02:03:46 PM PST 24
Peak memory 236668 kb
Host smart-66a4ec6b-0a08-4191-a90d-2adface5fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639410758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.639410758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest


Test location /workspace/coverage/default/29.kmac_key_error.3650403435
Short name T618
Test name
Test status
Simulation time 1885176196 ps
CPU time 5.86 seconds
Started Jan 21 02:32:39 PM PST 24
Finished Jan 21 02:32:46 PM PST 24
Peak memory 207588 kb
Host smart-dbaf758b-099f-49f8-9409-68c20d740e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650403435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3650403435 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest


Test location /workspace/coverage/default/29.kmac_lc_escalation.534031174
Short name T745
Test name
Test status
Simulation time 47853813 ps
CPU time 1.37 seconds
Started Jan 21 02:24:06 PM PST 24
Finished Jan 21 02:24:10 PM PST 24
Peak memory 215768 kb
Host smart-8ef09d0b-e076-494b-88f0-57f67be2c2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534031174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.534031174 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest


Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3514594865
Short name T658
Test name
Test status
Simulation time 297056712986 ps
CPU time 1698.4 seconds
Started Jan 21 02:01:14 PM PST 24
Finished Jan 21 02:29:33 PM PST 24
Peak memory 366796 kb
Host smart-fbdb8180-c64b-4822-841c-9280f2653b57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514594865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3514594865 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/29.kmac_sideload.1927739969
Short name T85
Test name
Test status
Simulation time 4313466680 ps
CPU time 332.81 seconds
Started Jan 21 02:01:12 PM PST 24
Finished Jan 21 02:06:45 PM PST 24
Peak memory 249040 kb
Host smart-d79c7c1a-f992-4c1c-887f-bea3b4f99e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927739969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1927739969 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest


Test location /workspace/coverage/default/29.kmac_smoke.3131482016
Short name T574
Test name
Test status
Simulation time 2718534115 ps
CPU time 14.52 seconds
Started Jan 21 02:01:04 PM PST 24
Finished Jan 21 02:01:20 PM PST 24
Peak memory 217548 kb
Host smart-f1b5d0ef-2a19-4456-b66c-3ea8dd9bddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131482016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3131482016 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest


Test location /workspace/coverage/default/29.kmac_stress_all.779582808
Short name T1094
Test name
Test status
Simulation time 30255115125 ps
CPU time 847.52 seconds
Started Jan 21 02:01:39 PM PST 24
Finished Jan 21 02:15:47 PM PST 24
Peak memory 320924 kb
Host smart-b41bedba-e60a-4039-b771-bbdbd4c65ca0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=779582808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.779582808 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.3809983037
Short name T1011
Test name
Test status
Simulation time 978660492 ps
CPU time 5.21 seconds
Started Jan 21 02:39:21 PM PST 24
Finished Jan 21 02:39:27 PM PST 24
Peak memory 217048 kb
Host smart-6f5faa70-b9d1-4ca5-9afe-38c6d633644f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809983037 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.3809983037 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.3916730674
Short name T698
Test name
Test status
Simulation time 607294471 ps
CPU time 4.34 seconds
Started Jan 21 02:01:34 PM PST 24
Finished Jan 21 02:01:39 PM PST 24
Peak memory 216720 kb
Host smart-3932d075-cee1-4702-9cab-2911087bfc24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916730674 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.3916730674 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.676429260
Short name T588
Test name
Test status
Simulation time 69760894062 ps
CPU time 1909.68 seconds
Started Jan 21 02:01:15 PM PST 24
Finished Jan 21 02:33:06 PM PST 24
Peak memory 391392 kb
Host smart-d6735062-581d-473c-b90c-3240b3292b33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=676429260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.676429260 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.1718479618
Short name T452
Test name
Test status
Simulation time 61949926374 ps
CPU time 1792.58 seconds
Started Jan 21 02:52:46 PM PST 24
Finished Jan 21 03:22:40 PM PST 24
Peak memory 374720 kb
Host smart-13db3ef6-92f4-4284-8ff9-e60a21a3c465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1718479618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.1718479618 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.195658511
Short name T687
Test name
Test status
Simulation time 302744099372 ps
CPU time 1447.6 seconds
Started Jan 21 02:01:14 PM PST 24
Finished Jan 21 02:25:23 PM PST 24
Peak memory 332296 kb
Host smart-1b79a530-0c4c-4c60-91fb-c2d652262ff8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=195658511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.195658511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.1227597709
Short name T173
Test name
Test status
Simulation time 134770423470 ps
CPU time 989.06 seconds
Started Jan 21 02:01:24 PM PST 24
Finished Jan 21 02:17:54 PM PST 24
Peak memory 293104 kb
Host smart-66fefa43-ae9c-421a-af3f-300694dbf7b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1227597709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1227597709 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2123298214
Short name T491
Test name
Test status
Simulation time 2840782433900 ps
CPU time 5042.71 seconds
Started Jan 21 02:01:24 PM PST 24
Finished Jan 21 03:25:28 PM PST 24
Peak memory 640420 kb
Host smart-769db68a-11ef-4f25-b975-9c42bacd38ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2123298214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2123298214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.431728115
Short name T614
Test name
Test status
Simulation time 195726893756 ps
CPU time 4060.63 seconds
Started Jan 21 02:01:24 PM PST 24
Finished Jan 21 03:09:06 PM PST 24
Peak memory 560004 kb
Host smart-2cb5fbad-3d30-4648-b101-3464cd88a5f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=431728115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.431728115 +enable_masking=0 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/3.kmac_alert_test.3613936153
Short name T371
Test name
Test status
Simulation time 67668645 ps
CPU time 0.85 seconds
Started Jan 21 01:47:19 PM PST 24
Finished Jan 21 01:47:22 PM PST 24
Peak memory 207300 kb
Host smart-97568a8e-a4ab-4506-9f4b-cd8c0593f84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613936153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3613936153 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest


Test location /workspace/coverage/default/3.kmac_app.718928670
Short name T581
Test name
Test status
Simulation time 327981463 ps
CPU time 10.5 seconds
Started Jan 21 01:47:17 PM PST 24
Finished Jan 21 01:47:29 PM PST 24
Peak memory 223536 kb
Host smart-02b85ef5-9fc1-4b8c-852c-d45261aded90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718928670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.718928670 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest


Test location /workspace/coverage/default/3.kmac_app_with_partial_data.4096681429
Short name T419
Test name
Test status
Simulation time 7211772232 ps
CPU time 91.27 seconds
Started Jan 21 01:47:17 PM PST 24
Finished Jan 21 01:48:49 PM PST 24
Peak memory 230480 kb
Host smart-0c9e5223-5e60-4b6e-b830-647a55af9edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096681429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.4096681429 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/3.kmac_burst_write.2053103615
Short name T902
Test name
Test status
Simulation time 69280517733 ps
CPU time 377.19 seconds
Started Jan 21 01:47:17 PM PST 24
Finished Jan 21 01:53:35 PM PST 24
Peak memory 228348 kb
Host smart-ed280ee3-789c-43bb-8c86-4f47f466850f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053103615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2053103615 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest


Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3814568522
Short name T669
Test name
Test status
Simulation time 373800312 ps
CPU time 9.96 seconds
Started Jan 21 01:47:16 PM PST 24
Finished Jan 21 01:47:27 PM PST 24
Peak memory 221000 kb
Host smart-384561d0-d08f-4ade-806a-59826b7bace5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3814568522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3814568522 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/3.kmac_entropy_mode_error.2412742101
Short name T1075
Test name
Test status
Simulation time 5584638451 ps
CPU time 34.97 seconds
Started Jan 21 01:47:19 PM PST 24
Finished Jan 21 01:47:56 PM PST 24
Peak memory 223652 kb
Host smart-ea63ab03-ed60-46a8-ac71-7a18397edf17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2412742101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2412742101 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/3.kmac_entropy_ready_error.3950310952
Short name T137
Test name
Test status
Simulation time 72429935820 ps
CPU time 93.99 seconds
Started Jan 21 01:47:16 PM PST 24
Finished Jan 21 01:48:51 PM PST 24
Peak memory 222284 kb
Host smart-1e47707d-f2c9-477a-a3b4-4b22334b1e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950310952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3950310952 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/3.kmac_entropy_refresh.3110429352
Short name T988
Test name
Test status
Simulation time 20856961325 ps
CPU time 86.7 seconds
Started Jan 21 01:47:17 PM PST 24
Finished Jan 21 01:48:44 PM PST 24
Peak memory 228072 kb
Host smart-67e172a4-3be1-4aff-ad53-e69d7330bfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110429352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3110429352 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/3.kmac_error.2818184597
Short name T922
Test name
Test status
Simulation time 37286159092 ps
CPU time 261.33 seconds
Started Jan 21 01:47:15 PM PST 24
Finished Jan 21 01:51:38 PM PST 24
Peak memory 256004 kb
Host smart-cd94bfdc-203c-4944-a01e-3bdadc9c51fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818184597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2818184597 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest


Test location /workspace/coverage/default/3.kmac_key_error.1720944845
Short name T65
Test name
Test status
Simulation time 389529085 ps
CPU time 2.6 seconds
Started Jan 21 01:47:28 PM PST 24
Finished Jan 21 01:47:33 PM PST 24
Peak memory 207580 kb
Host smart-f115e88c-039e-463d-8718-f68d022bc11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720944845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1720944845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest


Test location /workspace/coverage/default/3.kmac_lc_escalation.3106749637
Short name T416
Test name
Test status
Simulation time 54122894 ps
CPU time 1.44 seconds
Started Jan 21 01:47:18 PM PST 24
Finished Jan 21 01:47:21 PM PST 24
Peak memory 215876 kb
Host smart-5cd010a4-4af1-48a3-9285-1b04d3d4bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106749637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3106749637 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest


Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2734543923
Short name T848
Test name
Test status
Simulation time 203951402159 ps
CPU time 2285.99 seconds
Started Jan 21 01:47:22 PM PST 24
Finished Jan 21 02:25:30 PM PST 24
Peak memory 457020 kb
Host smart-1d62e99e-18c5-4c69-a155-a898b7e630f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734543923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2734543923 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/3.kmac_mubi.566139556
Short name T39
Test name
Test status
Simulation time 7482665341 ps
CPU time 97.2 seconds
Started Jan 21 01:47:18 PM PST 24
Finished Jan 21 01:48:57 PM PST 24
Peak memory 231452 kb
Host smart-0f0659bc-7fa8-4ef1-9009-d1e611eeda8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566139556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.566139556 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest


Test location /workspace/coverage/default/3.kmac_sec_cm.1927288578
Short name T13
Test name
Test status
Simulation time 16393819425 ps
CPU time 36.85 seconds
Started Jan 21 01:47:29 PM PST 24
Finished Jan 21 01:48:07 PM PST 24
Peak memory 253360 kb
Host smart-0f6f4734-2c9c-4861-b368-8d86e0f8cbfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927288578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1927288578 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest


Test location /workspace/coverage/default/3.kmac_sideload.273061842
Short name T174
Test name
Test status
Simulation time 1299175031 ps
CPU time 61.03 seconds
Started Jan 21 01:47:16 PM PST 24
Finished Jan 21 01:48:18 PM PST 24
Peak memory 223852 kb
Host smart-44b2bbf9-672d-4aef-9374-2efcbfef9a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273061842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.273061842 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest


Test location /workspace/coverage/default/3.kmac_smoke.1814255084
Short name T710
Test name
Test status
Simulation time 7982438794 ps
CPU time 51.01 seconds
Started Jan 21 01:47:21 PM PST 24
Finished Jan 21 01:48:13 PM PST 24
Peak memory 219200 kb
Host smart-4ce6028d-ccfd-4156-bf67-6fe622265102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814255084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1814255084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest


Test location /workspace/coverage/default/3.kmac_stress_all.3616318774
Short name T825
Test name
Test status
Simulation time 90789412389 ps
CPU time 1487.68 seconds
Started Jan 21 01:47:23 PM PST 24
Finished Jan 21 02:12:11 PM PST 24
Peak memory 401116 kb
Host smart-d44b6a98-8e6b-46e6-8e78-7471a362dc7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3616318774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3616318774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest


Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.2306114984
Short name T403
Test name
Test status
Simulation time 155413416925 ps
CPU time 505.8 seconds
Started Jan 21 01:47:26 PM PST 24
Finished Jan 21 01:55:53 PM PST 24
Peak memory 272860 kb
Host smart-23169f70-0dbf-4537-be7f-ccc22b018473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306114984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.2306114984 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.2708613719
Short name T692
Test name
Test status
Simulation time 954363648 ps
CPU time 4.6 seconds
Started Jan 21 01:47:19 PM PST 24
Finished Jan 21 01:47:25 PM PST 24
Peak memory 216476 kb
Host smart-80580af8-8738-4ecc-befa-a08179d3ce7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708613719 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.2708613719 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.820123550
Short name T1036
Test name
Test status
Simulation time 160103289 ps
CPU time 4.23 seconds
Started Jan 21 01:47:17 PM PST 24
Finished Jan 21 01:47:23 PM PST 24
Peak memory 216792 kb
Host smart-996f991e-8f42-407d-9633-62a22ed1f419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820123550 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.kmac_test_vectors_kmac_xof.820123550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2139494999
Short name T554
Test name
Test status
Simulation time 66005556558 ps
CPU time 1717.07 seconds
Started Jan 21 01:47:29 PM PST 24
Finished Jan 21 02:16:08 PM PST 24
Peak memory 378704 kb
Host smart-302b2234-e6f2-46be-a18f-9296014bfeef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2139494999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2139494999 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1597950847
Short name T194
Test name
Test status
Simulation time 90669491488 ps
CPU time 1813.87 seconds
Started Jan 21 01:47:29 PM PST 24
Finished Jan 21 02:17:44 PM PST 24
Peak memory 370428 kb
Host smart-910ae95c-9730-426f-b136-cf7b791ccf5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1597950847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1597950847 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.2727641791
Short name T192
Test name
Test status
Simulation time 190728449871 ps
CPU time 1287.02 seconds
Started Jan 21 01:47:19 PM PST 24
Finished Jan 21 02:08:48 PM PST 24
Peak memory 327952 kb
Host smart-91607fb3-7bcb-4e20-8551-66684ed03b09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2727641791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2727641791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1160695247
Short name T530
Test name
Test status
Simulation time 176700287191 ps
CPU time 1079.03 seconds
Started Jan 21 01:47:16 PM PST 24
Finished Jan 21 02:05:16 PM PST 24
Peak memory 296848 kb
Host smart-4e0da3f0-a088-4db9-a1bf-c47dd4e54a8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1160695247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1160695247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.3199421130
Short name T471
Test name
Test status
Simulation time 1416119557570 ps
CPU time 5634.25 seconds
Started Jan 21 01:47:26 PM PST 24
Finished Jan 21 03:21:22 PM PST 24
Peak memory 643348 kb
Host smart-8197896c-9e3e-473d-9444-51ff1496edf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3199421130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3199421130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.1632546354
Short name T481
Test name
Test status
Simulation time 288941830394 ps
CPU time 3544.2 seconds
Started Jan 21 01:47:28 PM PST 24
Finished Jan 21 02:46:34 PM PST 24
Peak memory 561352 kb
Host smart-bad3fb89-9db6-4067-a9b2-a180744a7903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1632546354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1632546354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/30.kmac_alert_test.3657015832
Short name T279
Test name
Test status
Simulation time 92950120 ps
CPU time 0.79 seconds
Started Jan 21 02:02:32 PM PST 24
Finished Jan 21 02:02:48 PM PST 24
Peak memory 207340 kb
Host smart-a4548810-da34-4e8d-bd43-7ef57339a098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657015832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3657015832 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest


Test location /workspace/coverage/default/30.kmac_app.245248958
Short name T677
Test name
Test status
Simulation time 2890778008 ps
CPU time 41.95 seconds
Started Jan 21 02:02:22 PM PST 24
Finished Jan 21 02:03:30 PM PST 24
Peak memory 223880 kb
Host smart-6c2ccfae-e817-4c7f-9e0e-b607c96b9594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245248958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.245248958 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest


Test location /workspace/coverage/default/30.kmac_entropy_refresh.3085743894
Short name T282
Test name
Test status
Simulation time 1480153231 ps
CPU time 13.6 seconds
Started Jan 21 02:02:22 PM PST 24
Finished Jan 21 02:03:01 PM PST 24
Peak memory 222292 kb
Host smart-54eb21a3-8ca2-4f62-97b3-98654a943487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085743894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3085743894 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/30.kmac_error.550621220
Short name T699
Test name
Test status
Simulation time 8580643077 ps
CPU time 159.27 seconds
Started Jan 21 02:02:22 PM PST 24
Finished Jan 21 02:05:27 PM PST 24
Peak memory 252624 kb
Host smart-f9cc7240-9136-4167-9113-bd0d8dcebe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550621220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.550621220 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest


Test location /workspace/coverage/default/30.kmac_key_error.1568468354
Short name T64
Test name
Test status
Simulation time 409488396 ps
CPU time 1.23 seconds
Started Jan 21 02:02:22 PM PST 24
Finished Jan 21 02:02:49 PM PST 24
Peak memory 207308 kb
Host smart-43025343-18a7-4bcd-8ad7-56d18de77ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568468354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1568468354 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest


Test location /workspace/coverage/default/30.kmac_lc_escalation.525658304
Short name T199
Test name
Test status
Simulation time 28107408 ps
CPU time 1.25 seconds
Started Jan 21 02:02:19 PM PST 24
Finished Jan 21 02:02:49 PM PST 24
Peak memory 215956 kb
Host smart-f89be18a-45fb-428b-8564-8ff41ce51bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525658304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.525658304 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest


Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3172158444
Short name T1090
Test name
Test status
Simulation time 62329496284 ps
CPU time 671.63 seconds
Started Jan 21 02:01:48 PM PST 24
Finished Jan 21 02:13:01 PM PST 24
Peak memory 279368 kb
Host smart-6827f172-f27e-43c3-925d-2f06fa56f070
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172158444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3172158444 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/30.kmac_sideload.375858669
Short name T701
Test name
Test status
Simulation time 1989641734 ps
CPU time 141.17 seconds
Started Jan 21 02:01:50 PM PST 24
Finished Jan 21 02:04:13 PM PST 24
Peak memory 232196 kb
Host smart-bb544e79-f6ef-47dc-9fb1-0eaa50dffbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375858669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.375858669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest


Test location /workspace/coverage/default/30.kmac_smoke.3570447263
Short name T475
Test name
Test status
Simulation time 17330044564 ps
CPU time 57.54 seconds
Started Jan 21 02:01:48 PM PST 24
Finished Jan 21 02:02:48 PM PST 24
Peak memory 219300 kb
Host smart-98240e42-57f2-4dca-a2b1-0b1cdf42eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570447263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3570447263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest


Test location /workspace/coverage/default/30.kmac_stress_all.2297641868
Short name T1129
Test name
Test status
Simulation time 17460845501 ps
CPU time 524.67 seconds
Started Jan 21 02:02:33 PM PST 24
Finished Jan 21 02:11:32 PM PST 24
Peak memory 294152 kb
Host smart-e4f2870b-00f3-49e9-8cc7-18691d355b86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2297641868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2297641868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest


Test location /workspace/coverage/default/30.kmac_stress_all_with_rand_reset.3210428967
Short name T33
Test name
Test status
Simulation time 26661427703 ps
CPU time 522.87 seconds
Started Jan 21 02:02:34 PM PST 24
Finished Jan 21 02:11:30 PM PST 24
Peak memory 273056 kb
Host smart-d8964216-e482-482a-b267-10568d18b8d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210428967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all_with_rand_reset.3210428967 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.442204088
Short name T421
Test name
Test status
Simulation time 191513038 ps
CPU time 3.87 seconds
Started Jan 21 02:01:58 PM PST 24
Finished Jan 21 02:02:02 PM PST 24
Peak memory 217336 kb
Host smart-da59f521-89b4-4477-a104-16bdb949374c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442204088 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.kmac_test_vectors_kmac.442204088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.4198698425
Short name T1080
Test name
Test status
Simulation time 1241686255 ps
CPU time 5.3 seconds
Started Jan 21 02:02:08 PM PST 24
Finished Jan 21 02:02:15 PM PST 24
Peak memory 216596 kb
Host smart-5e701269-94ad-4565-8604-8c7070e36b47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198698425 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.4198698425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.1970662230
Short name T908
Test name
Test status
Simulation time 200692303672 ps
CPU time 2069.77 seconds
Started Jan 21 02:01:56 PM PST 24
Finished Jan 21 02:36:27 PM PST 24
Peak memory 404076 kb
Host smart-ab38ede8-bde7-45df-8695-22f728a1975c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1970662230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.1970662230 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.3742409687
Short name T1061
Test name
Test status
Simulation time 123356723152 ps
CPU time 1677.55 seconds
Started Jan 21 02:01:58 PM PST 24
Finished Jan 21 02:29:56 PM PST 24
Peak memory 369588 kb
Host smart-26b119d5-56a4-4d88-80ec-6b014857d2e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3742409687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.3742409687 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.2730704018
Short name T807
Test name
Test status
Simulation time 68493423469 ps
CPU time 1344.19 seconds
Started Jan 21 02:01:57 PM PST 24
Finished Jan 21 02:24:22 PM PST 24
Peak memory 334484 kb
Host smart-0e2da528-42e5-412c-aed1-a908691b0997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2730704018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2730704018 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.304724947
Short name T994
Test name
Test status
Simulation time 36604585714 ps
CPU time 754.44 seconds
Started Jan 21 02:01:57 PM PST 24
Finished Jan 21 02:14:32 PM PST 24
Peak memory 287040 kb
Host smart-d2c6a98d-30c4-499f-9edf-05b5578e8d4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=304724947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.304724947 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.932267550
Short name T693
Test name
Test status
Simulation time 525875083798 ps
CPU time 5314.11 seconds
Started Jan 21 02:01:55 PM PST 24
Finished Jan 21 03:30:31 PM PST 24
Peak memory 653944 kb
Host smart-c6da2ebe-12b2-43ea-b1d6-4815d509a6dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=932267550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.932267550 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.2212948111
Short name T579
Test name
Test status
Simulation time 154348858972 ps
CPU time 3936.46 seconds
Started Jan 21 02:01:58 PM PST 24
Finished Jan 21 03:07:35 PM PST 24
Peak memory 567864 kb
Host smart-18aa9f03-3e5e-4058-a45a-b044c09abe64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2212948111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.2212948111 +enable_masking=0 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/31.kmac_alert_test.2612206461
Short name T926
Test name
Test status
Simulation time 52698658 ps
CPU time 0.83 seconds
Started Jan 21 02:03:37 PM PST 24
Finished Jan 21 02:04:03 PM PST 24
Peak memory 207332 kb
Host smart-900759b6-dc94-492b-9ca0-659f23b0c9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612206461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2612206461 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest


Test location /workspace/coverage/default/31.kmac_app.1267522850
Short name T741
Test name
Test status
Simulation time 9935692314 ps
CPU time 158.36 seconds
Started Jan 21 02:24:56 PM PST 24
Finished Jan 21 02:27:35 PM PST 24
Peak memory 238540 kb
Host smart-9b137321-9e55-4315-ab12-24563a2d327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267522850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1267522850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest


Test location /workspace/coverage/default/31.kmac_burst_write.2755717266
Short name T434
Test name
Test status
Simulation time 19397936481 ps
CPU time 605.98 seconds
Started Jan 21 02:02:48 PM PST 24
Finished Jan 21 02:12:56 PM PST 24
Peak memory 231168 kb
Host smart-d32d3136-3264-47a1-beaa-02c4c1d47323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755717266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2755717266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest


Test location /workspace/coverage/default/31.kmac_entropy_refresh.3846104284
Short name T776
Test name
Test status
Simulation time 1204266309 ps
CPU time 61.82 seconds
Started Jan 21 02:03:29 PM PST 24
Finished Jan 21 02:04:45 PM PST 24
Peak memory 225060 kb
Host smart-7fa68da6-796c-420c-ac0b-ae1ca8091f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846104284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3846104284 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/31.kmac_error.2917317780
Short name T527
Test name
Test status
Simulation time 7963631290 ps
CPU time 204.32 seconds
Started Jan 21 02:03:32 PM PST 24
Finished Jan 21 02:07:13 PM PST 24
Peak memory 248472 kb
Host smart-49e97561-752e-4677-9b1b-2607c830ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917317780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2917317780 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest


Test location /workspace/coverage/default/31.kmac_key_error.1842526162
Short name T1111
Test name
Test status
Simulation time 2899074967 ps
CPU time 4.44 seconds
Started Jan 21 02:39:10 PM PST 24
Finished Jan 21 02:39:16 PM PST 24
Peak memory 207520 kb
Host smart-5a0d7f61-e612-42d8-a736-0887a3176cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842526162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1842526162 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest


Test location /workspace/coverage/default/31.kmac_lc_escalation.4070058896
Short name T303
Test name
Test status
Simulation time 714116232 ps
CPU time 19.17 seconds
Started Jan 21 02:03:33 PM PST 24
Finished Jan 21 02:04:18 PM PST 24
Peak memory 233268 kb
Host smart-7f108eb7-98ca-4c6d-b15a-96aeba904534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070058896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.4070058896 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest


Test location /workspace/coverage/default/31.kmac_long_msg_and_output.3147015264
Short name T517
Test name
Test status
Simulation time 30322487409 ps
CPU time 1357.57 seconds
Started Jan 21 02:02:50 PM PST 24
Finished Jan 21 02:25:29 PM PST 24
Peak memory 368684 kb
Host smart-eca9db4d-9ea0-4a8b-a986-728276981afc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147015264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.3147015264 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/31.kmac_sideload.3036477579
Short name T839
Test name
Test status
Simulation time 28985144274 ps
CPU time 404.19 seconds
Started Jan 21 02:02:51 PM PST 24
Finished Jan 21 02:09:36 PM PST 24
Peak memory 249532 kb
Host smart-238765d2-e7dc-4cc0-9702-e52f2c4a7430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036477579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3036477579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest


Test location /workspace/coverage/default/31.kmac_smoke.2089882245
Short name T439
Test name
Test status
Simulation time 583448100 ps
CPU time 8.45 seconds
Started Jan 21 02:02:32 PM PST 24
Finished Jan 21 02:02:56 PM PST 24
Peak memory 217324 kb
Host smart-dfe4a95d-afd7-47ee-a290-45ab4a2a46b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089882245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2089882245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest


Test location /workspace/coverage/default/31.kmac_stress_all.1311940606
Short name T560
Test name
Test status
Simulation time 8563792707 ps
CPU time 213.07 seconds
Started Jan 21 02:03:36 PM PST 24
Finished Jan 21 02:07:35 PM PST 24
Peak memory 268228 kb
Host smart-ff3de5bd-a8e0-46fb-af87-80238b750b89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1311940606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1311940606 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest


Test location /workspace/coverage/default/31.kmac_stress_all_with_rand_reset.3485269034
Short name T899
Test name
Test status
Simulation time 36796612119 ps
CPU time 969.54 seconds
Started Jan 21 02:03:36 PM PST 24
Finished Jan 21 02:20:12 PM PST 24
Peak memory 319396 kb
Host smart-d6ef610e-cb0b-44fc-b54b-41507799fad6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485269034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all_with_rand_reset.3485269034 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.2218741863
Short name T635
Test name
Test status
Simulation time 1088386436 ps
CPU time 5.06 seconds
Started Jan 21 02:27:05 PM PST 24
Finished Jan 21 02:27:11 PM PST 24
Peak memory 217148 kb
Host smart-50ad8ba9-6b5a-4516-8f69-f4460880c0d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218741863 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.2218741863 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.1784631578
Short name T251
Test name
Test status
Simulation time 250532132 ps
CPU time 4.76 seconds
Started Jan 21 02:37:46 PM PST 24
Finished Jan 21 02:37:57 PM PST 24
Peak memory 216980 kb
Host smart-d48f851f-8f63-472c-a777-aaddae7ecad4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784631578 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.1784631578 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.2527166593
Short name T320
Test name
Test status
Simulation time 154488171404 ps
CPU time 1560.92 seconds
Started Jan 21 02:02:51 PM PST 24
Finished Jan 21 02:28:53 PM PST 24
Peak memory 378932 kb
Host smart-a391dd35-935b-47ca-85e8-340e5cccf297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2527166593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.2527166593 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.3942609449
Short name T365
Test name
Test status
Simulation time 98130329759 ps
CPU time 1955.82 seconds
Started Jan 21 02:21:19 PM PST 24
Finished Jan 21 02:53:59 PM PST 24
Peak memory 376808 kb
Host smart-81069f4e-1974-4f8f-9183-95f08910d61a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3942609449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.3942609449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.3962814619
Short name T343
Test name
Test status
Simulation time 139817036149 ps
CPU time 1207.57 seconds
Started Jan 21 02:02:50 PM PST 24
Finished Jan 21 02:22:59 PM PST 24
Peak memory 341588 kb
Host smart-e5f0b5f7-a75e-428e-b28a-957d88879c39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3962814619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.3962814619 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1445014557
Short name T299
Test name
Test status
Simulation time 367072625649 ps
CPU time 1043.28 seconds
Started Jan 21 02:02:51 PM PST 24
Finished Jan 21 02:20:15 PM PST 24
Peak memory 296016 kb
Host smart-42018fbe-021f-484e-9baf-738f284c9e52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1445014557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1445014557 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.3464881629
Short name T155
Test name
Test status
Simulation time 554081142260 ps
CPU time 5040.94 seconds
Started Jan 21 02:02:49 PM PST 24
Finished Jan 21 03:26:52 PM PST 24
Peak memory 649032 kb
Host smart-616c2a5d-d6b9-46be-901d-1f04ab26b1af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3464881629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.3464881629 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.1845985219
Short name T1124
Test name
Test status
Simulation time 603981976184 ps
CPU time 3995.93 seconds
Started Jan 21 02:42:04 PM PST 24
Finished Jan 21 03:48:41 PM PST 24
Peak memory 558960 kb
Host smart-ca8934f0-da8e-402e-8ff7-29c69911bfaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1845985219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.1845985219 +enable_masking=0 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/32.kmac_alert_test.2014904209
Short name T746
Test name
Test status
Simulation time 29528652 ps
CPU time 0.81 seconds
Started Jan 21 02:04:42 PM PST 24
Finished Jan 21 02:04:46 PM PST 24
Peak memory 207340 kb
Host smart-a34df513-6fd8-449d-bfa7-b9520de178af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014904209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2014904209 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest


Test location /workspace/coverage/default/32.kmac_app.305930574
Short name T101
Test name
Test status
Simulation time 3269997152 ps
CPU time 69.91 seconds
Started Jan 21 02:24:16 PM PST 24
Finished Jan 21 02:25:26 PM PST 24
Peak memory 225332 kb
Host smart-8242691f-419d-4279-80ae-f5dbe3dd94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305930574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.305930574 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest


Test location /workspace/coverage/default/32.kmac_burst_write.2125311928
Short name T16
Test name
Test status
Simulation time 14947572804 ps
CPU time 663.16 seconds
Started Jan 21 02:03:39 PM PST 24
Finished Jan 21 02:15:09 PM PST 24
Peak memory 229728 kb
Host smart-a009e25e-08aa-466b-9d0c-f446d0a9aab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125311928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2125311928 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest


Test location /workspace/coverage/default/32.kmac_entropy_refresh.1009876982
Short name T865
Test name
Test status
Simulation time 49326647761 ps
CPU time 289.57 seconds
Started Jan 21 02:31:15 PM PST 24
Finished Jan 21 02:36:05 PM PST 24
Peak memory 244672 kb
Host smart-ae84d77c-c89f-416f-98d0-07dd1d175498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009876982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1009876982 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/32.kmac_error.2861434344
Short name T139
Test name
Test status
Simulation time 2955404060 ps
CPU time 209.34 seconds
Started Jan 21 02:04:24 PM PST 24
Finished Jan 21 02:07:58 PM PST 24
Peak memory 251760 kb
Host smart-0bb64964-fccd-441d-95e1-fcdd4c04ce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861434344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2861434344 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest


Test location /workspace/coverage/default/32.kmac_key_error.3915347988
Short name T61
Test name
Test status
Simulation time 1570616177 ps
CPU time 2.92 seconds
Started Jan 21 02:04:23 PM PST 24
Finished Jan 21 02:04:27 PM PST 24
Peak memory 207504 kb
Host smart-7d61aec2-f979-4ebf-85ab-693f76aa1dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915347988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3915347988 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest


Test location /workspace/coverage/default/32.kmac_lc_escalation.2998261520
Short name T1063
Test name
Test status
Simulation time 198161180 ps
CPU time 1.46 seconds
Started Jan 21 02:04:24 PM PST 24
Finished Jan 21 02:04:33 PM PST 24
Peak memory 220124 kb
Host smart-1474dbf1-6ecd-4244-9291-069bf6b8fada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998261520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2998261520 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest


Test location /workspace/coverage/default/32.kmac_long_msg_and_output.1317770137
Short name T1077
Test name
Test status
Simulation time 23116883168 ps
CPU time 1902.29 seconds
Started Jan 21 02:03:39 PM PST 24
Finished Jan 21 02:35:49 PM PST 24
Peak memory 436780 kb
Host smart-9d8d4eb1-caf2-4618-b5ae-e7080ae9fe48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317770137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.1317770137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/32.kmac_sideload.801738877
Short name T837
Test name
Test status
Simulation time 6394875941 ps
CPU time 116.3 seconds
Started Jan 21 02:03:38 PM PST 24
Finished Jan 21 02:06:02 PM PST 24
Peak memory 227504 kb
Host smart-0b37d6a3-2ea8-460a-b183-8ca7fa1399ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801738877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.801738877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest


Test location /workspace/coverage/default/32.kmac_smoke.623265913
Short name T324
Test name
Test status
Simulation time 2191197834 ps
CPU time 27.79 seconds
Started Jan 21 02:03:36 PM PST 24
Finished Jan 21 02:04:30 PM PST 24
Peak memory 223724 kb
Host smart-36c914bf-ea90-46cd-9a86-3ad3879d8b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623265913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.623265913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest


Test location /workspace/coverage/default/32.kmac_stress_all.18183278
Short name T341
Test name
Test status
Simulation time 6249884779 ps
CPU time 59.97 seconds
Started Jan 21 02:25:51 PM PST 24
Finished Jan 21 02:26:56 PM PST 24
Peak memory 226264 kb
Host smart-15dad8d3-c9e2-4eb4-8de9-57bd459bd9e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=18183278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.18183278 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest


Test location /workspace/coverage/default/32.kmac_stress_all_with_rand_reset.180384615
Short name T428
Test name
Test status
Simulation time 100751163463 ps
CPU time 170.22 seconds
Started Jan 21 02:04:41 PM PST 24
Finished Jan 21 02:07:34 PM PST 24
Peak memory 240160 kb
Host smart-d265eb8d-4525-44c2-9a1b-0372cc89edc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=180384615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all_with_rand_reset.180384615 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.2629050955
Short name T616
Test name
Test status
Simulation time 180210787 ps
CPU time 4.17 seconds
Started Jan 21 02:03:53 PM PST 24
Finished Jan 21 02:04:16 PM PST 24
Peak memory 208904 kb
Host smart-b12a909f-a425-4979-9dc9-10129b9883d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629050955 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.2629050955 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2259824271
Short name T904
Test name
Test status
Simulation time 247434765 ps
CPU time 3.64 seconds
Started Jan 21 02:23:47 PM PST 24
Finished Jan 21 02:23:51 PM PST 24
Peak memory 208924 kb
Host smart-1859ff75-6abf-4eb2-8fe3-1a276d48e521
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259824271 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2259824271 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.3867131345
Short name T890
Test name
Test status
Simulation time 66786757975 ps
CPU time 1777.82 seconds
Started Jan 21 02:35:37 PM PST 24
Finished Jan 21 03:05:16 PM PST 24
Peak memory 386772 kb
Host smart-be80cdfa-c781-4f06-a7c5-9469c3b7adee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3867131345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3867131345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.150281041
Short name T850
Test name
Test status
Simulation time 162444669193 ps
CPU time 1713.83 seconds
Started Jan 21 02:03:54 PM PST 24
Finished Jan 21 02:32:46 PM PST 24
Peak memory 373408 kb
Host smart-6a5771f9-0a0e-45bd-883c-6403bcafd3d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=150281041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.150281041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.3138090056
Short name T974
Test name
Test status
Simulation time 27431571305 ps
CPU time 1133.32 seconds
Started Jan 21 02:03:53 PM PST 24
Finished Jan 21 02:23:03 PM PST 24
Peak memory 336524 kb
Host smart-b77d3f0a-3902-4f4e-aab0-e51450f8308c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3138090056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3138090056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.3144706806
Short name T570
Test name
Test status
Simulation time 9976536293 ps
CPU time 780.77 seconds
Started Jan 21 02:03:54 PM PST 24
Finished Jan 21 02:17:13 PM PST 24
Peak memory 292056 kb
Host smart-3b16aee0-7507-4e8c-a359-10b308f50395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3144706806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3144706806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.2563174263
Short name T621
Test name
Test status
Simulation time 170291801266 ps
CPU time 4697.96 seconds
Started Jan 21 02:03:55 PM PST 24
Finished Jan 21 03:22:30 PM PST 24
Peak memory 639980 kb
Host smart-ccd5e621-825a-4a89-b05b-0137969f79c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2563174263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.2563174263 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.2798086591
Short name T613
Test name
Test status
Simulation time 859799936079 ps
CPU time 4401.62 seconds
Started Jan 21 02:12:58 PM PST 24
Finished Jan 21 03:26:21 PM PST 24
Peak memory 554256 kb
Host smart-54579ecc-1c54-43a5-8fd5-a4aa88e22b67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2798086591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2798086591 +enable_masking=0 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/33.kmac_alert_test.2678591302
Short name T556
Test name
Test status
Simulation time 56962605 ps
CPU time 0.76 seconds
Started Jan 21 02:05:24 PM PST 24
Finished Jan 21 02:05:28 PM PST 24
Peak memory 207168 kb
Host smart-e557d784-fe18-42c2-ac8e-a68a9cf82d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678591302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2678591302 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest


Test location /workspace/coverage/default/33.kmac_app.2534762214
Short name T245
Test name
Test status
Simulation time 35505467529 ps
CPU time 180.08 seconds
Started Jan 21 03:04:19 PM PST 24
Finished Jan 21 03:07:21 PM PST 24
Peak memory 240244 kb
Host smart-e55296d9-8795-487c-965a-20ef4d078178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534762214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2534762214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest


Test location /workspace/coverage/default/33.kmac_burst_write.1411971044
Short name T1021
Test name
Test status
Simulation time 1797088184 ps
CPU time 148.8 seconds
Started Jan 21 02:05:00 PM PST 24
Finished Jan 21 02:07:32 PM PST 24
Peak memory 223796 kb
Host smart-ba81dd0d-6b2e-4596-a815-d27eb96d5fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411971044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1411971044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest


Test location /workspace/coverage/default/33.kmac_entropy_refresh.1571403144
Short name T860
Test name
Test status
Simulation time 14077654367 ps
CPU time 315.73 seconds
Started Jan 21 02:41:34 PM PST 24
Finished Jan 21 02:46:51 PM PST 24
Peak memory 245552 kb
Host smart-cd8af3a1-e219-46e6-b49f-6d4781009ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571403144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1571403144 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/33.kmac_error.192864337
Short name T578
Test name
Test status
Simulation time 43429525322 ps
CPU time 289.8 seconds
Started Jan 21 02:30:33 PM PST 24
Finished Jan 21 02:35:24 PM PST 24
Peak memory 254596 kb
Host smart-30f1bd97-83ca-4d42-b0f0-552c3cd79d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192864337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.192864337 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest


Test location /workspace/coverage/default/33.kmac_key_error.427207995
Short name T67
Test name
Test status
Simulation time 377468191 ps
CPU time 1.09 seconds
Started Jan 21 02:05:21 PM PST 24
Finished Jan 21 02:05:24 PM PST 24
Peak memory 207316 kb
Host smart-1e70bc14-3c70-416c-9465-d07f317d79ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427207995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.427207995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest


Test location /workspace/coverage/default/33.kmac_lc_escalation.598582916
Short name T799
Test name
Test status
Simulation time 63053260 ps
CPU time 1.26 seconds
Started Jan 21 02:05:18 PM PST 24
Finished Jan 21 02:05:20 PM PST 24
Peak memory 215944 kb
Host smart-234dfaa5-04c3-44d2-9918-e291c22f2969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598582916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.598582916 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/33.kmac_lc_escalation/latest


Test location /workspace/coverage/default/33.kmac_long_msg_and_output.939902418
Short name T1136
Test name
Test status
Simulation time 31726333696 ps
CPU time 181.43 seconds
Started Jan 21 02:04:51 PM PST 24
Finished Jan 21 02:07:55 PM PST 24
Peak memory 236480 kb
Host smart-47bda9b6-7537-4c3b-ac63-9a58e51324a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939902418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_an
d_output.939902418 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/33.kmac_sideload.2454364367
Short name T952
Test name
Test status
Simulation time 4249661661 ps
CPU time 338.44 seconds
Started Jan 21 02:37:36 PM PST 24
Finished Jan 21 02:43:16 PM PST 24
Peak memory 251032 kb
Host smart-a2a18b5d-18a1-4ed7-bd19-cc5d05cfe68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454364367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2454364367 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest


Test location /workspace/coverage/default/33.kmac_smoke.3549439453
Short name T972
Test name
Test status
Simulation time 1164206059 ps
CPU time 7.51 seconds
Started Jan 21 02:04:50 PM PST 24
Finished Jan 21 02:05:00 PM PST 24
Peak memory 217460 kb
Host smart-708f5724-bdf4-4dcc-8372-c1f5f30a5410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549439453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3549439453 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest


Test location /workspace/coverage/default/33.kmac_stress_all.158656165
Short name T397
Test name
Test status
Simulation time 6265398016 ps
CPU time 400.27 seconds
Started Jan 21 02:05:18 PM PST 24
Finished Jan 21 02:12:01 PM PST 24
Peak memory 297736 kb
Host smart-b75c749a-9c51-4801-bd8d-4240f7fb0542
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=158656165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.158656165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest


Test location /workspace/coverage/default/33.kmac_stress_all_with_rand_reset.346817383
Short name T844
Test name
Test status
Simulation time 123179927138 ps
CPU time 1410.96 seconds
Started Jan 21 02:05:26 PM PST 24
Finished Jan 21 02:29:01 PM PST 24
Peak memory 321148 kb
Host smart-a9148488-10eb-452a-bb4b-17dfa15715d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346817383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.346817383 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.1587833061
Short name T1009
Test name
Test status
Simulation time 2523543432 ps
CPU time 5.11 seconds
Started Jan 21 02:05:07 PM PST 24
Finished Jan 21 02:05:14 PM PST 24
Peak memory 217532 kb
Host smart-55e6d688-5346-47cc-ad4d-122ae2b491c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587833061 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.1587833061 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.4058847795
Short name T441
Test name
Test status
Simulation time 349505647 ps
CPU time 4.76 seconds
Started Jan 21 02:23:09 PM PST 24
Finished Jan 21 02:23:16 PM PST 24
Peak memory 217156 kb
Host smart-32508b47-cda1-424a-b4b7-d2842d31c6d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058847795 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.4058847795 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.1385141551
Short name T408
Test name
Test status
Simulation time 75163041964 ps
CPU time 1568.09 seconds
Started Jan 21 02:17:57 PM PST 24
Finished Jan 21 02:44:06 PM PST 24
Peak memory 391056 kb
Host smart-f7812558-c1bf-409c-adf2-70fd1f63b685
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1385141551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1385141551 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.3225564065
Short name T559
Test name
Test status
Simulation time 17850323816 ps
CPU time 1508.59 seconds
Started Jan 21 02:56:02 PM PST 24
Finished Jan 21 03:21:12 PM PST 24
Peak memory 375292 kb
Host smart-45fdba3a-7324-4de8-9c5d-793bad0f1ecb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3225564065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3225564065 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.3753152941
Short name T1022
Test name
Test status
Simulation time 70086217030 ps
CPU time 1439.8 seconds
Started Jan 21 02:23:09 PM PST 24
Finished Jan 21 02:47:11 PM PST 24
Peak memory 333016 kb
Host smart-511249f0-b1b5-4e8c-9289-01ad7f50934e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3753152941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3753152941 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.820593517
Short name T483
Test name
Test status
Simulation time 66969363787 ps
CPU time 963.79 seconds
Started Jan 21 02:05:10 PM PST 24
Finished Jan 21 02:21:15 PM PST 24
Peak memory 295616 kb
Host smart-9f48466f-c9c6-46a1-9f87-098de036279f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=820593517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.820593517 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.1287469486
Short name T1025
Test name
Test status
Simulation time 266728321660 ps
CPU time 5290.54 seconds
Started Jan 21 02:41:24 PM PST 24
Finished Jan 21 04:09:36 PM PST 24
Peak memory 657732 kb
Host smart-12d3f4ba-798c-44aa-a860-911dd0c95c05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1287469486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.1287469486 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.3901126320
Short name T1010
Test name
Test status
Simulation time 274358792549 ps
CPU time 4274.42 seconds
Started Jan 21 02:22:39 PM PST 24
Finished Jan 21 03:33:54 PM PST 24
Peak memory 562256 kb
Host smart-acee5b94-5e99-4cc8-9798-445eab482655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3901126320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.3901126320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/34.kmac_alert_test.2132439273
Short name T44
Test name
Test status
Simulation time 112530294 ps
CPU time 0.79 seconds
Started Jan 21 02:06:07 PM PST 24
Finished Jan 21 02:06:09 PM PST 24
Peak memory 207304 kb
Host smart-04a856d0-56d2-407d-8a60-86fafc4a6173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132439273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2132439273 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest


Test location /workspace/coverage/default/34.kmac_app.2782722007
Short name T322
Test name
Test status
Simulation time 4768259124 ps
CPU time 45.53 seconds
Started Jan 21 02:05:57 PM PST 24
Finished Jan 21 02:06:43 PM PST 24
Peak memory 223864 kb
Host smart-99cfa182-d1ec-441d-845c-1bc41b994053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782722007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2782722007 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest


Test location /workspace/coverage/default/34.kmac_burst_write.1678023177
Short name T978
Test name
Test status
Simulation time 4977761100 ps
CPU time 111.85 seconds
Started Jan 21 02:05:27 PM PST 24
Finished Jan 21 02:07:21 PM PST 24
Peak memory 223876 kb
Host smart-28092ca7-1302-4d8a-88e9-4a7a63d8421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678023177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1678023177 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest


Test location /workspace/coverage/default/34.kmac_entropy_refresh.3002250712
Short name T314
Test name
Test status
Simulation time 15478161406 ps
CPU time 239.87 seconds
Started Jan 21 02:05:55 PM PST 24
Finished Jan 21 02:09:55 PM PST 24
Peak memory 242316 kb
Host smart-9e133e86-cd52-4323-ab9a-7e295cbc78c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002250712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3002250712 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/34.kmac_error.2742088371
Short name T851
Test name
Test status
Simulation time 4044602074 ps
CPU time 316.54 seconds
Started Jan 21 02:05:53 PM PST 24
Finished Jan 21 02:11:11 PM PST 24
Peak memory 256592 kb
Host smart-4cf26d98-d5fd-4ef3-b70e-aa7ee9efe6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742088371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2742088371 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest


Test location /workspace/coverage/default/34.kmac_key_error.1626592772
Short name T25
Test name
Test status
Simulation time 5733475832 ps
CPU time 5.37 seconds
Started Jan 21 02:06:07 PM PST 24
Finished Jan 21 02:06:13 PM PST 24
Peak memory 207572 kb
Host smart-0530edf1-ae99-44f3-a49f-0f7135cdf354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626592772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1626592772 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest


Test location /workspace/coverage/default/34.kmac_lc_escalation.2933549461
Short name T950
Test name
Test status
Simulation time 1040159484 ps
CPU time 25.28 seconds
Started Jan 21 02:06:12 PM PST 24
Finished Jan 21 02:06:38 PM PST 24
Peak memory 232412 kb
Host smart-a9a6d9ce-70f3-43b9-8540-f7cfb9fe2291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933549461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2933549461 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest


Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2167776430
Short name T244
Test name
Test status
Simulation time 1576246098596 ps
CPU time 2761.96 seconds
Started Jan 21 02:05:27 PM PST 24
Finished Jan 21 02:51:32 PM PST 24
Peak memory 474464 kb
Host smart-50431feb-6f5a-4b70-a74b-c8f08d5b3095
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167776430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2167776430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/34.kmac_sideload.1634494287
Short name T820
Test name
Test status
Simulation time 276522437 ps
CPU time 21.22 seconds
Started Jan 21 02:05:27 PM PST 24
Finished Jan 21 02:05:51 PM PST 24
Peak memory 223840 kb
Host smart-381e259c-5d2a-40c1-8822-686e94ccf0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634494287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1634494287 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest


Test location /workspace/coverage/default/34.kmac_smoke.173775579
Short name T626
Test name
Test status
Simulation time 52668857 ps
CPU time 2.7 seconds
Started Jan 21 02:05:24 PM PST 24
Finished Jan 21 02:05:29 PM PST 24
Peak memory 216484 kb
Host smart-830bb1b9-1c3b-4b2f-843c-911a0b09863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173775579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.173775579 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest


Test location /workspace/coverage/default/34.kmac_stress_all.2778808529
Short name T983
Test name
Test status
Simulation time 17580572248 ps
CPU time 1414.97 seconds
Started Jan 21 02:06:12 PM PST 24
Finished Jan 21 02:29:48 PM PST 24
Peak memory 415584 kb
Host smart-dcce67e1-1afa-4b7e-98f9-feb8a6e3386b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2778808529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2778808529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest


Test location /workspace/coverage/default/34.kmac_stress_all_with_rand_reset.370955402
Short name T29
Test name
Test status
Simulation time 4066231116 ps
CPU time 70.89 seconds
Started Jan 21 02:06:06 PM PST 24
Finished Jan 21 02:07:18 PM PST 24
Peak memory 240312 kb
Host smart-b921367f-358d-40df-a07c-e9ad88fe39bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370955402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all_with_rand_reset.370955402 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3556348456
Short name T468
Test name
Test status
Simulation time 1006582464 ps
CPU time 5.19 seconds
Started Jan 21 02:05:55 PM PST 24
Finished Jan 21 02:06:01 PM PST 24
Peak memory 209024 kb
Host smart-de11e382-9386-4439-8c6b-e1aa338dd8ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556348456 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.3556348456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.3632789346
Short name T665
Test name
Test status
Simulation time 868010732 ps
CPU time 5.68 seconds
Started Jan 21 02:48:09 PM PST 24
Finished Jan 21 02:48:17 PM PST 24
Peak memory 209044 kb
Host smart-671d5500-dc89-48f3-a5ed-e41fa1911f3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632789346 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.3632789346 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.3831265736
Short name T765
Test name
Test status
Simulation time 39107046996 ps
CPU time 1624.23 seconds
Started Jan 21 02:05:35 PM PST 24
Finished Jan 21 02:32:40 PM PST 24
Peak memory 398368 kb
Host smart-8ed7827a-4f32-4923-a02c-74c57fe362d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3831265736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3831265736 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.368901889
Short name T348
Test name
Test status
Simulation time 340285370889 ps
CPU time 1834.88 seconds
Started Jan 21 02:05:34 PM PST 24
Finished Jan 21 02:36:10 PM PST 24
Peak memory 368784 kb
Host smart-5782cb6d-94cc-4e09-9235-5bf741c49e08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=368901889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.368901889 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.1384852596
Short name T297
Test name
Test status
Simulation time 174316809371 ps
CPU time 1370.01 seconds
Started Jan 21 02:05:33 PM PST 24
Finished Jan 21 02:28:24 PM PST 24
Peak memory 335456 kb
Host smart-0cd3d5e7-9297-4129-ae82-69f5d2e34654
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1384852596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1384852596 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.908428238
Short name T1032
Test name
Test status
Simulation time 50440599282 ps
CPU time 943.78 seconds
Started Jan 21 02:05:39 PM PST 24
Finished Jan 21 02:21:23 PM PST 24
Peak memory 292940 kb
Host smart-eeb4c6dc-a181-44b9-ab50-b3bf710dee69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=908428238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.908428238 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.516114759
Short name T548
Test name
Test status
Simulation time 1084691199629 ps
CPU time 5241 seconds
Started Jan 21 02:05:46 PM PST 24
Finished Jan 21 03:33:09 PM PST 24
Peak memory 663660 kb
Host smart-0d3a4c50-e9a8-4b2a-b7de-0677c2b78ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=516114759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.516114759 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.1532273421
Short name T1089
Test name
Test status
Simulation time 45477819930 ps
CPU time 3505.85 seconds
Started Jan 21 02:29:04 PM PST 24
Finished Jan 21 03:27:32 PM PST 24
Peak memory 560212 kb
Host smart-c9b62622-4679-4595-8dea-559a826eb771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1532273421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.1532273421 +enable_masking=0 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/35.kmac_alert_test.2042654540
Short name T261
Test name
Test status
Simulation time 201409176 ps
CPU time 0.82 seconds
Started Jan 21 02:27:19 PM PST 24
Finished Jan 21 02:27:21 PM PST 24
Peak memory 207296 kb
Host smart-cb1cc919-c16e-447f-896d-ae5eb4440760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042654540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2042654540 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest


Test location /workspace/coverage/default/35.kmac_app.1610575866
Short name T296
Test name
Test status
Simulation time 61220374507 ps
CPU time 280.35 seconds
Started Jan 21 02:06:39 PM PST 24
Finished Jan 21 02:11:21 PM PST 24
Peak memory 241060 kb
Host smart-18a44d5e-b0fe-4628-a617-3556b678cc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610575866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1610575866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest


Test location /workspace/coverage/default/35.kmac_burst_write.4179760239
Short name T587
Test name
Test status
Simulation time 30119752085 ps
CPU time 736.08 seconds
Started Jan 21 02:06:22 PM PST 24
Finished Jan 21 02:18:40 PM PST 24
Peak memory 232784 kb
Host smart-c52ecf61-16eb-426a-be91-7b975734dabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179760239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.4179760239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest


Test location /workspace/coverage/default/35.kmac_entropy_refresh.3123377944
Short name T281
Test name
Test status
Simulation time 9308805365 ps
CPU time 168.22 seconds
Started Jan 21 02:21:26 PM PST 24
Finished Jan 21 02:24:15 PM PST 24
Peak memory 236756 kb
Host smart-81880855-a8bc-4a9a-a77a-93755c0ba97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123377944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3123377944 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/35.kmac_error.2499258585
Short name T476
Test name
Test status
Simulation time 2848467748 ps
CPU time 108.23 seconds
Started Jan 21 02:06:56 PM PST 24
Finished Jan 21 02:08:53 PM PST 24
Peak memory 240380 kb
Host smart-38a11861-87ad-46f4-87a7-f8e2d8284aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499258585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2499258585 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest


Test location /workspace/coverage/default/35.kmac_key_error.867949216
Short name T26
Test name
Test status
Simulation time 2905737539 ps
CPU time 3.79 seconds
Started Jan 21 02:06:52 PM PST 24
Finished Jan 21 02:06:59 PM PST 24
Peak memory 207592 kb
Host smart-b20b7818-f7a6-48e2-8449-729578e1ec3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867949216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.867949216 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest


Test location /workspace/coverage/default/35.kmac_lc_escalation.2570455458
Short name T328
Test name
Test status
Simulation time 52594748 ps
CPU time 1.28 seconds
Started Jan 21 02:06:51 PM PST 24
Finished Jan 21 02:06:55 PM PST 24
Peak memory 215964 kb
Host smart-7f7c0c12-bcb4-4bea-9ad7-f7106f635e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570455458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2570455458 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest


Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2195984845
Short name T797
Test name
Test status
Simulation time 106188242844 ps
CPU time 2203.99 seconds
Started Jan 21 02:06:13 PM PST 24
Finished Jan 21 02:42:58 PM PST 24
Peak memory 462096 kb
Host smart-9bc69776-2fd5-4179-9891-e886ec4af708
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195984845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2195984845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/35.kmac_sideload.2951919063
Short name T678
Test name
Test status
Simulation time 1550462210 ps
CPU time 111.07 seconds
Started Jan 21 02:06:22 PM PST 24
Finished Jan 21 02:08:15 PM PST 24
Peak memory 228988 kb
Host smart-a2472f8c-e0db-4113-a003-4fbeac4c85d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951919063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2951919063 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest


Test location /workspace/coverage/default/35.kmac_smoke.3788057730
Short name T884
Test name
Test status
Simulation time 7335918646 ps
CPU time 38.99 seconds
Started Jan 21 02:06:12 PM PST 24
Finished Jan 21 02:06:52 PM PST 24
Peak memory 218940 kb
Host smart-8d64506e-205c-4a9d-8cb1-bde041e77f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788057730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3788057730 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest


Test location /workspace/coverage/default/35.kmac_stress_all.3023766015
Short name T410
Test name
Test status
Simulation time 7142894287 ps
CPU time 589.03 seconds
Started Jan 21 02:06:51 PM PST 24
Finished Jan 21 02:16:42 PM PST 24
Peak memory 289604 kb
Host smart-9732509d-497d-4419-8ec0-d4ae67079baa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3023766015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3023766015 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest


Test location /workspace/coverage/default/35.kmac_stress_all_with_rand_reset.1262564258
Short name T939
Test name
Test status
Simulation time 49855327371 ps
CPU time 924.44 seconds
Started Jan 21 02:07:05 PM PST 24
Finished Jan 21 02:22:44 PM PST 24
Peak memory 298012 kb
Host smart-d94de4e7-f8c9-4901-9ea4-b4949c6ed691
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262564258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all_with_rand_reset.1262564258 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3777260731
Short name T1125
Test name
Test status
Simulation time 254851062 ps
CPU time 4.21 seconds
Started Jan 21 02:29:18 PM PST 24
Finished Jan 21 02:29:23 PM PST 24
Peak memory 217300 kb
Host smart-2a9737e4-527a-4b60-9880-e0f54b31a4db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777260731 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3777260731 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1345804473
Short name T1113
Test name
Test status
Simulation time 330444845 ps
CPU time 4.83 seconds
Started Jan 21 02:28:22 PM PST 24
Finished Jan 21 02:28:27 PM PST 24
Peak memory 208952 kb
Host smart-43bc998f-c532-4aa2-b15d-6f0a2c33f18c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345804473 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1345804473 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2294615293
Short name T895
Test name
Test status
Simulation time 65862143043 ps
CPU time 1828.9 seconds
Started Jan 21 02:06:23 PM PST 24
Finished Jan 21 02:36:53 PM PST 24
Peak memory 397496 kb
Host smart-83631d49-929e-4fde-a360-23251d313405
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2294615293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2294615293 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.4166475318
Short name T360
Test name
Test status
Simulation time 318692386537 ps
CPU time 1795.07 seconds
Started Jan 21 02:21:16 PM PST 24
Finished Jan 21 02:51:17 PM PST 24
Peak memory 370728 kb
Host smart-2d5a89eb-3f32-457a-912f-7a15944ef6be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4166475318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.4166475318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3306844134
Short name T960
Test name
Test status
Simulation time 14536811569 ps
CPU time 1171.88 seconds
Started Jan 21 02:06:21 PM PST 24
Finished Jan 21 02:25:54 PM PST 24
Peak memory 334476 kb
Host smart-3f2aa14c-601e-474e-918f-84f630e01a68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3306844134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3306844134 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.791191698
Short name T179
Test name
Test status
Simulation time 37087387942 ps
CPU time 742.23 seconds
Started Jan 21 02:26:04 PM PST 24
Finished Jan 21 02:38:27 PM PST 24
Peak memory 289908 kb
Host smart-5a6b9755-f031-44e2-b8ba-4360fd05034b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=791191698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.791191698 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.4109122348
Short name T610
Test name
Test status
Simulation time 178829722837 ps
CPU time 4699.98 seconds
Started Jan 21 02:32:50 PM PST 24
Finished Jan 21 03:51:12 PM PST 24
Peak memory 647024 kb
Host smart-67874a53-f645-4cab-8302-6ff7bd501166
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4109122348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.4109122348 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.1971709258
Short name T375
Test name
Test status
Simulation time 156937416136 ps
CPU time 3415 seconds
Started Jan 21 02:24:47 PM PST 24
Finished Jan 21 03:21:43 PM PST 24
Peak memory 542836 kb
Host smart-287d378f-0247-4efb-b15d-00a9ee4a2d48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1971709258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.1971709258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/36.kmac_alert_test.293524722
Short name T184
Test name
Test status
Simulation time 13494578 ps
CPU time 0.75 seconds
Started Jan 21 02:07:50 PM PST 24
Finished Jan 21 02:07:53 PM PST 24
Peak memory 207560 kb
Host smart-32392b24-4fef-4c9b-a28c-39e6f7a81904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293524722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.293524722 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest


Test location /workspace/coverage/default/36.kmac_app.2424853650
Short name T1041
Test name
Test status
Simulation time 7625949326 ps
CPU time 225 seconds
Started Jan 21 02:07:31 PM PST 24
Finished Jan 21 02:11:22 PM PST 24
Peak memory 243120 kb
Host smart-4a7371a6-7f3d-4715-9eb0-47d96f9e16e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424853650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2424853650 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest


Test location /workspace/coverage/default/36.kmac_burst_write.807347518
Short name T600
Test name
Test status
Simulation time 61124704812 ps
CPU time 623.79 seconds
Started Jan 21 02:07:11 PM PST 24
Finished Jan 21 02:17:47 PM PST 24
Peak memory 228784 kb
Host smart-5d8fc47b-5f62-455f-82a9-32620677e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807347518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.807347518 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest


Test location /workspace/coverage/default/36.kmac_entropy_refresh.1534922502
Short name T462
Test name
Test status
Simulation time 7311758151 ps
CPU time 143.28 seconds
Started Jan 21 02:07:41 PM PST 24
Finished Jan 21 02:10:06 PM PST 24
Peak memory 237156 kb
Host smart-e71f149b-bf21-4ee4-a42a-9663aae88eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534922502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1534922502 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/36.kmac_error.3788529338
Short name T999
Test name
Test status
Simulation time 24119593212 ps
CPU time 126.77 seconds
Started Jan 21 02:07:41 PM PST 24
Finished Jan 21 02:09:49 PM PST 24
Peak memory 234828 kb
Host smart-628ef1cc-5d55-4dc1-8a2a-2983e95c8dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788529338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3788529338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest


Test location /workspace/coverage/default/36.kmac_key_error.3722808152
Short name T420
Test name
Test status
Simulation time 919151281 ps
CPU time 1.93 seconds
Started Jan 21 02:07:41 PM PST 24
Finished Jan 21 02:07:44 PM PST 24
Peak memory 207504 kb
Host smart-41fc7d67-2819-43af-9262-caa8dae61eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722808152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3722808152 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest


Test location /workspace/coverage/default/36.kmac_lc_escalation.3222844895
Short name T770
Test name
Test status
Simulation time 94770392 ps
CPU time 1.33 seconds
Started Jan 21 02:07:48 PM PST 24
Finished Jan 21 02:07:51 PM PST 24
Peak memory 220716 kb
Host smart-41892061-a1d1-4cb4-9dc8-4eb0109f704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222844895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3222844895 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest


Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2457222190
Short name T526
Test name
Test status
Simulation time 27622010824 ps
CPU time 1250.47 seconds
Started Jan 21 02:07:02 PM PST 24
Finished Jan 21 02:28:04 PM PST 24
Peak memory 351112 kb
Host smart-a3d740d7-8657-41ea-b7a2-367ea251c577
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457222190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2457222190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/36.kmac_sideload.86883176
Short name T369
Test name
Test status
Simulation time 7255663381 ps
CPU time 193.97 seconds
Started Jan 21 02:24:50 PM PST 24
Finished Jan 21 02:28:04 PM PST 24
Peak memory 237060 kb
Host smart-49b49d0b-d166-4a94-9a0d-142427cb37d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86883176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.86883176 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest


Test location /workspace/coverage/default/36.kmac_smoke.805528400
Short name T1073
Test name
Test status
Simulation time 23110442229 ps
CPU time 35.95 seconds
Started Jan 21 02:07:05 PM PST 24
Finished Jan 21 02:07:56 PM PST 24
Peak memory 219012 kb
Host smart-deb2c09a-c3b8-4171-a078-9cdc105fa892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805528400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.805528400 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest


Test location /workspace/coverage/default/36.kmac_stress_all.3421827079
Short name T942
Test name
Test status
Simulation time 301084589292 ps
CPU time 2181.46 seconds
Started Jan 21 02:07:40 PM PST 24
Finished Jan 21 02:44:03 PM PST 24
Peak memory 467896 kb
Host smart-416b7e1b-129a-4ede-a5ff-b0985d620a0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3421827079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3421827079 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest


Test location /workspace/coverage/default/36.kmac_stress_all_with_rand_reset.891815731
Short name T1092
Test name
Test status
Simulation time 189771624470 ps
CPU time 1000.71 seconds
Started Jan 21 02:07:55 PM PST 24
Finished Jan 21 02:24:37 PM PST 24
Peak memory 335548 kb
Host smart-feac0756-f545-4a93-b7d2-1c3866f502ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891815731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.891815731 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.1242811659
Short name T1014
Test name
Test status
Simulation time 392824122 ps
CPU time 4.1 seconds
Started Jan 21 02:07:29 PM PST 24
Finished Jan 21 02:07:41 PM PST 24
Peak memory 217080 kb
Host smart-1660e036-5dd5-49e1-9e7c-870daa8c0f48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242811659 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.1242811659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.967124885
Short name T893
Test name
Test status
Simulation time 345025921 ps
CPU time 4.65 seconds
Started Jan 21 02:25:29 PM PST 24
Finished Jan 21 02:25:36 PM PST 24
Peak memory 217160 kb
Host smart-d76069b1-9d29-4734-b899-f27e9d1a764b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967124885 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.967124885 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.1867473387
Short name T951
Test name
Test status
Simulation time 267109733966 ps
CPU time 1866.77 seconds
Started Jan 21 02:07:25 PM PST 24
Finished Jan 21 02:38:33 PM PST 24
Peak memory 387084 kb
Host smart-70eaa37a-7d6a-4783-b5e3-67be7b636c42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1867473387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1867473387 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.1823584096
Short name T703
Test name
Test status
Simulation time 71434351109 ps
CPU time 1518.87 seconds
Started Jan 21 02:07:23 PM PST 24
Finished Jan 21 02:32:44 PM PST 24
Peak memory 376088 kb
Host smart-6acba595-5546-49ef-b95d-54de5d93a16f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1823584096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.1823584096 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.3738643997
Short name T1095
Test name
Test status
Simulation time 149488819459 ps
CPU time 1149.69 seconds
Started Jan 21 02:07:31 PM PST 24
Finished Jan 21 02:26:47 PM PST 24
Peak memory 331300 kb
Host smart-9c03350c-20c4-4cff-aeb2-1cfef9d37b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3738643997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.3738643997 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.4125507816
Short name T304
Test name
Test status
Simulation time 250435811544 ps
CPU time 945.92 seconds
Started Jan 21 02:07:30 PM PST 24
Finished Jan 21 02:23:23 PM PST 24
Peak memory 294224 kb
Host smart-dc5a3864-cf0e-44bd-86e7-b006aaa16181
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4125507816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.4125507816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.1780727316
Short name T524
Test name
Test status
Simulation time 190063765075 ps
CPU time 4230.06 seconds
Started Jan 21 03:17:10 PM PST 24
Finished Jan 21 04:27:42 PM PST 24
Peak memory 658696 kb
Host smart-9dd5708b-f9da-487f-a893-c11d5101de2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1780727316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1780727316 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.4144548258
Short name T1062
Test name
Test status
Simulation time 843110914190 ps
CPU time 4522.65 seconds
Started Jan 21 02:07:31 PM PST 24
Finished Jan 21 03:23:00 PM PST 24
Peak memory 570692 kb
Host smart-c79c8f61-106e-404a-99b2-f9f100dd7204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4144548258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.4144548258 +enable_masking=0 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/37.kmac_alert_test.1898389752
Short name T237
Test name
Test status
Simulation time 50150329 ps
CPU time 0.78 seconds
Started Jan 21 02:31:17 PM PST 24
Finished Jan 21 02:31:18 PM PST 24
Peak memory 207204 kb
Host smart-5aff7604-8eb9-4765-8ea8-e83f5d0933d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898389752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1898389752 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest


Test location /workspace/coverage/default/37.kmac_app.564270801
Short name T373
Test name
Test status
Simulation time 175617818437 ps
CPU time 186.95 seconds
Started Jan 21 02:08:30 PM PST 24
Finished Jan 21 02:11:38 PM PST 24
Peak memory 236144 kb
Host smart-0221146a-6cec-49a7-a96a-61ed5b96e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564270801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.564270801 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest


Test location /workspace/coverage/default/37.kmac_burst_write.3226604323
Short name T189
Test name
Test status
Simulation time 7479632486 ps
CPU time 181.02 seconds
Started Jan 21 02:36:43 PM PST 24
Finished Jan 21 02:39:45 PM PST 24
Peak memory 223804 kb
Host smart-3671d793-e0fb-48d9-ba90-cb70ab9a2fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226604323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3226604323 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest


Test location /workspace/coverage/default/37.kmac_entropy_refresh.723412542
Short name T1115
Test name
Test status
Simulation time 7390530783 ps
CPU time 78.69 seconds
Started Jan 21 02:27:43 PM PST 24
Finished Jan 21 02:29:02 PM PST 24
Peak memory 227704 kb
Host smart-b1fe5762-4d81-4def-b848-d73dc54a4f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723412542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.723412542 +enable_masking=0 +sw
_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/37.kmac_error.3988754965
Short name T1048
Test name
Test status
Simulation time 5493904564 ps
CPU time 103.68 seconds
Started Jan 21 02:08:30 PM PST 24
Finished Jan 21 02:10:15 PM PST 24
Peak memory 239196 kb
Host smart-e15e684e-c224-47cc-acd5-5e869143ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988754965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3988754965 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest


Test location /workspace/coverage/default/37.kmac_key_error.3179361328
Short name T336
Test name
Test status
Simulation time 764695352 ps
CPU time 1.42 seconds
Started Jan 21 02:08:30 PM PST 24
Finished Jan 21 02:08:33 PM PST 24
Peak memory 207296 kb
Host smart-b7dd1c9b-4756-45b3-ac78-616953b32606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179361328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3179361328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest


Test location /workspace/coverage/default/37.kmac_lc_escalation.1776247281
Short name T744
Test name
Test status
Simulation time 442430075 ps
CPU time 5.09 seconds
Started Jan 21 02:08:39 PM PST 24
Finished Jan 21 02:08:45 PM PST 24
Peak memory 216108 kb
Host smart-738c2823-0460-4a7a-a39b-66f564f9c3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776247281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1776247281 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest


Test location /workspace/coverage/default/37.kmac_long_msg_and_output.538367318
Short name T534
Test name
Test status
Simulation time 78648984646 ps
CPU time 2518.07 seconds
Started Jan 21 02:07:50 PM PST 24
Finished Jan 21 02:49:50 PM PST 24
Peak memory 452604 kb
Host smart-e56b9587-68ad-48b1-9f5a-5978bc83d429
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538367318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an
d_output.538367318 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/37.kmac_sideload.351604006
Short name T589
Test name
Test status
Simulation time 197356133669 ps
CPU time 298.05 seconds
Started Jan 21 02:32:52 PM PST 24
Finished Jan 21 02:37:50 PM PST 24
Peak memory 241628 kb
Host smart-46a57f7c-0978-43c0-8db9-5f6d09fb9a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351604006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.351604006 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest


Test location /workspace/coverage/default/37.kmac_smoke.1249465880
Short name T272
Test name
Test status
Simulation time 1836418561 ps
CPU time 40.8 seconds
Started Jan 21 02:07:57 PM PST 24
Finished Jan 21 02:08:39 PM PST 24
Peak memory 218264 kb
Host smart-837521b2-d3bf-4efa-abdd-012a181f4ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249465880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1249465880 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest


Test location /workspace/coverage/default/37.kmac_stress_all.2018100003
Short name T966
Test name
Test status
Simulation time 51479133835 ps
CPU time 1310.23 seconds
Started Jan 21 02:08:40 PM PST 24
Finished Jan 21 02:30:31 PM PST 24
Peak memory 389688 kb
Host smart-3f147a28-346b-420f-a896-bb6e664350bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2018100003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2018100003 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest


Test location /workspace/coverage/default/37.kmac_stress_all_with_rand_reset.429860092
Short name T913
Test name
Test status
Simulation time 29027709337 ps
CPU time 547.32 seconds
Started Jan 21 02:32:48 PM PST 24
Finished Jan 21 02:41:56 PM PST 24
Peak memory 281644 kb
Host smart-c8dc5aa8-05a1-4b49-939e-a0a1451f80c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429860092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all_with_rand_reset.429860092 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1402591199
Short name T1145
Test name
Test status
Simulation time 744589585 ps
CPU time 4.94 seconds
Started Jan 21 02:08:31 PM PST 24
Finished Jan 21 02:08:36 PM PST 24
Peak memory 217048 kb
Host smart-c93458db-9e39-4a51-be73-94e695640a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402591199 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1402591199 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.3004539319
Short name T333
Test name
Test status
Simulation time 913320771 ps
CPU time 4.69 seconds
Started Jan 21 02:08:32 PM PST 24
Finished Jan 21 02:08:38 PM PST 24
Peak memory 216720 kb
Host smart-64863db6-11fe-4312-803a-5f34c6853d4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004539319 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.3004539319 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.3480746787
Short name T362
Test name
Test status
Simulation time 100992564014 ps
CPU time 1993.39 seconds
Started Jan 21 02:28:53 PM PST 24
Finished Jan 21 03:02:08 PM PST 24
Peak memory 391428 kb
Host smart-1545fbc3-475c-4982-926e-1708ccdb0dbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3480746787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.3480746787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.692472278
Short name T633
Test name
Test status
Simulation time 61269951172 ps
CPU time 1717.97 seconds
Started Jan 21 02:36:45 PM PST 24
Finished Jan 21 03:05:24 PM PST 24
Peak memory 370940 kb
Host smart-f52e6844-e7db-44a1-a32d-e9b49b9082e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=692472278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.692472278 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.1515005093
Short name T803
Test name
Test status
Simulation time 54297731460 ps
CPU time 1144.43 seconds
Started Jan 21 02:12:57 PM PST 24
Finished Jan 21 02:32:02 PM PST 24
Peak memory 332980 kb
Host smart-5d1a3c7a-1e89-4354-bdfb-a2ecedeeec71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1515005093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.1515005093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.1230567137
Short name T790
Test name
Test status
Simulation time 43542537102 ps
CPU time 835.6 seconds
Started Jan 21 02:08:19 PM PST 24
Finished Jan 21 02:22:16 PM PST 24
Peak memory 296052 kb
Host smart-499d7199-4b26-44f7-a31e-2c841763b3f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1230567137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.1230567137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.2669766774
Short name T506
Test name
Test status
Simulation time 50404317904 ps
CPU time 3935.63 seconds
Started Jan 21 02:08:31 PM PST 24
Finished Jan 21 03:14:08 PM PST 24
Peak memory 639936 kb
Host smart-a1b52deb-f3d4-4e9c-84c0-71ecc9fe7458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2669766774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.2669766774 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.2894290799
Short name T214
Test name
Test status
Simulation time 112641347277 ps
CPU time 3350.83 seconds
Started Jan 21 02:25:38 PM PST 24
Finished Jan 21 03:21:30 PM PST 24
Peak memory 551372 kb
Host smart-81b1d475-a692-486a-abd6-22a677d047cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2894290799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2894290799 +enable_masking=0 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/38.kmac_alert_test.4294416447
Short name T396
Test name
Test status
Simulation time 15264361 ps
CPU time 0.77 seconds
Started Jan 21 02:09:38 PM PST 24
Finished Jan 21 02:09:43 PM PST 24
Peak memory 207260 kb
Host smart-9a16c9b9-9cd5-4180-9caa-3791fcdff895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294416447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.4294416447 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest


Test location /workspace/coverage/default/38.kmac_app.230163234
Short name T606
Test name
Test status
Simulation time 29914054410 ps
CPU time 142.44 seconds
Started Jan 21 02:09:20 PM PST 24
Finished Jan 21 02:11:44 PM PST 24
Peak memory 232336 kb
Host smart-10b0395d-6934-4919-8580-eaaf272e7e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230163234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.230163234 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest


Test location /workspace/coverage/default/38.kmac_burst_write.1978094994
Short name T707
Test name
Test status
Simulation time 4581364986 ps
CPU time 141.96 seconds
Started Jan 21 02:31:06 PM PST 24
Finished Jan 21 02:33:29 PM PST 24
Peak memory 223908 kb
Host smart-1982a80a-519a-41fe-b2fd-222f3fddb838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978094994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1978094994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest


Test location /workspace/coverage/default/38.kmac_entropy_refresh.1638646034
Short name T305
Test name
Test status
Simulation time 17949433695 ps
CPU time 116.27 seconds
Started Jan 21 02:09:34 PM PST 24
Finished Jan 21 02:11:35 PM PST 24
Peak memory 231400 kb
Host smart-9843cc6c-182a-4614-869a-d1749afa9cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638646034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1638646034 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/38.kmac_key_error.2117717818
Short name T836
Test name
Test status
Simulation time 7019819598 ps
CPU time 6.15 seconds
Started Jan 21 02:09:30 PM PST 24
Finished Jan 21 02:09:37 PM PST 24
Peak memory 207608 kb
Host smart-a8c20bb1-acc9-4d14-9ab7-c0d50f62f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117717818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2117717818 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest


Test location /workspace/coverage/default/38.kmac_lc_escalation.595807356
Short name T861
Test name
Test status
Simulation time 999017975 ps
CPU time 11.95 seconds
Started Jan 21 02:09:30 PM PST 24
Finished Jan 21 02:09:43 PM PST 24
Peak memory 223092 kb
Host smart-5f0dd00c-4352-4bf1-8b9b-11066a4ed7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595807356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.595807356 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest


Test location /workspace/coverage/default/38.kmac_long_msg_and_output.147743888
Short name T298
Test name
Test status
Simulation time 5243269409 ps
CPU time 73.6 seconds
Started Jan 21 02:08:50 PM PST 24
Finished Jan 21 02:10:05 PM PST 24
Peak memory 224388 kb
Host smart-d65afdaf-3da2-46cf-a483-8e225cb5aeb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147743888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an
d_output.147743888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/38.kmac_sideload.667991581
Short name T1088
Test name
Test status
Simulation time 3860881247 ps
CPU time 146.39 seconds
Started Jan 21 02:08:48 PM PST 24
Finished Jan 21 02:11:15 PM PST 24
Peak memory 233700 kb
Host smart-43dbc39f-9439-43cf-aba7-89b73e818c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667991581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.667991581 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest


Test location /workspace/coverage/default/38.kmac_smoke.1955171470
Short name T638
Test name
Test status
Simulation time 2187882094 ps
CPU time 11.17 seconds
Started Jan 21 02:08:41 PM PST 24
Finished Jan 21 02:08:53 PM PST 24
Peak memory 217404 kb
Host smart-233921a5-9345-49f4-8612-c6aff2b4da7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955171470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1955171470 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest


Test location /workspace/coverage/default/38.kmac_stress_all.2660799292
Short name T1107
Test name
Test status
Simulation time 12701171855 ps
CPU time 795.2 seconds
Started Jan 21 02:09:33 PM PST 24
Finished Jan 21 02:22:49 PM PST 24
Peak memory 329828 kb
Host smart-9629fd8b-9d72-41a9-867b-05d35b050041
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2660799292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2660799292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest


Test location /workspace/coverage/default/38.kmac_stress_all_with_rand_reset.1992604878
Short name T622
Test name
Test status
Simulation time 36398664977 ps
CPU time 581.08 seconds
Started Jan 21 02:09:32 PM PST 24
Finished Jan 21 02:19:15 PM PST 24
Peak memory 279536 kb
Host smart-ea74be05-aabd-473c-a8b5-b8a95fb1e912
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992604878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.1992604878 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.959611425
Short name T196
Test name
Test status
Simulation time 232986422 ps
CPU time 4 seconds
Started Jan 21 02:09:22 PM PST 24
Finished Jan 21 02:09:27 PM PST 24
Peak memory 217140 kb
Host smart-875c6a51-4606-419f-bc17-1f67fd704374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959611425 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.kmac_test_vectors_kmac.959611425 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.1940788071
Short name T4
Test name
Test status
Simulation time 936023282 ps
CPU time 4.51 seconds
Started Jan 21 02:09:19 PM PST 24
Finished Jan 21 02:09:25 PM PST 24
Peak memory 217200 kb
Host smart-dd852469-c67e-4e1d-bcbd-340600a3bc9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940788071 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.1940788071 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.3937428456
Short name T558
Test name
Test status
Simulation time 133519366483 ps
CPU time 1836.13 seconds
Started Jan 21 02:08:48 PM PST 24
Finished Jan 21 02:39:25 PM PST 24
Peak memory 395160 kb
Host smart-d1eeef07-8a33-4d94-bfae-32ac19ea28ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3937428456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.3937428456 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.3850075450
Short name T249
Test name
Test status
Simulation time 274330034337 ps
CPU time 1730.84 seconds
Started Jan 21 02:31:51 PM PST 24
Finished Jan 21 03:00:43 PM PST 24
Peak memory 369328 kb
Host smart-5415b785-9622-44b8-adc9-fe777219cb76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3850075450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.3850075450 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.1525677265
Short name T1054
Test name
Test status
Simulation time 26307113075 ps
CPU time 1123.2 seconds
Started Jan 21 02:09:10 PM PST 24
Finished Jan 21 02:27:54 PM PST 24
Peak memory 335768 kb
Host smart-e0618870-77d8-47fa-9ba7-cecfda475bf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1525677265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1525677265 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.101687130
Short name T1058
Test name
Test status
Simulation time 40220945826 ps
CPU time 844.48 seconds
Started Jan 21 02:09:10 PM PST 24
Finished Jan 21 02:23:16 PM PST 24
Peak memory 297684 kb
Host smart-e0f49202-d80d-4462-812b-2164836ffab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=101687130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.101687130 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.228985496
Short name T609
Test name
Test status
Simulation time 180753370277 ps
CPU time 4648.18 seconds
Started Jan 21 02:09:10 PM PST 24
Finished Jan 21 03:26:40 PM PST 24
Peak memory 648440 kb
Host smart-1f40a2a3-566d-4cd4-9635-1a2da91bec04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=228985496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.228985496 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1956640623
Short name T1051
Test name
Test status
Simulation time 457110210768 ps
CPU time 4459.11 seconds
Started Jan 21 02:26:44 PM PST 24
Finished Jan 21 03:41:04 PM PST 24
Peak memory 570596 kb
Host smart-3f5a31ca-c06d-4759-830b-46198cf47e27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1956640623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1956640623 +enable_masking=0 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/39.kmac_alert_test.1159508925
Short name T1047
Test name
Test status
Simulation time 15513586 ps
CPU time 0.78 seconds
Started Jan 21 02:10:38 PM PST 24
Finished Jan 21 02:10:42 PM PST 24
Peak memory 207256 kb
Host smart-9cf6b234-c0c8-4167-8a58-4dfa1570659a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159508925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1159508925 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest


Test location /workspace/coverage/default/39.kmac_app.3936643962
Short name T671
Test name
Test status
Simulation time 2971938839 ps
CPU time 66.64 seconds
Started Jan 21 02:10:21 PM PST 24
Finished Jan 21 02:11:28 PM PST 24
Peak memory 226252 kb
Host smart-dec44923-91aa-4407-a152-2ec1a88f4bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936643962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3936643962 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest


Test location /workspace/coverage/default/39.kmac_burst_write.1010517256
Short name T1122
Test name
Test status
Simulation time 4998937257 ps
CPU time 420.57 seconds
Started Jan 21 02:29:14 PM PST 24
Finished Jan 21 02:36:15 PM PST 24
Peak memory 228680 kb
Host smart-2af84c5d-bd72-4c10-9472-628998dfad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010517256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1010517256 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest


Test location /workspace/coverage/default/39.kmac_entropy_refresh.2989725596
Short name T1045
Test name
Test status
Simulation time 7223322009 ps
CPU time 113.64 seconds
Started Jan 21 02:10:22 PM PST 24
Finished Jan 21 02:12:17 PM PST 24
Peak memory 229752 kb
Host smart-182a063d-3af2-4d30-8eb8-fd03047445b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989725596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2989725596 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/39.kmac_error.133967259
Short name T1057
Test name
Test status
Simulation time 12247937755 ps
CPU time 238.49 seconds
Started Jan 21 02:10:21 PM PST 24
Finished Jan 21 02:14:20 PM PST 24
Peak memory 248496 kb
Host smart-da5ef721-7ef0-4910-95b4-38ff81ea1263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133967259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.133967259 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest


Test location /workspace/coverage/default/39.kmac_key_error.1880532649
Short name T62
Test name
Test status
Simulation time 99298024 ps
CPU time 1.16 seconds
Started Jan 21 02:10:26 PM PST 24
Finished Jan 21 02:10:28 PM PST 24
Peak memory 207220 kb
Host smart-4319dcfb-6241-4171-b150-c4e4eab60cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880532649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1880532649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest


Test location /workspace/coverage/default/39.kmac_lc_escalation.2247524999
Short name T711
Test name
Test status
Simulation time 40800201 ps
CPU time 1.3 seconds
Started Jan 21 02:10:26 PM PST 24
Finished Jan 21 02:10:28 PM PST 24
Peak memory 215940 kb
Host smart-c8c8b7be-e628-4032-8581-08af0f1d9bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247524999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2247524999 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest


Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3792260239
Short name T1024
Test name
Test status
Simulation time 115159241943 ps
CPU time 1489.49 seconds
Started Jan 21 02:09:37 PM PST 24
Finished Jan 21 02:34:32 PM PST 24
Peak memory 377776 kb
Host smart-d193373c-036b-4318-838c-fad0da0281e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792260239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3792260239 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/39.kmac_sideload.2674698132
Short name T955
Test name
Test status
Simulation time 24871641985 ps
CPU time 191.29 seconds
Started Jan 21 02:09:37 PM PST 24
Finished Jan 21 02:12:54 PM PST 24
Peak memory 234748 kb
Host smart-ff562b9c-248d-4cc9-8468-78deda595e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674698132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2674698132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest


Test location /workspace/coverage/default/39.kmac_smoke.3994304054
Short name T275
Test name
Test status
Simulation time 23541666433 ps
CPU time 50.16 seconds
Started Jan 21 02:09:37 PM PST 24
Finished Jan 21 02:10:33 PM PST 24
Peak memory 219124 kb
Host smart-f29126d7-47c5-4c80-982c-f945089f2eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994304054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3994304054 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest


Test location /workspace/coverage/default/39.kmac_stress_all.2893784462
Short name T37
Test name
Test status
Simulation time 22116627402 ps
CPU time 269.53 seconds
Started Jan 21 02:10:34 PM PST 24
Finished Jan 21 02:15:09 PM PST 24
Peak memory 283352 kb
Host smart-775149c3-e1b5-4b7b-abd2-28aba34ee5e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2893784462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2893784462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest


Test location /workspace/coverage/default/39.kmac_stress_all_with_rand_reset.3042377103
Short name T309
Test name
Test status
Simulation time 226946382743 ps
CPU time 1352.27 seconds
Started Jan 21 02:10:34 PM PST 24
Finished Jan 21 02:33:12 PM PST 24
Peak memory 330668 kb
Host smart-d4b4cb26-9f2d-430b-937c-71069836a0ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042377103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all_with_rand_reset.3042377103 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.1994436516
Short name T489
Test name
Test status
Simulation time 251344571 ps
CPU time 4.94 seconds
Started Jan 21 02:09:57 PM PST 24
Finished Jan 21 02:10:03 PM PST 24
Peak memory 208448 kb
Host smart-8226c4ea-31b0-4125-b082-5775c21c7c73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994436516 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.1994436516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.2032420000
Short name T1143
Test name
Test status
Simulation time 692774498 ps
CPU time 4.26 seconds
Started Jan 21 02:30:41 PM PST 24
Finished Jan 21 02:30:46 PM PST 24
Peak memory 208360 kb
Host smart-c6890451-9551-4b41-b5a9-59a0d49bea0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032420000 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.2032420000 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.809542434
Short name T206
Test name
Test status
Simulation time 66388367950 ps
CPU time 1797.88 seconds
Started Jan 21 02:09:37 PM PST 24
Finished Jan 21 02:39:40 PM PST 24
Peak memory 378132 kb
Host smart-9e17c049-1b77-4a44-9bf7-4fef33e10294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=809542434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.809542434 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.3037704384
Short name T263
Test name
Test status
Simulation time 61820384477 ps
CPU time 1698.01 seconds
Started Jan 21 02:09:46 PM PST 24
Finished Jan 21 02:38:10 PM PST 24
Peak memory 370228 kb
Host smart-521f24de-bf5f-473b-850d-b4b599a48387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3037704384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.3037704384 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.2084752877
Short name T180
Test name
Test status
Simulation time 14439779239 ps
CPU time 1123.65 seconds
Started Jan 21 02:09:49 PM PST 24
Finished Jan 21 02:28:37 PM PST 24
Peak memory 336420 kb
Host smart-0aac5a4a-3b5a-4fb7-9e38-8c72a3f59ffe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2084752877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2084752877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.1165385277
Short name T448
Test name
Test status
Simulation time 29306779548 ps
CPU time 831.17 seconds
Started Jan 21 02:36:39 PM PST 24
Finished Jan 21 02:50:31 PM PST 24
Peak memory 298312 kb
Host smart-114621e4-9b17-4b06-ba69-d7f8f8230e94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1165385277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1165385277 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.2494476002
Short name T424
Test name
Test status
Simulation time 104518622807 ps
CPU time 3918.91 seconds
Started Jan 21 02:09:46 PM PST 24
Finished Jan 21 03:15:12 PM PST 24
Peak memory 636240 kb
Host smart-31280653-222d-4f9f-ae50-9ef75a2c202f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2494476002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2494476002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1958937353
Short name T663
Test name
Test status
Simulation time 146408653812 ps
CPU time 4145.87 seconds
Started Jan 21 03:12:11 PM PST 24
Finished Jan 21 04:21:17 PM PST 24
Peak memory 559320 kb
Host smart-3a754b89-f14d-4cbd-a830-0a39f216a0bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1958937353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1958937353 +enable_masking=0 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/4.kmac_alert_test.2387723890
Short name T871
Test name
Test status
Simulation time 11059089 ps
CPU time 0.79 seconds
Started Jan 21 01:47:46 PM PST 24
Finished Jan 21 01:47:47 PM PST 24
Peak memory 207192 kb
Host smart-e40e2275-895d-48ed-aa71-1c6c7f8f06e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387723890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2387723890 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest


Test location /workspace/coverage/default/4.kmac_app.3015018511
Short name T469
Test name
Test status
Simulation time 8073053028 ps
CPU time 108.96 seconds
Started Jan 21 01:47:25 PM PST 24
Finished Jan 21 01:49:16 PM PST 24
Peak memory 231432 kb
Host smart-25a132e9-56db-4d37-9b2f-9ff5c1b650bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015018511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3015018511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest


Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3562744051
Short name T455
Test name
Test status
Simulation time 20661678783 ps
CPU time 91.73 seconds
Started Jan 21 01:47:34 PM PST 24
Finished Jan 21 01:49:09 PM PST 24
Peak memory 228168 kb
Host smart-5077dbfe-4160-4750-9f71-8f06624fdbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562744051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3562744051 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/4.kmac_burst_write.1238227267
Short name T390
Test name
Test status
Simulation time 21918214006 ps
CPU time 564.85 seconds
Started Jan 21 01:47:26 PM PST 24
Finished Jan 21 01:56:52 PM PST 24
Peak memory 229248 kb
Host smart-8437f86d-3b62-43c3-be19-8524dd09ccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238227267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1238227267 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest


Test location /workspace/coverage/default/4.kmac_edn_timeout_error.705977277
Short name T935
Test name
Test status
Simulation time 1554005756 ps
CPU time 29.68 seconds
Started Jan 21 01:47:35 PM PST 24
Finished Jan 21 01:48:07 PM PST 24
Peak memory 223576 kb
Host smart-759bb657-4564-46fc-9844-a4723b304c3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=705977277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.705977277 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/4.kmac_entropy_mode_error.1569397729
Short name T923
Test name
Test status
Simulation time 260921110 ps
CPU time 9.62 seconds
Started Jan 21 01:47:34 PM PST 24
Finished Jan 21 01:47:47 PM PST 24
Peak memory 220820 kb
Host smart-c1ec07a9-a618-481d-aca7-ed27b19ee983
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1569397729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1569397729 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1437936847
Short name T227
Test name
Test status
Simulation time 1332914223 ps
CPU time 11.99 seconds
Started Jan 21 01:47:46 PM PST 24
Finished Jan 21 01:47:59 PM PST 24
Peak memory 223428 kb
Host smart-6f4cfafb-5d46-4ba1-ac4b-491396bb34e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437936847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1437936847 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/4.kmac_entropy_refresh.445818179
Short name T522
Test name
Test status
Simulation time 6913182717 ps
CPU time 110.64 seconds
Started Jan 21 01:47:36 PM PST 24
Finished Jan 21 01:49:28 PM PST 24
Peak memory 229372 kb
Host smart-56df7d6f-b586-4d8a-a03f-793f1e088505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445818179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.445818179 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/4.kmac_error.3377981589
Short name T35
Test name
Test status
Simulation time 7181489341 ps
CPU time 138.36 seconds
Started Jan 21 02:00:45 PM PST 24
Finished Jan 21 02:03:05 PM PST 24
Peak memory 239884 kb
Host smart-eed152a0-88c2-4a7c-97d0-48c8c6a1763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377981589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3377981589 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest


Test location /workspace/coverage/default/4.kmac_key_error.2423402467
Short name T1137
Test name
Test status
Simulation time 1594933552 ps
CPU time 1.66 seconds
Started Jan 21 01:47:35 PM PST 24
Finished Jan 21 01:47:39 PM PST 24
Peak memory 207208 kb
Host smart-a7d5176a-e6e8-49b8-8402-10d06ef7c68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423402467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2423402467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest


Test location /workspace/coverage/default/4.kmac_lc_escalation.1996759852
Short name T646
Test name
Test status
Simulation time 73327924 ps
CPU time 1.24 seconds
Started Jan 21 02:05:38 PM PST 24
Finished Jan 21 02:05:40 PM PST 24
Peak memory 218528 kb
Host smart-a0c1a0e1-20c7-45e9-9812-caa13a76d166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996759852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1996759852 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest


Test location /workspace/coverage/default/4.kmac_long_msg_and_output.2613904184
Short name T211
Test name
Test status
Simulation time 21908674993 ps
CPU time 1799.66 seconds
Started Jan 21 01:47:20 PM PST 24
Finished Jan 21 02:17:21 PM PST 24
Peak memory 419784 kb
Host smart-fd09e3ca-ae9f-4a9f-a8a1-a69432429b62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613904184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.2613904184 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/4.kmac_mubi.2173222511
Short name T520
Test name
Test status
Simulation time 69546114943 ps
CPU time 342.21 seconds
Started Jan 21 03:04:04 PM PST 24
Finished Jan 21 03:09:51 PM PST 24
Peak memory 245832 kb
Host smart-b00ee120-7394-4c42-8e40-08db10494d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173222511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2173222511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest


Test location /workspace/coverage/default/4.kmac_sec_cm.1250777660
Short name T68
Test name
Test status
Simulation time 103097778530 ps
CPU time 64.23 seconds
Started Jan 21 01:47:44 PM PST 24
Finished Jan 21 01:48:49 PM PST 24
Peak memory 273264 kb
Host smart-31deba33-9dbd-4461-b06b-4d546b5d9997
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250777660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1250777660 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest


Test location /workspace/coverage/default/4.kmac_sideload.1807801851
Short name T762
Test name
Test status
Simulation time 15969343555 ps
CPU time 328.67 seconds
Started Jan 21 02:33:49 PM PST 24
Finished Jan 21 02:39:18 PM PST 24
Peak memory 241844 kb
Host smart-41a18740-601b-49db-a0c5-78b53cb7473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807801851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1807801851 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest


Test location /workspace/coverage/default/4.kmac_smoke.26662190
Short name T191
Test name
Test status
Simulation time 994043161 ps
CPU time 19.96 seconds
Started Jan 21 01:47:18 PM PST 24
Finished Jan 21 01:47:39 PM PST 24
Peak memory 217676 kb
Host smart-5f375eed-3a3e-413c-ae76-9fbbc57f77d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26662190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.26662190 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest


Test location /workspace/coverage/default/4.kmac_stress_all.1738263153
Short name T954
Test name
Test status
Simulation time 45750087099 ps
CPU time 916.17 seconds
Started Jan 21 01:47:47 PM PST 24
Finished Jan 21 02:03:04 PM PST 24
Peak memory 330472 kb
Host smart-7602ca3d-569a-4dbd-9a55-a77ab877efff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1738263153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1738263153 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.4099321478
Short name T1148
Test name
Test status
Simulation time 292681456 ps
CPU time 4.3 seconds
Started Jan 21 02:20:30 PM PST 24
Finished Jan 21 02:20:35 PM PST 24
Peak memory 209076 kb
Host smart-988aa1e5-947a-44f9-85b1-2a49938ad09f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099321478 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.4099321478 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3185334143
Short name T445
Test name
Test status
Simulation time 617916509 ps
CPU time 3.98 seconds
Started Jan 21 01:47:28 PM PST 24
Finished Jan 21 01:47:34 PM PST 24
Peak memory 217292 kb
Host smart-6cedc452-8bb5-49b0-90a2-ddf20029238e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185334143 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3185334143 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.3567869768
Short name T808
Test name
Test status
Simulation time 65390709978 ps
CPU time 1878.93 seconds
Started Jan 21 01:47:23 PM PST 24
Finished Jan 21 02:18:44 PM PST 24
Peak memory 376540 kb
Host smart-6c36de07-d96a-4b28-bb11-38f9b3007567
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3567869768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3567869768 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.3049560292
Short name T867
Test name
Test status
Simulation time 83518534503 ps
CPU time 1755.43 seconds
Started Jan 21 02:03:53 PM PST 24
Finished Jan 21 02:33:27 PM PST 24
Peak memory 377228 kb
Host smart-a0f36f72-bf9c-4352-8367-77cc808bd8ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3049560292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3049560292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2632915522
Short name T329
Test name
Test status
Simulation time 49806425817 ps
CPU time 1335.99 seconds
Started Jan 21 02:21:58 PM PST 24
Finished Jan 21 02:44:15 PM PST 24
Peak memory 339248 kb
Host smart-65dd0cbc-85c3-4be1-bb33-4864e29c756a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2632915522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2632915522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3135701379
Short name T813
Test name
Test status
Simulation time 40036198382 ps
CPU time 786.23 seconds
Started Jan 21 01:47:24 PM PST 24
Finished Jan 21 02:00:32 PM PST 24
Peak memory 296648 kb
Host smart-560e302f-20a0-4316-b2db-1c0874717c2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3135701379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3135701379 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.1322644924
Short name T474
Test name
Test status
Simulation time 711991439930 ps
CPU time 4996.24 seconds
Started Jan 21 01:47:29 PM PST 24
Finished Jan 21 03:10:47 PM PST 24
Peak memory 643756 kb
Host smart-6753cc98-954a-4979-9f3f-78cbdfec4bf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1322644924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1322644924 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.3779276983
Short name T201
Test name
Test status
Simulation time 1044126246134 ps
CPU time 4349.01 seconds
Started Jan 21 01:47:29 PM PST 24
Finished Jan 21 03:00:00 PM PST 24
Peak memory 564728 kb
Host smart-b978d278-f62d-43df-9797-8ded3cff92ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3779276983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3779276983 +enable_masking=0 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/40.kmac_alert_test.3061453009
Short name T690
Test name
Test status
Simulation time 120800588 ps
CPU time 0.82 seconds
Started Jan 21 02:31:50 PM PST 24
Finished Jan 21 02:31:51 PM PST 24
Peak memory 207336 kb
Host smart-3a9f9311-13d5-46bf-b422-ba1e2a87fc8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061453009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3061453009 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest


Test location /workspace/coverage/default/40.kmac_app.2759964127
Short name T661
Test name
Test status
Simulation time 640205782 ps
CPU time 7.25 seconds
Started Jan 21 02:52:38 PM PST 24
Finished Jan 21 02:52:48 PM PST 24
Peak memory 215916 kb
Host smart-65f488fc-6a29-4c7c-b39b-94d41a13ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759964127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2759964127 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest


Test location /workspace/coverage/default/40.kmac_burst_write.3092366159
Short name T1003
Test name
Test status
Simulation time 79163037194 ps
CPU time 478.69 seconds
Started Jan 21 02:10:45 PM PST 24
Finished Jan 21 02:18:45 PM PST 24
Peak memory 230536 kb
Host smart-41a5e467-66b5-4745-8967-3a8c46efb2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092366159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3092366159 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest


Test location /workspace/coverage/default/40.kmac_entropy_refresh.3383412794
Short name T595
Test name
Test status
Simulation time 154936073819 ps
CPU time 278.81 seconds
Started Jan 21 02:49:46 PM PST 24
Finished Jan 21 02:54:25 PM PST 24
Peak memory 241380 kb
Host smart-9d03a261-2300-4b75-9102-1d99fbc1a787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383412794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3383412794 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/40.kmac_error.368731544
Short name T49
Test name
Test status
Simulation time 1080757628 ps
CPU time 80.44 seconds
Started Jan 21 02:11:07 PM PST 24
Finished Jan 21 02:12:28 PM PST 24
Peak memory 235512 kb
Host smart-7e26793f-2c45-4a0b-bce6-ed32a3c8c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368731544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.368731544 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest


Test location /workspace/coverage/default/40.kmac_key_error.199895440
Short name T435
Test name
Test status
Simulation time 4034403265 ps
CPU time 3.97 seconds
Started Jan 21 02:11:16 PM PST 24
Finished Jan 21 02:11:21 PM PST 24
Peak memory 207544 kb
Host smart-9a9298e9-9490-46b5-a9d6-f6aba1e8f822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199895440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.199895440 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest


Test location /workspace/coverage/default/40.kmac_lc_escalation.3353877436
Short name T605
Test name
Test status
Simulation time 45560607 ps
CPU time 1.38 seconds
Started Jan 21 02:11:17 PM PST 24
Finished Jan 21 02:11:19 PM PST 24
Peak memory 215864 kb
Host smart-33a0e92f-f952-4e15-a948-72928418cacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353877436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3353877436 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest


Test location /workspace/coverage/default/40.kmac_long_msg_and_output.275928571
Short name T883
Test name
Test status
Simulation time 142621519275 ps
CPU time 1093.69 seconds
Started Jan 21 02:10:36 PM PST 24
Finished Jan 21 02:28:55 PM PST 24
Peak memory 321660 kb
Host smart-4e01ce37-8a72-410b-b883-f3420dcb1b5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275928571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.275928571 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/40.kmac_sideload.1199340086
Short name T696
Test name
Test status
Simulation time 9865347228 ps
CPU time 188.02 seconds
Started Jan 21 02:10:51 PM PST 24
Finished Jan 21 02:14:00 PM PST 24
Peak memory 236900 kb
Host smart-17aa3c91-df3d-4235-9796-4388f9e52ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199340086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1199340086 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest


Test location /workspace/coverage/default/40.kmac_smoke.3738426787
Short name T882
Test name
Test status
Simulation time 1242381981 ps
CPU time 22.01 seconds
Started Jan 21 02:10:36 PM PST 24
Finished Jan 21 02:11:03 PM PST 24
Peak memory 217816 kb
Host smart-9f59ffad-d0dd-4c0e-91a7-04ee0548ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738426787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3738426787 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest


Test location /workspace/coverage/default/40.kmac_stress_all.3564575025
Short name T742
Test name
Test status
Simulation time 127432513681 ps
CPU time 1287.18 seconds
Started Jan 21 02:11:17 PM PST 24
Finished Jan 21 02:32:45 PM PST 24
Peak memory 373944 kb
Host smart-1fe57c4d-f8e5-462f-a208-6303eab635e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3564575025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3564575025 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest


Test location /workspace/coverage/default/40.kmac_stress_all_with_rand_reset.1606025206
Short name T889
Test name
Test status
Simulation time 39064594083 ps
CPU time 595.44 seconds
Started Jan 21 02:11:18 PM PST 24
Finished Jan 21 02:21:14 PM PST 24
Peak memory 281564 kb
Host smart-6e679802-7737-4c52-a04a-77b371db56bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606025206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.1606025206 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.637506868
Short name T857
Test name
Test status
Simulation time 860075653 ps
CPU time 4.37 seconds
Started Jan 21 02:33:13 PM PST 24
Finished Jan 21 02:33:20 PM PST 24
Peak memory 209092 kb
Host smart-c814fd7d-4d49-4ce2-bbaf-d0c05866d1dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637506868 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_test_vectors_kmac.637506868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.3859481479
Short name T344
Test name
Test status
Simulation time 1398334143 ps
CPU time 5.5 seconds
Started Jan 21 02:11:00 PM PST 24
Finished Jan 21 02:11:06 PM PST 24
Peak memory 217164 kb
Host smart-c46889bc-2e64-44f4-96ae-b014cb0df5b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859481479 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.3859481479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.38571476
Short name T387
Test name
Test status
Simulation time 270300574596 ps
CPU time 1892.85 seconds
Started Jan 21 02:27:02 PM PST 24
Finished Jan 21 02:58:36 PM PST 24
Peak memory 391896 kb
Host smart-5be8ac91-82de-49bf-b509-83bd6b12e729
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38571476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.38571476 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.1853586321
Short name T432
Test name
Test status
Simulation time 34604895542 ps
CPU time 1484.54 seconds
Started Jan 21 02:10:49 PM PST 24
Finished Jan 21 02:35:35 PM PST 24
Peak memory 364824 kb
Host smart-7b62a3a5-dfd1-4b2a-9371-8e87dc7b79e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1853586321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.1853586321 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.2243464194
Short name T175
Test name
Test status
Simulation time 141211270938 ps
CPU time 1367.69 seconds
Started Jan 21 02:10:45 PM PST 24
Finished Jan 21 02:33:34 PM PST 24
Peak memory 329984 kb
Host smart-7302089e-6e07-4aa1-8b81-f0bd5b79290d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2243464194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2243464194 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.354235479
Short name T243
Test name
Test status
Simulation time 50615867551 ps
CPU time 930.11 seconds
Started Jan 21 02:10:59 PM PST 24
Finished Jan 21 02:26:30 PM PST 24
Peak memory 293628 kb
Host smart-8a2540ed-98cc-492f-a5f9-d5362cd687ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=354235479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.354235479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.619515522
Short name T198
Test name
Test status
Simulation time 189438764815 ps
CPU time 4708.33 seconds
Started Jan 21 02:10:58 PM PST 24
Finished Jan 21 03:29:28 PM PST 24
Peak memory 641300 kb
Host smart-43b78c61-8b1e-4a8d-b147-3d677e4e11f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=619515522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.619515522 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.84346791
Short name T830
Test name
Test status
Simulation time 582235934409 ps
CPU time 4246.7 seconds
Started Jan 21 02:10:58 PM PST 24
Finished Jan 21 03:21:47 PM PST 24
Peak memory 562728 kb
Host smart-75bd9614-9a75-49c2-a483-c5e2d26d0782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=84346791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.84346791 +enable_masking=0 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/41.kmac_alert_test.742273023
Short name T1127
Test name
Test status
Simulation time 12701684 ps
CPU time 0.77 seconds
Started Jan 21 02:12:21 PM PST 24
Finished Jan 21 02:12:23 PM PST 24
Peak memory 207340 kb
Host smart-63c22ac1-32d9-4779-bc6c-cc2e5d48a732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742273023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.742273023 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest


Test location /workspace/coverage/default/41.kmac_app.2605869985
Short name T380
Test name
Test status
Simulation time 24136157709 ps
CPU time 249 seconds
Started Jan 21 02:49:48 PM PST 24
Finished Jan 21 02:53:57 PM PST 24
Peak memory 241588 kb
Host smart-9b364e60-3e48-4cd1-8440-010d019223c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605869985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2605869985 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest


Test location /workspace/coverage/default/41.kmac_burst_write.3427699879
Short name T256
Test name
Test status
Simulation time 37076302142 ps
CPU time 205.87 seconds
Started Jan 21 02:11:41 PM PST 24
Finished Jan 21 02:15:07 PM PST 24
Peak memory 225464 kb
Host smart-95ee75cb-e759-4319-9d08-53ae9ea0c7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427699879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3427699879 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest


Test location /workspace/coverage/default/41.kmac_error.2912797982
Short name T545
Test name
Test status
Simulation time 2374256054 ps
CPU time 187.37 seconds
Started Jan 21 02:41:40 PM PST 24
Finished Jan 21 02:44:48 PM PST 24
Peak memory 247936 kb
Host smart-39c95380-353c-45b7-bfd9-ab28a91b2bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912797982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2912797982 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest


Test location /workspace/coverage/default/41.kmac_key_error.2902624368
Short name T501
Test name
Test status
Simulation time 514181912 ps
CPU time 3.36 seconds
Started Jan 21 02:37:35 PM PST 24
Finished Jan 21 02:37:40 PM PST 24
Peak memory 207488 kb
Host smart-ea436955-d227-4ea2-87b9-3ccaa49cc712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902624368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2902624368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest


Test location /workspace/coverage/default/41.kmac_lc_escalation.4062068771
Short name T732
Test name
Test status
Simulation time 72345660 ps
CPU time 1.41 seconds
Started Jan 21 03:19:38 PM PST 24
Finished Jan 21 03:19:41 PM PST 24
Peak memory 215852 kb
Host smart-8a9f8753-88be-41d2-a110-dce2073e65b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062068771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.4062068771 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest


Test location /workspace/coverage/default/41.kmac_long_msg_and_output.3377997060
Short name T265
Test name
Test status
Simulation time 30450149063 ps
CPU time 1347.92 seconds
Started Jan 21 02:11:34 PM PST 24
Finished Jan 21 02:34:03 PM PST 24
Peak memory 365488 kb
Host smart-2d5964a0-54da-4f73-ae59-2359d0a913f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377997060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.3377997060 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/41.kmac_sideload.33436064
Short name T222
Test name
Test status
Simulation time 216421563 ps
CPU time 2.46 seconds
Started Jan 21 02:29:04 PM PST 24
Finished Jan 21 02:29:08 PM PST 24
Peak memory 217284 kb
Host smart-80583cec-08d7-4341-b348-8c9cfd7e3c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33436064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.33436064 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest


Test location /workspace/coverage/default/41.kmac_smoke.2625330920
Short name T1060
Test name
Test status
Simulation time 874952688 ps
CPU time 43.95 seconds
Started Jan 21 02:11:32 PM PST 24
Finished Jan 21 02:12:17 PM PST 24
Peak memory 218256 kb
Host smart-64fb7280-e991-40e4-9dfc-33e5356321ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625330920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2625330920 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest


Test location /workspace/coverage/default/41.kmac_stress_all.1203921002
Short name T680
Test name
Test status
Simulation time 4885880471 ps
CPU time 377.74 seconds
Started Jan 21 02:30:34 PM PST 24
Finished Jan 21 02:36:53 PM PST 24
Peak memory 276952 kb
Host smart-b4f7ccee-a7a9-43c7-b188-c9e01a9feff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1203921002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1203921002 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest


Test location /workspace/coverage/default/41.kmac_stress_all_with_rand_reset.3086637601
Short name T833
Test name
Test status
Simulation time 235508126523 ps
CPU time 1569.2 seconds
Started Jan 21 02:12:21 PM PST 24
Finished Jan 21 02:38:32 PM PST 24
Peak memory 330752 kb
Host smart-4039a637-78ae-4814-8efd-13d9c6b7ee7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086637601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all_with_rand_reset.3086637601 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.3119017485
Short name T392
Test name
Test status
Simulation time 62732061 ps
CPU time 3.78 seconds
Started Jan 21 02:12:01 PM PST 24
Finished Jan 21 02:12:05 PM PST 24
Peak memory 217356 kb
Host smart-fe68723c-7ef5-4fdf-9c2d-cf3433c633ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119017485 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.3119017485 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2784121155
Short name T984
Test name
Test status
Simulation time 241933648 ps
CPU time 4.53 seconds
Started Jan 21 02:31:20 PM PST 24
Finished Jan 21 02:31:26 PM PST 24
Peak memory 217028 kb
Host smart-ab91e44a-a896-40a2-a3f5-bd86ee6e2fcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784121155 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2784121155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2887212649
Short name T901
Test name
Test status
Simulation time 293960526704 ps
CPU time 1911.61 seconds
Started Jan 21 02:11:41 PM PST 24
Finished Jan 21 02:43:34 PM PST 24
Peak memory 390024 kb
Host smart-83ce0172-1750-4229-bbef-f5f9ead00142
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2887212649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2887212649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.1659590278
Short name T1121
Test name
Test status
Simulation time 359543762206 ps
CPU time 1900.65 seconds
Started Jan 21 02:11:41 PM PST 24
Finished Jan 21 02:43:22 PM PST 24
Peak memory 367576 kb
Host smart-07595345-e2bf-42b5-a958-9e1e8390ca7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1659590278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1659590278 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.1244109995
Short name T759
Test name
Test status
Simulation time 141906132619 ps
CPU time 1423.37 seconds
Started Jan 21 02:11:40 PM PST 24
Finished Jan 21 02:35:25 PM PST 24
Peak memory 337376 kb
Host smart-77abe121-6377-4ee7-a317-0eccba699e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1244109995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1244109995 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.3350970349
Short name T331
Test name
Test status
Simulation time 49003604231 ps
CPU time 946 seconds
Started Jan 21 02:11:50 PM PST 24
Finished Jan 21 02:27:37 PM PST 24
Peak memory 291524 kb
Host smart-d8385b41-9b10-4616-b587-ae7d9a857336
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3350970349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3350970349 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.3402093147
Short name T761
Test name
Test status
Simulation time 1121267568828 ps
CPU time 5667.17 seconds
Started Jan 21 02:19:18 PM PST 24
Finished Jan 21 03:53:47 PM PST 24
Peak memory 654296 kb
Host smart-42edf582-a550-4ca8-a88a-6841a3bae83b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3402093147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3402093147 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2384234173
Short name T911
Test name
Test status
Simulation time 459905686418 ps
CPU time 4464.96 seconds
Started Jan 21 02:54:59 PM PST 24
Finished Jan 21 04:09:25 PM PST 24
Peak memory 576344 kb
Host smart-41a03176-3648-4a28-a844-033de51189f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2384234173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2384234173 +enable_masking=0 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/42.kmac_alert_test.1196751043
Short name T580
Test name
Test status
Simulation time 19435872 ps
CPU time 0.86 seconds
Started Jan 21 02:34:57 PM PST 24
Finished Jan 21 02:35:01 PM PST 24
Peak memory 207280 kb
Host smart-1fdf7a1b-5e3d-48ec-97cf-e7ff8499f716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196751043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1196751043 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest


Test location /workspace/coverage/default/42.kmac_app.2101418925
Short name T591
Test name
Test status
Simulation time 22263779486 ps
CPU time 282.03 seconds
Started Jan 21 02:12:55 PM PST 24
Finished Jan 21 02:17:38 PM PST 24
Peak memory 244020 kb
Host smart-3815085a-d689-4038-9c05-980fd6aa7b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101418925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2101418925 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest


Test location /workspace/coverage/default/42.kmac_burst_write.1562968272
Short name T1033
Test name
Test status
Simulation time 31432472502 ps
CPU time 729.4 seconds
Started Jan 21 02:35:44 PM PST 24
Finished Jan 21 02:47:54 PM PST 24
Peak memory 230804 kb
Host smart-02af25bc-4ccd-4eb3-8e19-919f19ce7ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562968272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1562968272 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest


Test location /workspace/coverage/default/42.kmac_entropy_refresh.1360954839
Short name T47
Test name
Test status
Simulation time 14855574252 ps
CPU time 56.33 seconds
Started Jan 21 02:25:34 PM PST 24
Finished Jan 21 02:26:31 PM PST 24
Peak memory 232068 kb
Host smart-2d3fe2d3-2d3d-4a1d-b192-91c4c95b945f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360954839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1360954839 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/42.kmac_error.2955651504
Short name T826
Test name
Test status
Simulation time 1450747189 ps
CPU time 27.18 seconds
Started Jan 21 02:12:52 PM PST 24
Finished Jan 21 02:13:19 PM PST 24
Peak memory 232636 kb
Host smart-e8c90d89-c7e7-499a-8f45-25b1c9b5fc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955651504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2955651504 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest


Test location /workspace/coverage/default/42.kmac_key_error.1376795876
Short name T510
Test name
Test status
Simulation time 1029470533 ps
CPU time 4.97 seconds
Started Jan 21 02:12:52 PM PST 24
Finished Jan 21 02:12:58 PM PST 24
Peak memory 207576 kb
Host smart-c014d993-69a3-4f3e-b0ae-f6f507f2d14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376795876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1376795876 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest


Test location /workspace/coverage/default/42.kmac_lc_escalation.853733250
Short name T785
Test name
Test status
Simulation time 47287027 ps
CPU time 1.27 seconds
Started Jan 21 02:25:38 PM PST 24
Finished Jan 21 02:25:40 PM PST 24
Peak memory 215256 kb
Host smart-6ab5769a-1cb7-450d-b090-2d25c449be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853733250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.853733250 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/42.kmac_lc_escalation/latest


Test location /workspace/coverage/default/42.kmac_long_msg_and_output.1017300225
Short name T666
Test name
Test status
Simulation time 91995114318 ps
CPU time 1617.47 seconds
Started Jan 21 02:35:34 PM PST 24
Finished Jan 21 03:02:32 PM PST 24
Peak memory 352904 kb
Host smart-f2f8860f-0fe7-4585-b1a6-4648e765c458
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017300225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.1017300225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/42.kmac_sideload.3671117686
Short name T793
Test name
Test status
Simulation time 2252258128 ps
CPU time 44.7 seconds
Started Jan 21 02:29:05 PM PST 24
Finished Jan 21 02:29:51 PM PST 24
Peak memory 223828 kb
Host smart-9fa25b28-fb45-4331-9180-28dee1852949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671117686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3671117686 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest


Test location /workspace/coverage/default/42.kmac_smoke.2707510868
Short name T364
Test name
Test status
Simulation time 2068630426 ps
CPU time 26.01 seconds
Started Jan 21 02:12:22 PM PST 24
Finished Jan 21 02:12:49 PM PST 24
Peak memory 218152 kb
Host smart-3b14de66-fb11-445a-b0e1-58af95d491aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707510868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2707510868 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest


Test location /workspace/coverage/default/42.kmac_stress_all.2401586977
Short name T361
Test name
Test status
Simulation time 5480156270 ps
CPU time 354.32 seconds
Started Jan 21 02:12:54 PM PST 24
Finished Jan 21 02:18:50 PM PST 24
Peak memory 270292 kb
Host smart-118541df-73a1-4d27-9068-fab327ad23f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2401586977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2401586977 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest


Test location /workspace/coverage/default/42.kmac_stress_all_with_rand_reset.817096550
Short name T28
Test name
Test status
Simulation time 81191335585 ps
CPU time 757.52 seconds
Started Jan 21 02:12:54 PM PST 24
Finished Jan 21 02:25:33 PM PST 24
Peak memory 303816 kb
Host smart-fcb6c662-45c7-4d59-84e8-46512c1de916
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817096550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all_with_rand_reset.817096550 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.2342923341
Short name T804
Test name
Test status
Simulation time 360594319 ps
CPU time 4.89 seconds
Started Jan 21 02:49:04 PM PST 24
Finished Jan 21 02:49:10 PM PST 24
Peak memory 209032 kb
Host smart-2f2ad6a3-e1f9-4b92-8d92-59f945fa48ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342923341 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.2342923341 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.4274295041
Short name T783
Test name
Test status
Simulation time 343506970 ps
CPU time 4.78 seconds
Started Jan 21 02:12:43 PM PST 24
Finished Jan 21 02:12:50 PM PST 24
Peak memory 208960 kb
Host smart-68a4d25b-4b49-4531-945e-9e657035a224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274295041 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.4274295041 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.734141188
Short name T943
Test name
Test status
Simulation time 74055631036 ps
CPU time 1880.68 seconds
Started Jan 21 02:38:26 PM PST 24
Finished Jan 21 03:09:48 PM PST 24
Peak memory 388944 kb
Host smart-97349731-fef3-4696-826d-6b41c5740e23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=734141188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.734141188 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.752155845
Short name T970
Test name
Test status
Simulation time 82690826195 ps
CPU time 1720.41 seconds
Started Jan 21 02:12:33 PM PST 24
Finished Jan 21 02:41:15 PM PST 24
Peak memory 373568 kb
Host smart-fadcd0c1-15b3-4b05-870c-d303494f4394
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=752155845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.752155845 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3357877011
Short name T359
Test name
Test status
Simulation time 190754490474 ps
CPU time 1371.4 seconds
Started Jan 21 02:12:32 PM PST 24
Finished Jan 21 02:35:25 PM PST 24
Peak memory 339088 kb
Host smart-fcfba0fa-d0a9-46ca-94fb-814d04a0d0ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3357877011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3357877011 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.582731447
Short name T887
Test name
Test status
Simulation time 64819319540 ps
CPU time 927.23 seconds
Started Jan 21 02:58:22 PM PST 24
Finished Jan 21 03:13:54 PM PST 24
Peak memory 293276 kb
Host smart-08999224-398e-4afe-a0e0-916e195aa124
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=582731447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.582731447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.3802477866
Short name T967
Test name
Test status
Simulation time 172930293400 ps
CPU time 4756.32 seconds
Started Jan 21 02:42:13 PM PST 24
Finished Jan 21 04:01:30 PM PST 24
Peak memory 646168 kb
Host smart-3d633bb0-594d-4eb1-b7f5-48beec8ea866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3802477866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3802477866 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.1693572936
Short name T381
Test name
Test status
Simulation time 223771422595 ps
CPU time 4204.21 seconds
Started Jan 21 02:12:38 PM PST 24
Finished Jan 21 03:22:44 PM PST 24
Peak memory 553984 kb
Host smart-c4b17d8f-4509-4d74-b7fa-ffe54beef7fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1693572936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.1693572936 +enable_masking=0 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/43.kmac_alert_test.151972183
Short name T1068
Test name
Test status
Simulation time 56375876 ps
CPU time 0.81 seconds
Started Jan 21 03:03:23 PM PST 24
Finished Jan 21 03:03:25 PM PST 24
Peak memory 207296 kb
Host smart-823b9304-7b7b-4565-b7a2-01d82011e11a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151972183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.151972183 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest


Test location /workspace/coverage/default/43.kmac_app.3959883125
Short name T6
Test name
Test status
Simulation time 8393124517 ps
CPU time 152.66 seconds
Started Jan 21 02:13:14 PM PST 24
Finished Jan 21 02:15:48 PM PST 24
Peak memory 234992 kb
Host smart-f3e938ff-db6d-4de8-a2ce-6b1a209fdb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959883125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3959883125 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest


Test location /workspace/coverage/default/43.kmac_burst_write.3337206692
Short name T532
Test name
Test status
Simulation time 5558617568 ps
CPU time 454.59 seconds
Started Jan 21 02:13:01 PM PST 24
Finished Jan 21 02:20:37 PM PST 24
Peak memory 229792 kb
Host smart-4d07ae2d-f66d-484a-8d46-9e486993f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337206692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3337206692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest


Test location /workspace/coverage/default/43.kmac_entropy_refresh.2726032731
Short name T230
Test name
Test status
Simulation time 5513920619 ps
CPU time 134.1 seconds
Started Jan 21 02:30:30 PM PST 24
Finished Jan 21 02:32:49 PM PST 24
Peak memory 231844 kb
Host smart-9d430eba-ed98-425e-bdb9-4b8984600e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726032731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2726032731 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/43.kmac_error.1308855658
Short name T372
Test name
Test status
Simulation time 42730257116 ps
CPU time 455.31 seconds
Started Jan 21 02:42:16 PM PST 24
Finished Jan 21 02:49:52 PM PST 24
Peak memory 256540 kb
Host smart-8016ff55-a066-4162-aa28-e4ca749ffb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308855658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1308855658 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest


Test location /workspace/coverage/default/43.kmac_key_error.325158155
Short name T1142
Test name
Test status
Simulation time 14851912185 ps
CPU time 4.44 seconds
Started Jan 21 02:13:24 PM PST 24
Finished Jan 21 02:13:29 PM PST 24
Peak memory 215792 kb
Host smart-e18fb5dd-d703-4731-9cc7-d467d48f20ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325158155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.325158155 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest


Test location /workspace/coverage/default/43.kmac_lc_escalation.990679126
Short name T479
Test name
Test status
Simulation time 1430152056 ps
CPU time 7.86 seconds
Started Jan 21 02:13:29 PM PST 24
Finished Jan 21 02:13:38 PM PST 24
Peak memory 219912 kb
Host smart-229a015f-e78c-4fdf-b452-b3f3d0b0160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990679126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.990679126 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/43.kmac_lc_escalation/latest


Test location /workspace/coverage/default/43.kmac_long_msg_and_output.1491317398
Short name T965
Test name
Test status
Simulation time 35952721730 ps
CPU time 781.2 seconds
Started Jan 21 02:13:02 PM PST 24
Finished Jan 21 02:26:04 PM PST 24
Peak memory 286884 kb
Host smart-f22c6cc4-0299-42ee-91a8-0632c2655d26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491317398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.1491317398 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/43.kmac_sideload.1149274090
Short name T894
Test name
Test status
Simulation time 34066362163 ps
CPU time 338.12 seconds
Started Jan 21 03:19:38 PM PST 24
Finished Jan 21 03:25:17 PM PST 24
Peak memory 243720 kb
Host smart-ab5d7d0a-bec8-4618-b1a4-fa88e863cb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149274090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1149274090 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest


Test location /workspace/coverage/default/43.kmac_smoke.2908004297
Short name T779
Test name
Test status
Simulation time 1030481181 ps
CPU time 16.34 seconds
Started Jan 21 02:43:06 PM PST 24
Finished Jan 21 02:43:23 PM PST 24
Peak memory 223804 kb
Host smart-f8075329-6724-43bd-9dc6-8053bc590f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908004297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2908004297 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest


Test location /workspace/coverage/default/43.kmac_stress_all.3533409881
Short name T393
Test name
Test status
Simulation time 53923486185 ps
CPU time 329.03 seconds
Started Jan 21 02:57:05 PM PST 24
Finished Jan 21 03:02:34 PM PST 24
Peak memory 256300 kb
Host smart-9779d416-5274-4619-911c-8c2142dec728
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3533409881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3533409881 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest


Test location /workspace/coverage/default/43.kmac_stress_all_with_rand_reset.2382672598
Short name T291
Test name
Test status
Simulation time 405334090284 ps
CPU time 1428.93 seconds
Started Jan 21 02:13:30 PM PST 24
Finished Jan 21 02:37:21 PM PST 24
Peak memory 289388 kb
Host smart-91e0da98-16fe-4960-a291-ed394c06e2a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382672598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.2382672598 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.4188144530
Short name T465
Test name
Test status
Simulation time 696609514 ps
CPU time 4.49 seconds
Started Jan 21 03:37:01 PM PST 24
Finished Jan 21 03:37:17 PM PST 24
Peak memory 209072 kb
Host smart-f1585d47-d821-4f24-b26e-b69dede794c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188144530 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.4188144530 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1725498467
Short name T538
Test name
Test status
Simulation time 502071790 ps
CPU time 4.81 seconds
Started Jan 21 02:13:11 PM PST 24
Finished Jan 21 02:13:18 PM PST 24
Peak memory 217356 kb
Host smart-59e69c7c-d220-4a34-86e1-1a910b455358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725498467 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1725498467 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.2859927383
Short name T224
Test name
Test status
Simulation time 77517489399 ps
CPU time 1535.15 seconds
Started Jan 21 02:28:16 PM PST 24
Finished Jan 21 02:53:52 PM PST 24
Peak memory 386980 kb
Host smart-863bcc8f-0df0-4581-91c9-a3ec33442d96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2859927383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.2859927383 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3410580072
Short name T339
Test name
Test status
Simulation time 134328306624 ps
CPU time 1450.46 seconds
Started Jan 21 02:13:03 PM PST 24
Finished Jan 21 02:37:14 PM PST 24
Peak memory 367476 kb
Host smart-92ff776e-4875-4688-9a4b-e4cfde5f4cbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3410580072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3410580072 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.3926129943
Short name T845
Test name
Test status
Simulation time 93915784751 ps
CPU time 1264.09 seconds
Started Jan 21 02:13:01 PM PST 24
Finished Jan 21 02:34:06 PM PST 24
Peak memory 329072 kb
Host smart-7603159b-64e2-4ee8-a397-dcc105482474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3926129943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.3926129943 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.1888065361
Short name T200
Test name
Test status
Simulation time 65554368992 ps
CPU time 893.39 seconds
Started Jan 21 02:36:46 PM PST 24
Finished Jan 21 02:51:40 PM PST 24
Peak memory 287652 kb
Host smart-69b59a59-980e-4dbc-806d-931c969807e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1888065361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1888065361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.2890093114
Short name T897
Test name
Test status
Simulation time 256329734911 ps
CPU time 5428.05 seconds
Started Jan 21 02:57:08 PM PST 24
Finished Jan 21 04:27:37 PM PST 24
Peak memory 647920 kb
Host smart-3a40b584-8139-4cf6-8d70-90e95db022d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2890093114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.2890093114 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3381177647
Short name T131
Test name
Test status
Simulation time 294066948755 ps
CPU time 3573.32 seconds
Started Jan 21 02:35:44 PM PST 24
Finished Jan 21 03:35:18 PM PST 24
Peak memory 577188 kb
Host smart-adf4558a-5c14-4577-949b-01220391def1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3381177647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3381177647 +enable_masking=0 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/44.kmac_alert_test.3221198164
Short name T823
Test name
Test status
Simulation time 22227821 ps
CPU time 0.76 seconds
Started Jan 21 02:14:14 PM PST 24
Finished Jan 21 02:14:15 PM PST 24
Peak memory 207320 kb
Host smart-fece0a94-6a69-4db0-9cc5-79efd1ac9bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221198164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3221198164 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest


Test location /workspace/coverage/default/44.kmac_app.3867317913
Short name T660
Test name
Test status
Simulation time 1258932222 ps
CPU time 14.81 seconds
Started Jan 21 02:13:55 PM PST 24
Finished Jan 21 02:14:11 PM PST 24
Peak memory 223148 kb
Host smart-90a3d855-bbbb-4e00-bea6-ac732f8a1178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867317913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3867317913 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest


Test location /workspace/coverage/default/44.kmac_burst_write.1168107806
Short name T497
Test name
Test status
Simulation time 86500137709 ps
CPU time 619.18 seconds
Started Jan 21 02:13:43 PM PST 24
Finished Jan 21 02:24:04 PM PST 24
Peak memory 230448 kb
Host smart-0141c039-c447-4aee-864c-424e7fc3c58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168107806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1168107806 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest


Test location /workspace/coverage/default/44.kmac_entropy_refresh.1599558908
Short name T853
Test name
Test status
Simulation time 68199415224 ps
CPU time 170.83 seconds
Started Jan 21 02:13:54 PM PST 24
Finished Jan 21 02:16:46 PM PST 24
Peak memory 236412 kb
Host smart-27e235b0-cd08-4c3f-b80e-b2e6503f4bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599558908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1599558908 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/44.kmac_error.1083961044
Short name T508
Test name
Test status
Simulation time 16310967580 ps
CPU time 182.73 seconds
Started Jan 21 02:50:17 PM PST 24
Finished Jan 21 02:53:21 PM PST 24
Peak memory 248456 kb
Host smart-5f0560bb-76e8-4059-92cb-618dadca5be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083961044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1083961044 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest


Test location /workspace/coverage/default/44.kmac_key_error.1792833539
Short name T430
Test name
Test status
Simulation time 3979731834 ps
CPU time 5.11 seconds
Started Jan 21 02:14:03 PM PST 24
Finished Jan 21 02:14:09 PM PST 24
Peak memory 207560 kb
Host smart-bf9046df-6fba-4ea8-9dc3-b90dab3f2dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792833539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1792833539 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest


Test location /workspace/coverage/default/44.kmac_lc_escalation.612724977
Short name T1147
Test name
Test status
Simulation time 53977811 ps
CPU time 1.38 seconds
Started Jan 21 02:14:16 PM PST 24
Finished Jan 21 02:14:18 PM PST 24
Peak memory 220344 kb
Host smart-0c7d0272-ee03-4fa9-a447-9bb8adea8128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612724977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.612724977 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/44.kmac_lc_escalation/latest


Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2448760266
Short name T46
Test name
Test status
Simulation time 169695089780 ps
CPU time 1772.88 seconds
Started Jan 21 02:13:45 PM PST 24
Finished Jan 21 02:43:19 PM PST 24
Peak memory 377656 kb
Host smart-6a462b97-06e9-416e-834d-b41ccd00cc29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448760266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2448760266 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/44.kmac_sideload.4191528449
Short name T1140
Test name
Test status
Simulation time 8847966803 ps
CPU time 184.25 seconds
Started Jan 21 02:13:42 PM PST 24
Finished Jan 21 02:16:48 PM PST 24
Peak memory 233588 kb
Host smart-d933807c-0c6d-4a8f-a66f-f9b9970418ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191528449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.4191528449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest


Test location /workspace/coverage/default/44.kmac_smoke.3856081668
Short name T268
Test name
Test status
Simulation time 96479899 ps
CPU time 1.66 seconds
Started Jan 21 02:13:29 PM PST 24
Finished Jan 21 02:13:32 PM PST 24
Peak memory 215928 kb
Host smart-49261089-1b4e-4617-bc1d-bf33c9c6508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856081668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3856081668 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.3808157892
Short name T700
Test name
Test status
Simulation time 228968079 ps
CPU time 4.61 seconds
Started Jan 21 02:27:22 PM PST 24
Finished Jan 21 02:27:27 PM PST 24
Peak memory 209036 kb
Host smart-668567bb-3061-476b-9a84-ec8b2c3f5547
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808157892 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.3808157892 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.1225528914
Short name T431
Test name
Test status
Simulation time 68409466 ps
CPU time 3.76 seconds
Started Jan 21 03:45:21 PM PST 24
Finished Jan 21 03:45:27 PM PST 24
Peak memory 209176 kb
Host smart-b409268b-a1eb-4115-8e3e-db7c9b1558e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225528914 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.1225528914 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.2349194994
Short name T1004
Test name
Test status
Simulation time 19195074020 ps
CPU time 1619.09 seconds
Started Jan 21 02:13:43 PM PST 24
Finished Jan 21 02:40:44 PM PST 24
Peak memory 398896 kb
Host smart-6858d6e4-f1f8-453e-9830-bc3e7d12e785
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2349194994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.2349194994 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.3040319676
Short name T824
Test name
Test status
Simulation time 95095470162 ps
CPU time 1883.75 seconds
Started Jan 21 02:13:44 PM PST 24
Finished Jan 21 02:45:09 PM PST 24
Peak memory 372984 kb
Host smart-e76d116e-bcdc-498a-be57-89caee37f56d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3040319676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.3040319676 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.4230347758
Short name T684
Test name
Test status
Simulation time 13684922528 ps
CPU time 1133.14 seconds
Started Jan 21 02:13:49 PM PST 24
Finished Jan 21 02:32:43 PM PST 24
Peak memory 333076 kb
Host smart-e2acb5d4-8c81-42ab-95e9-9c94c9382af9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4230347758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.4230347758 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.397962993
Short name T931
Test name
Test status
Simulation time 35408047189 ps
CPU time 870.97 seconds
Started Jan 21 03:40:41 PM PST 24
Finished Jan 21 03:55:13 PM PST 24
Peak memory 295856 kb
Host smart-60811732-7891-4df3-b385-e3b06cf847ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=397962993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.397962993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.2958854537
Short name T477
Test name
Test status
Simulation time 105787242188 ps
CPU time 4087.49 seconds
Started Jan 21 02:39:51 PM PST 24
Finished Jan 21 03:48:00 PM PST 24
Peak memory 647856 kb
Host smart-b02e3885-8a8a-4a26-95b8-c4721da69637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2958854537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.2958854537 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.3910152336
Short name T182
Test name
Test status
Simulation time 148639326978 ps
CPU time 4153.19 seconds
Started Jan 21 02:37:08 PM PST 24
Finished Jan 21 03:46:22 PM PST 24
Peak memory 562740 kb
Host smart-98236f4e-1a36-4fd7-80db-999a0be3e9f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3910152336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.3910152336 +enable_masking=0 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/45.kmac_alert_test.283514503
Short name T216
Test name
Test status
Simulation time 65769128 ps
CPU time 0.79 seconds
Started Jan 21 02:31:42 PM PST 24
Finished Jan 21 02:31:44 PM PST 24
Peak memory 207288 kb
Host smart-bed5b973-bf02-4113-a2ce-890a5fecf277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283514503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.283514503 +enable_m
asking=0 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest


Test location /workspace/coverage/default/45.kmac_app.2757706744
Short name T515
Test name
Test status
Simulation time 97312297864 ps
CPU time 178.51 seconds
Started Jan 21 02:15:00 PM PST 24
Finished Jan 21 02:17:59 PM PST 24
Peak memory 236784 kb
Host smart-b12109fe-b0d0-4dbc-8ea4-8c41f95af0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757706744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2757706744 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest


Test location /workspace/coverage/default/45.kmac_burst_write.519750552
Short name T800
Test name
Test status
Simulation time 10548388247 ps
CPU time 337.15 seconds
Started Jan 21 02:14:20 PM PST 24
Finished Jan 21 02:19:58 PM PST 24
Peak memory 226336 kb
Host smart-5940dd7e-14a7-4184-ac81-2fed93ed438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519750552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.519750552 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest


Test location /workspace/coverage/default/45.kmac_entropy_refresh.4166361031
Short name T862
Test name
Test status
Simulation time 25994379107 ps
CPU time 199.16 seconds
Started Jan 21 02:14:59 PM PST 24
Finished Jan 21 02:18:20 PM PST 24
Peak memory 236268 kb
Host smart-3594840a-9f46-4585-be30-1d538299746d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166361031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.4166361031 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/45.kmac_error.384374093
Short name T141
Test name
Test status
Simulation time 8936363177 ps
CPU time 311.05 seconds
Started Jan 21 02:30:28 PM PST 24
Finished Jan 21 02:35:45 PM PST 24
Peak memory 256544 kb
Host smart-2561b21f-adde-4064-927c-bef14fb2a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384374093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.384374093 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest


Test location /workspace/coverage/default/45.kmac_key_error.3633768036
Short name T394
Test name
Test status
Simulation time 5462863756 ps
CPU time 2.65 seconds
Started Jan 21 02:14:58 PM PST 24
Finished Jan 21 02:15:03 PM PST 24
Peak memory 207648 kb
Host smart-b412d7e2-be7d-4623-a149-7e5a6e310660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633768036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3633768036 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest


Test location /workspace/coverage/default/45.kmac_lc_escalation.1020882452
Short name T1044
Test name
Test status
Simulation time 2837821981 ps
CPU time 15.84 seconds
Started Jan 21 02:15:07 PM PST 24
Finished Jan 21 02:15:24 PM PST 24
Peak memory 224016 kb
Host smart-e5f46bfc-ee50-471f-9ab4-539253520a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020882452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1020882452 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest


Test location /workspace/coverage/default/45.kmac_long_msg_and_output.1250487990
Short name T285
Test name
Test status
Simulation time 22836472940 ps
CPU time 525.65 seconds
Started Jan 21 02:14:21 PM PST 24
Finished Jan 21 02:23:07 PM PST 24
Peak memory 266004 kb
Host smart-15745e43-a773-4b2b-bc79-3cdb93e93094
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250487990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.1250487990 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/45.kmac_sideload.3324520972
Short name T294
Test name
Test status
Simulation time 11782004124 ps
CPU time 206.01 seconds
Started Jan 21 02:14:22 PM PST 24
Finished Jan 21 02:17:49 PM PST 24
Peak memory 237380 kb
Host smart-d7c44e33-2dc4-4ff4-893b-2cb826723b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324520972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3324520972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest


Test location /workspace/coverage/default/45.kmac_smoke.3107531433
Short name T842
Test name
Test status
Simulation time 5603668699 ps
CPU time 27.02 seconds
Started Jan 21 02:29:42 PM PST 24
Finished Jan 21 02:30:10 PM PST 24
Peak memory 218356 kb
Host smart-0159477c-ecd3-4c16-8133-e11fb4ab8887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107531433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3107531433 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest


Test location /workspace/coverage/default/45.kmac_stress_all.1714393669
Short name T1123
Test name
Test status
Simulation time 383130482 ps
CPU time 4.79 seconds
Started Jan 21 02:15:09 PM PST 24
Finished Jan 21 02:15:14 PM PST 24
Peak memory 217732 kb
Host smart-91445bb8-7d7f-4a2e-b92e-3bbff0846397
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1714393669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1714393669 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest


Test location /workspace/coverage/default/45.kmac_stress_all_with_rand_reset.1188177508
Short name T838
Test name
Test status
Simulation time 316323414543 ps
CPU time 1787.33 seconds
Started Jan 21 02:15:09 PM PST 24
Finished Jan 21 02:44:58 PM PST 24
Peak memory 355196 kb
Host smart-9face998-7e97-4e89-871e-70e5a8da0548
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188177508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.1188177508 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1146730573
Short name T627
Test name
Test status
Simulation time 173639752 ps
CPU time 4.8 seconds
Started Jan 21 02:14:42 PM PST 24
Finished Jan 21 02:14:48 PM PST 24
Peak memory 209080 kb
Host smart-912be055-ce81-4507-b6ee-f061b34372bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146730573 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1146730573 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.1686182462
Short name T582
Test name
Test status
Simulation time 69746273 ps
CPU time 4.08 seconds
Started Jan 21 02:14:52 PM PST 24
Finished Jan 21 02:14:59 PM PST 24
Peak memory 217144 kb
Host smart-6b0de0f3-b68c-4d25-96d3-4b278b1f7bf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686182462 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.1686182462 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.441336313
Short name T941
Test name
Test status
Simulation time 118376459171 ps
CPU time 1648.24 seconds
Started Jan 21 02:14:22 PM PST 24
Finished Jan 21 02:41:51 PM PST 24
Peak memory 393960 kb
Host smart-f5a9c087-2dae-4d47-a798-c71da50b7494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=441336313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.441336313 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.1375742043
Short name T757
Test name
Test status
Simulation time 165599146205 ps
CPU time 1792.32 seconds
Started Jan 21 02:14:31 PM PST 24
Finished Jan 21 02:44:24 PM PST 24
Peak memory 374408 kb
Host smart-81987df5-337a-4010-884f-5891f20e2ba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1375742043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.1375742043 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2374781777
Short name T505
Test name
Test status
Simulation time 90049984285 ps
CPU time 1178.79 seconds
Started Jan 21 02:36:39 PM PST 24
Finished Jan 21 02:56:19 PM PST 24
Peak memory 331432 kb
Host smart-20a5ae7c-86c7-4cf5-be4e-cde77efbe0e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2374781777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2374781777 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.1285604927
Short name T555
Test name
Test status
Simulation time 48266011947 ps
CPU time 994.54 seconds
Started Jan 21 02:14:32 PM PST 24
Finished Jan 21 02:31:08 PM PST 24
Peak memory 292112 kb
Host smart-7a75f164-f92d-45e6-9dd2-8da820bbd96b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1285604927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.1285604927 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.1759777202
Short name T1072
Test name
Test status
Simulation time 227803111443 ps
CPU time 4846.87 seconds
Started Jan 21 02:14:32 PM PST 24
Finished Jan 21 03:35:20 PM PST 24
Peak memory 642096 kb
Host smart-6abae427-a97d-49cb-a05f-9ca44a62890b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1759777202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1759777202 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.566361803
Short name T634
Test name
Test status
Simulation time 491242465535 ps
CPU time 4446.31 seconds
Started Jan 21 02:14:43 PM PST 24
Finished Jan 21 03:28:50 PM PST 24
Peak memory 558080 kb
Host smart-e5480c75-9a41-47da-85a3-fe40bad4417d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=566361803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.566361803 +enable_masking=0 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/46.kmac_alert_test.3544735292
Short name T632
Test name
Test status
Simulation time 42401315 ps
CPU time 0.76 seconds
Started Jan 21 02:16:23 PM PST 24
Finished Jan 21 02:16:25 PM PST 24
Peak memory 207216 kb
Host smart-150477f7-374e-4ef3-8911-9a0916c02985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544735292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3544735292 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest


Test location /workspace/coverage/default/46.kmac_app.277767292
Short name T1037
Test name
Test status
Simulation time 1954275751 ps
CPU time 24.66 seconds
Started Jan 21 02:15:54 PM PST 24
Finished Jan 21 02:16:20 PM PST 24
Peak memory 223824 kb
Host smart-a1a822cb-87df-43c4-926c-ca450ad46b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277767292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.277767292 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest


Test location /workspace/coverage/default/46.kmac_burst_write.1603312529
Short name T856
Test name
Test status
Simulation time 20847389797 ps
CPU time 422.69 seconds
Started Jan 21 02:23:22 PM PST 24
Finished Jan 21 02:30:26 PM PST 24
Peak memory 229152 kb
Host smart-1fde6e92-70f2-4f84-a92f-d7f27d54fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603312529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1603312529 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest


Test location /workspace/coverage/default/46.kmac_entropy_refresh.1525924027
Short name T338
Test name
Test status
Simulation time 9972458375 ps
CPU time 158.61 seconds
Started Jan 21 02:15:55 PM PST 24
Finished Jan 21 02:18:34 PM PST 24
Peak memory 233476 kb
Host smart-4c8d41d4-4eca-47bc-9bd9-8df9dd156318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525924027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1525924027 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/46.kmac_error.208686904
Short name T500
Test name
Test status
Simulation time 95325764026 ps
CPU time 384.6 seconds
Started Jan 21 02:15:56 PM PST 24
Finished Jan 21 02:22:21 PM PST 24
Peak memory 256656 kb
Host smart-2e0a1a6d-783f-49e0-b60b-f219444250b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208686904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.208686904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest


Test location /workspace/coverage/default/46.kmac_key_error.1206640464
Short name T651
Test name
Test status
Simulation time 1300663045 ps
CPU time 3.75 seconds
Started Jan 21 02:15:54 PM PST 24
Finished Jan 21 02:15:59 PM PST 24
Peak memory 207432 kb
Host smart-65286e4b-2c4e-4591-b87e-669abad9686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206640464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1206640464 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest


Test location /workspace/coverage/default/46.kmac_lc_escalation.129239272
Short name T415
Test name
Test status
Simulation time 542824777 ps
CPU time 3.11 seconds
Started Jan 21 02:42:06 PM PST 24
Finished Jan 21 02:42:09 PM PST 24
Peak memory 218968 kb
Host smart-de9cba9b-9bf9-40bd-853c-070daa9ab622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129239272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.129239272 +enable_masking=0 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest


Test location /workspace/coverage/default/46.kmac_long_msg_and_output.3524111671
Short name T712
Test name
Test status
Simulation time 82420490249 ps
CPU time 946.28 seconds
Started Jan 21 02:15:19 PM PST 24
Finished Jan 21 02:31:07 PM PST 24
Peak memory 307540 kb
Host smart-a8a050e8-3ab6-4752-8322-e91061b139e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524111671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.3524111671 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/46.kmac_sideload.3838380888
Short name T601
Test name
Test status
Simulation time 23213540422 ps
CPU time 256.42 seconds
Started Jan 21 02:15:30 PM PST 24
Finished Jan 21 02:19:52 PM PST 24
Peak memory 238380 kb
Host smart-480e9c21-d6d2-43c6-bb89-8e78aa98d3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838380888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3838380888 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest


Test location /workspace/coverage/default/46.kmac_smoke.3664588215
Short name T313
Test name
Test status
Simulation time 552358099 ps
CPU time 10.27 seconds
Started Jan 21 02:15:10 PM PST 24
Finished Jan 21 02:15:21 PM PST 24
Peak memory 217560 kb
Host smart-22e4fed6-e354-460a-9c70-db1904311e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664588215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.3664588215 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest


Test location /workspace/coverage/default/46.kmac_stress_all.1615378498
Short name T1042
Test name
Test status
Simulation time 20935939095 ps
CPU time 203.44 seconds
Started Jan 21 02:16:27 PM PST 24
Finished Jan 21 02:19:51 PM PST 24
Peak memory 255700 kb
Host smart-4d007cb1-e555-4326-96a3-9a54dead6c0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1615378498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1615378498 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.4058138102
Short name T537
Test name
Test status
Simulation time 129251947 ps
CPU time 3.88 seconds
Started Jan 21 02:15:55 PM PST 24
Finished Jan 21 02:15:59 PM PST 24
Peak memory 208504 kb
Host smart-b5c5d131-4f18-4701-88aa-347123a5d6af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058138102 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.4058138102 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.3925100701
Short name T567
Test name
Test status
Simulation time 200107274 ps
CPU time 4 seconds
Started Jan 21 02:32:47 PM PST 24
Finished Jan 21 02:32:53 PM PST 24
Peak memory 217416 kb
Host smart-6cdb7585-54e1-4d89-8330-a2dd33ab189d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925100701 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.3925100701 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.1448739441
Short name T756
Test name
Test status
Simulation time 18434129135 ps
CPU time 1498.68 seconds
Started Jan 21 02:15:37 PM PST 24
Finished Jan 21 02:40:38 PM PST 24
Peak memory 372424 kb
Host smart-2ab3ee53-2060-4888-9f1e-ae897fa61a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1448739441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1448739441 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.4152781966
Short name T796
Test name
Test status
Simulation time 163408543024 ps
CPU time 1542.73 seconds
Started Jan 21 02:15:37 PM PST 24
Finished Jan 21 02:41:22 PM PST 24
Peak memory 377492 kb
Host smart-1f2a86df-6423-4326-ade8-1cff3a5a00fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4152781966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.4152781966 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.363459247
Short name T1006
Test name
Test status
Simulation time 13464294770 ps
CPU time 1139.63 seconds
Started Jan 21 02:15:48 PM PST 24
Finished Jan 21 02:34:49 PM PST 24
Peak memory 331184 kb
Host smart-68060909-93e2-40a3-be76-734b22e9a476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=363459247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.363459247 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.832639870
Short name T617
Test name
Test status
Simulation time 78777689739 ps
CPU time 796.41 seconds
Started Jan 21 02:15:46 PM PST 24
Finished Jan 21 02:29:04 PM PST 24
Peak memory 293388 kb
Host smart-8d3964c5-ab02-4cf5-87b4-be933a5d030e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=832639870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.832639870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.1682328511
Short name T458
Test name
Test status
Simulation time 183374547483 ps
CPU time 4726.88 seconds
Started Jan 21 02:39:59 PM PST 24
Finished Jan 21 03:58:47 PM PST 24
Peak memory 651420 kb
Host smart-a2137a83-a739-427f-b23d-3b1bf16ef77a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1682328511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1682328511 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2582943014
Short name T953
Test name
Test status
Simulation time 972185848490 ps
CPU time 3982.8 seconds
Started Jan 21 02:15:57 PM PST 24
Finished Jan 21 03:22:21 PM PST 24
Peak memory 563720 kb
Host smart-4f9e31d6-2291-4525-bd99-14fd93a66dfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2582943014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2582943014 +enable_masking=0 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/47.kmac_alert_test.3685477887
Short name T859
Test name
Test status
Simulation time 17566752 ps
CPU time 0.79 seconds
Started Jan 21 02:17:04 PM PST 24
Finished Jan 21 02:17:06 PM PST 24
Peak memory 207280 kb
Host smart-93adb873-9141-4504-9319-2657812195d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685477887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3685477887 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest


Test location /workspace/coverage/default/47.kmac_app.226987526
Short name T523
Test name
Test status
Simulation time 6058440041 ps
CPU time 64.14 seconds
Started Jan 21 02:16:54 PM PST 24
Finished Jan 21 02:17:59 PM PST 24
Peak memory 225592 kb
Host smart-ba040674-682d-4ce9-9767-ead226831931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226987526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.226987526 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest


Test location /workspace/coverage/default/47.kmac_burst_write.373162972
Short name T177
Test name
Test status
Simulation time 25058921177 ps
CPU time 354.29 seconds
Started Jan 21 02:16:35 PM PST 24
Finished Jan 21 02:22:30 PM PST 24
Peak memory 227512 kb
Host smart-9006eb1d-20ae-425e-a62f-c4e7c119caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373162972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.373162972 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest


Test location /workspace/coverage/default/47.kmac_entropy_refresh.1091027019
Short name T433
Test name
Test status
Simulation time 12150821671 ps
CPU time 219.02 seconds
Started Jan 21 02:16:55 PM PST 24
Finished Jan 21 02:20:35 PM PST 24
Peak memory 238472 kb
Host smart-244b0926-b9ae-4588-8285-c4cd182a7c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091027019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1091027019 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/47.kmac_error.2741105458
Short name T652
Test name
Test status
Simulation time 5411559988 ps
CPU time 42.86 seconds
Started Jan 21 02:17:03 PM PST 24
Finished Jan 21 02:17:47 PM PST 24
Peak memory 232140 kb
Host smart-e80f9cfe-21d6-4a54-9fb8-1ef1f5b245e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741105458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2741105458 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest


Test location /workspace/coverage/default/47.kmac_key_error.3406125533
Short name T725
Test name
Test status
Simulation time 1264533019 ps
CPU time 6.08 seconds
Started Jan 21 02:17:04 PM PST 24
Finished Jan 21 02:17:11 PM PST 24
Peak memory 207464 kb
Host smart-22d7609b-64c1-48ef-a97d-0fccdb1268b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406125533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3406125533 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest


Test location /workspace/coverage/default/47.kmac_lc_escalation.4090588864
Short name T992
Test name
Test status
Simulation time 94831257 ps
CPU time 1.17 seconds
Started Jan 21 02:17:04 PM PST 24
Finished Jan 21 02:17:06 PM PST 24
Peak memory 215932 kb
Host smart-2c38433d-319d-4efb-910e-a611156000b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090588864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.4090588864 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest


Test location /workspace/coverage/default/47.kmac_long_msg_and_output.1496881756
Short name T1079
Test name
Test status
Simulation time 74940261529 ps
CPU time 1442.04 seconds
Started Jan 21 02:16:35 PM PST 24
Finished Jan 21 02:40:38 PM PST 24
Peak memory 375812 kb
Host smart-86c73ff7-a996-446d-b833-6e14b829238e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496881756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.1496881756 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/47.kmac_sideload.682194773
Short name T354
Test name
Test status
Simulation time 7473271066 ps
CPU time 240.52 seconds
Started Jan 21 02:16:34 PM PST 24
Finished Jan 21 02:20:35 PM PST 24
Peak memory 241888 kb
Host smart-b244e7fd-d16b-40fb-ab24-99e85ec23c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682194773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.682194773 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest


Test location /workspace/coverage/default/47.kmac_smoke.1245919084
Short name T697
Test name
Test status
Simulation time 814204893 ps
CPU time 41.29 seconds
Started Jan 21 02:16:24 PM PST 24
Finished Jan 21 02:17:06 PM PST 24
Peak memory 218372 kb
Host smart-b0c02dad-95d3-4537-8fd8-c49f6232e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245919084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1245919084 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest


Test location /workspace/coverage/default/47.kmac_stress_all.3080041228
Short name T525
Test name
Test status
Simulation time 74011280441 ps
CPU time 1971.09 seconds
Started Jan 21 02:17:07 PM PST 24
Finished Jan 21 02:49:59 PM PST 24
Peak memory 444956 kb
Host smart-e3e2ef95-16a3-443b-9642-d8981b94bbd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3080041228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3080041228 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest


Test location /workspace/coverage/default/47.kmac_stress_all_with_rand_reset.2705513268
Short name T383
Test name
Test status
Simulation time 182390328029 ps
CPU time 808.66 seconds
Started Jan 21 02:17:03 PM PST 24
Finished Jan 21 02:30:32 PM PST 24
Peak memory 297904 kb
Host smart-3db6a5db-17c7-4c12-b507-77bc0fd0f61a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705513268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all_with_rand_reset.2705513268 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.755745433
Short name T447
Test name
Test status
Simulation time 130566777 ps
CPU time 3.66 seconds
Started Jan 21 02:16:46 PM PST 24
Finished Jan 21 02:16:50 PM PST 24
Peak memory 208184 kb
Host smart-5f958bc3-44ed-4a0a-b0ed-9071b2c7ada5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755745433 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.kmac_test_vectors_kmac.755745433 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.1275915231
Short name T731
Test name
Test status
Simulation time 63530087 ps
CPU time 3.9 seconds
Started Jan 21 02:16:56 PM PST 24
Finished Jan 21 02:17:01 PM PST 24
Peak memory 208880 kb
Host smart-ab29ef42-60f1-435b-86dc-9db805aa933d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275915231 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.1275915231 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.2041480978
Short name T784
Test name
Test status
Simulation time 78306309167 ps
CPU time 1557.72 seconds
Started Jan 21 03:04:11 PM PST 24
Finished Jan 21 03:30:10 PM PST 24
Peak memory 391164 kb
Host smart-a4ff45ea-590a-4f1f-9c87-ad8a94974c12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2041480978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.2041480978 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.600568916
Short name T499
Test name
Test status
Simulation time 135105495303 ps
CPU time 1864.8 seconds
Started Jan 21 02:16:43 PM PST 24
Finished Jan 21 02:47:49 PM PST 24
Peak memory 375564 kb
Host smart-bd3bd2f4-17ec-4d91-b9c7-7ae3f0ed2651
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=600568916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.600568916 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.206322069
Short name T352
Test name
Test status
Simulation time 246019951840 ps
CPU time 1257.72 seconds
Started Jan 21 02:16:42 PM PST 24
Finished Jan 21 02:37:41 PM PST 24
Peak memory 333244 kb
Host smart-3819cd95-9809-42b7-8972-1d081535370f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=206322069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.206322069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.3039212627
Short name T705
Test name
Test status
Simulation time 9906018206 ps
CPU time 779.11 seconds
Started Jan 21 02:16:46 PM PST 24
Finished Jan 21 02:29:46 PM PST 24
Peak memory 292588 kb
Host smart-e6736d32-7f9f-44ce-9b5c-e4f7ec780218
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3039212627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.3039212627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3904272214
Short name T625
Test name
Test status
Simulation time 820409969309 ps
CPU time 5218.26 seconds
Started Jan 21 02:16:44 PM PST 24
Finished Jan 21 03:43:43 PM PST 24
Peak memory 653108 kb
Host smart-025af076-d423-4398-a274-d089c4889803
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3904272214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3904272214 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.3432694815
Short name T855
Test name
Test status
Simulation time 2704521550876 ps
CPU time 4856.01 seconds
Started Jan 21 02:16:45 PM PST 24
Finished Jan 21 03:37:42 PM PST 24
Peak memory 566892 kb
Host smart-8cb23df9-ee14-4ad0-9977-f026510a570d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3432694815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3432694815 +enable_masking=0 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/48.kmac_alert_test.3192814965
Short name T212
Test name
Test status
Simulation time 25710588 ps
CPU time 0.73 seconds
Started Jan 21 02:17:52 PM PST 24
Finished Jan 21 02:17:54 PM PST 24
Peak memory 207188 kb
Host smart-33157338-ae07-4ac6-94fa-e04df582b2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192814965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3192814965 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest


Test location /workspace/coverage/default/48.kmac_app.1585211273
Short name T979
Test name
Test status
Simulation time 72112645130 ps
CPU time 304.81 seconds
Started Jan 21 02:17:32 PM PST 24
Finished Jan 21 02:22:39 PM PST 24
Peak memory 242084 kb
Host smart-0b97a18d-c3db-4661-a557-e82231815807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585211273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1585211273 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest


Test location /workspace/coverage/default/48.kmac_burst_write.3821293538
Short name T495
Test name
Test status
Simulation time 136826117958 ps
CPU time 620.32 seconds
Started Jan 21 02:17:17 PM PST 24
Finished Jan 21 02:27:38 PM PST 24
Peak memory 230808 kb
Host smart-916daf36-7959-4ab9-a07c-ccda63b5da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821293538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3821293538 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest


Test location /workspace/coverage/default/48.kmac_entropy_refresh.2153838433
Short name T48
Test name
Test status
Simulation time 18010043805 ps
CPU time 225.51 seconds
Started Jan 21 02:17:43 PM PST 24
Finished Jan 21 02:21:29 PM PST 24
Peak memory 239940 kb
Host smart-6ab16f1e-e2e7-44a8-9d8d-18f71b35b775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153838433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2153838433 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/48.kmac_error.4028561664
Short name T547
Test name
Test status
Simulation time 34877210451 ps
CPU time 347.36 seconds
Started Jan 21 02:17:41 PM PST 24
Finished Jan 21 02:23:29 PM PST 24
Peak memory 256504 kb
Host smart-3fa6e26d-1576-4ae4-9075-ef2e74c4b292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028561664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.4028561664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest


Test location /workspace/coverage/default/48.kmac_key_error.750791452
Short name T683
Test name
Test status
Simulation time 2556778976 ps
CPU time 6.84 seconds
Started Jan 21 02:17:41 PM PST 24
Finished Jan 21 02:17:49 PM PST 24
Peak memory 207640 kb
Host smart-7863dafb-a3a1-4397-8e57-95072feb2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750791452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.750791452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest


Test location /workspace/coverage/default/48.kmac_lc_escalation.3661604558
Short name T10
Test name
Test status
Simulation time 52513554 ps
CPU time 1.39 seconds
Started Jan 21 02:17:43 PM PST 24
Finished Jan 21 02:17:46 PM PST 24
Peak memory 215872 kb
Host smart-e45486b1-21f0-4fc8-ab4d-507599e2a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661604558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3661604558 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest


Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1618067855
Short name T1135
Test name
Test status
Simulation time 44990757604 ps
CPU time 960.15 seconds
Started Jan 21 02:17:16 PM PST 24
Finished Jan 21 02:33:17 PM PST 24
Peak memory 319012 kb
Host smart-a9b45fc4-ddaa-4f03-8bb8-f54f5dc7edcf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618067855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1618067855 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/48.kmac_sideload.1997518771
Short name T413
Test name
Test status
Simulation time 30146339932 ps
CPU time 277.72 seconds
Started Jan 21 02:17:14 PM PST 24
Finished Jan 21 02:21:53 PM PST 24
Peak memory 243908 kb
Host smart-ff564b02-00ec-47f8-be52-4410ae491ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997518771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1997518771 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest


Test location /workspace/coverage/default/48.kmac_smoke.4125684338
Short name T310
Test name
Test status
Simulation time 1380597936 ps
CPU time 34.27 seconds
Started Jan 21 02:17:04 PM PST 24
Finished Jan 21 02:17:39 PM PST 24
Peak memory 218116 kb
Host smart-fa97d411-7ac5-476c-ab42-a79b5e861e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125684338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.4125684338 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest


Test location /workspace/coverage/default/48.kmac_stress_all.251153915
Short name T916
Test name
Test status
Simulation time 60508484993 ps
CPU time 860.63 seconds
Started Jan 21 02:17:45 PM PST 24
Finished Jan 21 02:32:06 PM PST 24
Peak memory 333820 kb
Host smart-14d8e67e-b0c8-46e9-93fd-ee715e3ab231
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=251153915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.251153915 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest


Test location /workspace/coverage/default/48.kmac_stress_all_with_rand_reset.3795824200
Short name T1118
Test name
Test status
Simulation time 219248610588 ps
CPU time 1454.4 seconds
Started Jan 21 02:31:29 PM PST 24
Finished Jan 21 02:55:49 PM PST 24
Peak memory 345996 kb
Host smart-173c2f72-7f54-4ffa-92fd-90a12aa6c808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795824200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.3795824200 +e
nable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.1836984088
Short name T870
Test name
Test status
Simulation time 338540024 ps
CPU time 4.52 seconds
Started Jan 21 03:42:04 PM PST 24
Finished Jan 21 03:42:09 PM PST 24
Peak memory 208640 kb
Host smart-2176a7c4-4a23-4e5d-a4ea-4ec815cda6c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836984088 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.1836984088 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2561612156
Short name T846
Test name
Test status
Simulation time 252063423 ps
CPU time 5.05 seconds
Started Jan 21 02:17:31 PM PST 24
Finished Jan 21 02:17:38 PM PST 24
Peak memory 208520 kb
Host smart-f991a621-6cda-4244-a4b4-52a41b793531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561612156 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2561612156 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.1254129446
Short name T565
Test name
Test status
Simulation time 98066958665 ps
CPU time 2054.43 seconds
Started Jan 21 02:17:16 PM PST 24
Finished Jan 21 02:51:31 PM PST 24
Peak memory 395384 kb
Host smart-3dab88e6-a8c8-420c-82bc-e9cf7d7f92ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1254129446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.1254129446 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.4244313500
Short name T1087
Test name
Test status
Simulation time 41006350542 ps
CPU time 1491.79 seconds
Started Jan 21 02:17:15 PM PST 24
Finished Jan 21 02:42:08 PM PST 24
Peak memory 387008 kb
Host smart-c9ac591e-790b-4ddf-8202-6114717204d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4244313500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.4244313500 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.2228314904
Short name T704
Test name
Test status
Simulation time 46962482080 ps
CPU time 1298.69 seconds
Started Jan 21 02:37:38 PM PST 24
Finished Jan 21 02:59:17 PM PST 24
Peak memory 329336 kb
Host smart-51feaae0-f28b-4f6e-986e-3f3a99eee6d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2228314904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.2228314904 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1389151728
Short name T185
Test name
Test status
Simulation time 176578321254 ps
CPU time 1049.44 seconds
Started Jan 21 02:41:44 PM PST 24
Finished Jan 21 02:59:14 PM PST 24
Peak memory 290224 kb
Host smart-55f960e9-3f71-4763-b799-f86fe43eb2de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1389151728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1389151728 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.2789525497
Short name T702
Test name
Test status
Simulation time 117475646387 ps
CPU time 4131.13 seconds
Started Jan 21 02:17:23 PM PST 24
Finished Jan 21 03:26:16 PM PST 24
Peak memory 643144 kb
Host smart-d4ce7632-83ab-4deb-bbee-8d8fd1098c50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2789525497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2789525497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.2651055934
Short name T349
Test name
Test status
Simulation time 172963489988 ps
CPU time 3494.41 seconds
Started Jan 21 02:17:31 PM PST 24
Finished Jan 21 03:15:47 PM PST 24
Peak memory 560576 kb
Host smart-7aa67e38-f9a4-419e-8765-26d61c6b7f62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2651055934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.2651055934 +enable_masking=0 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/49.kmac_alert_test.4276404347
Short name T50
Test name
Test status
Simulation time 57125534 ps
CPU time 0.82 seconds
Started Jan 21 02:18:34 PM PST 24
Finished Jan 21 02:18:40 PM PST 24
Peak memory 207304 kb
Host smart-ce9f8431-5b05-40c4-8038-b02dc19a90e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276404347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.4276404347 +enable
_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest


Test location /workspace/coverage/default/49.kmac_app.314120494
Short name T470
Test name
Test status
Simulation time 8232465796 ps
CPU time 153.21 seconds
Started Jan 21 02:18:33 PM PST 24
Finished Jan 21 02:21:08 PM PST 24
Peak memory 233228 kb
Host smart-9126270b-ee0b-4626-a5b3-f0f482ac4dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314120494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.314120494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest


Test location /workspace/coverage/default/49.kmac_burst_write.2645802137
Short name T507
Test name
Test status
Simulation time 14914120915 ps
CPU time 490.89 seconds
Started Jan 21 03:02:53 PM PST 24
Finished Jan 21 03:11:05 PM PST 24
Peak memory 229992 kb
Host smart-eee53c56-2514-48af-a450-5fa906634ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645802137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2645802137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest


Test location /workspace/coverage/default/49.kmac_entropy_refresh.1464233435
Short name T564
Test name
Test status
Simulation time 8337410584 ps
CPU time 280.51 seconds
Started Jan 21 02:18:33 PM PST 24
Finished Jan 21 02:23:16 PM PST 24
Peak memory 244788 kb
Host smart-0c6d80c3-fbb2-4643-9f0d-3f3e557abbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464233435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1464233435 +enable_masking=0 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/49.kmac_error.2531028267
Short name T485
Test name
Test status
Simulation time 4970114291 ps
CPU time 22.44 seconds
Started Jan 21 02:18:35 PM PST 24
Finished Jan 21 02:19:03 PM PST 24
Peak memory 223768 kb
Host smart-33388ed2-bad7-4fd5-8b26-91a2a39e41f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531028267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.2531028267 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest


Test location /workspace/coverage/default/49.kmac_key_error.3821301493
Short name T815
Test name
Test status
Simulation time 8168685105 ps
CPU time 8.37 seconds
Started Jan 21 02:18:36 PM PST 24
Finished Jan 21 02:18:50 PM PST 24
Peak memory 207444 kb
Host smart-e83b2faf-0036-4dea-a209-3d2643eefdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821301493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3821301493 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest


Test location /workspace/coverage/default/49.kmac_lc_escalation.2050574833
Short name T514
Test name
Test status
Simulation time 131867164 ps
CPU time 1.21 seconds
Started Jan 21 02:27:21 PM PST 24
Finished Jan 21 02:27:23 PM PST 24
Peak memory 216228 kb
Host smart-511a8351-365a-4d46-9692-098d44dfe19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050574833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2050574833 +enable_masking=0 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest


Test location /workspace/coverage/default/49.kmac_long_msg_and_output.1527021345
Short name T775
Test name
Test status
Simulation time 10662333041 ps
CPU time 878.38 seconds
Started Jan 21 02:41:56 PM PST 24
Finished Jan 21 02:56:35 PM PST 24
Peak memory 312084 kb
Host smart-823f2be8-31c3-49b3-bdb2-80ad42ebb175
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527021345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.1527021345 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/49.kmac_sideload.2783539685
Short name T648
Test name
Test status
Simulation time 5249250955 ps
CPU time 129.85 seconds
Started Jan 21 02:31:14 PM PST 24
Finished Jan 21 02:33:25 PM PST 24
Peak memory 231332 kb
Host smart-ff002cad-7e98-480d-9c91-ebc054ba728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783539685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2783539685 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest


Test location /workspace/coverage/default/49.kmac_smoke.450207963
Short name T915
Test name
Test status
Simulation time 2565458883 ps
CPU time 49.31 seconds
Started Jan 21 02:17:51 PM PST 24
Finished Jan 21 02:18:41 PM PST 24
Peak memory 218636 kb
Host smart-e9dc8663-d65a-4a44-a386-20767281c751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450207963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.450207963 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest


Test location /workspace/coverage/default/49.kmac_stress_all.1886106132
Short name T758
Test name
Test status
Simulation time 16359291594 ps
CPU time 926.67 seconds
Started Jan 21 02:39:56 PM PST 24
Finished Jan 21 02:55:24 PM PST 24
Peak memory 341668 kb
Host smart-61cd1199-bfc5-4621-bba7-0a048547edec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1886106132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1886106132 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest


Test location /workspace/coverage/default/49.kmac_stress_all_with_rand_reset.11635252
Short name T411
Test name
Test status
Simulation time 31981665884 ps
CPU time 778.52 seconds
Started Jan 21 02:18:34 PM PST 24
Finished Jan 21 02:31:34 PM PST 24
Peak memory 302000 kb
Host smart-199440ee-2450-4dda-9b8f-e2c195c593ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11635252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.11635252 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.2836750553
Short name T1055
Test name
Test status
Simulation time 354835664 ps
CPU time 4.94 seconds
Started Jan 21 02:18:25 PM PST 24
Finished Jan 21 02:18:31 PM PST 24
Peak memory 217192 kb
Host smart-a8b8bccb-0142-4a76-a41e-ef67baf1b72c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836750553 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.2836750553 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2476341137
Short name T203
Test name
Test status
Simulation time 1024310937 ps
CPU time 5.45 seconds
Started Jan 21 02:18:36 PM PST 24
Finished Jan 21 02:18:47 PM PST 24
Peak memory 208940 kb
Host smart-d2d4af77-11e0-47f7-8e17-ad5d2cd9b40d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476341137 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2476341137 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1792857993
Short name T326
Test name
Test status
Simulation time 134638680127 ps
CPU time 1953.89 seconds
Started Jan 21 02:17:53 PM PST 24
Finished Jan 21 02:50:28 PM PST 24
Peak memory 397812 kb
Host smart-6560dfff-6ecb-4d4a-b09e-9997525f5a72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1792857993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1792857993 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.874416816
Short name T956
Test name
Test status
Simulation time 885845285045 ps
CPU time 1838.5 seconds
Started Jan 21 03:01:54 PM PST 24
Finished Jan 21 03:32:36 PM PST 24
Peak memory 375592 kb
Host smart-d9115006-b236-43f5-a7f6-5bcd59805e95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=874416816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.874416816 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.4219522837
Short name T914
Test name
Test status
Simulation time 28177342396 ps
CPU time 1134.87 seconds
Started Jan 21 02:17:52 PM PST 24
Finished Jan 21 02:36:47 PM PST 24
Peak memory 338252 kb
Host smart-85d0b734-6ca9-42cc-8133-1aa79dfa3ff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4219522837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.4219522837 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.898506203
Short name T218
Test name
Test status
Simulation time 248162884428 ps
CPU time 908.28 seconds
Started Jan 21 02:31:16 PM PST 24
Finished Jan 21 02:46:26 PM PST 24
Peak memory 291772 kb
Host smart-305fb55b-4d81-4675-b1e9-1858e12bdaf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=898506203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.898506203 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.2641118483
Short name T239
Test name
Test status
Simulation time 266392820148 ps
CPU time 5451.08 seconds
Started Jan 21 03:15:50 PM PST 24
Finished Jan 21 04:46:44 PM PST 24
Peak memory 647084 kb
Host smart-958bb7a9-d1a2-4cac-9ffe-0238c03fc382
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2641118483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.2641118483 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.716097494
Short name T330
Test name
Test status
Simulation time 173769760274 ps
CPU time 3484.87 seconds
Started Jan 21 02:42:13 PM PST 24
Finished Jan 21 03:40:18 PM PST 24
Peak memory 564364 kb
Host smart-525edf20-2dc7-4df9-bb4a-000544359b05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=716097494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.716097494 +enable_masking=0 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/5.kmac_alert_test.4281443601
Short name T831
Test name
Test status
Simulation time 25788286 ps
CPU time 0.77 seconds
Started Jan 21 01:48:03 PM PST 24
Finished Jan 21 01:48:05 PM PST 24
Peak memory 207212 kb
Host smart-5fbeac4a-26f6-4795-9e0f-962f046b9a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281443601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.4281443601 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest


Test location /workspace/coverage/default/5.kmac_app.3902553852
Short name T1144
Test name
Test status
Simulation time 56667318451 ps
CPU time 219.28 seconds
Started Jan 21 03:18:03 PM PST 24
Finished Jan 21 03:21:44 PM PST 24
Peak memory 237092 kb
Host smart-24a51db8-7ace-472a-b06b-bc293347ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902553852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3902553852 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest


Test location /workspace/coverage/default/5.kmac_app_with_partial_data.2366037805
Short name T399
Test name
Test status
Simulation time 32565649385 ps
CPU time 254.65 seconds
Started Jan 21 02:05:47 PM PST 24
Finished Jan 21 02:10:03 PM PST 24
Peak memory 240580 kb
Host smart-919648a8-4c6c-4026-8535-2b5b4a34164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366037805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2366037805 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/5.kmac_burst_write.325177225
Short name T1043
Test name
Test status
Simulation time 7885057816 ps
CPU time 641.05 seconds
Started Jan 21 02:54:58 PM PST 24
Finished Jan 21 03:05:40 PM PST 24
Peak memory 230048 kb
Host smart-ea932d1e-a4d1-42c5-a0ed-6d06668f0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325177225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.325177225 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest


Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2795349244
Short name T656
Test name
Test status
Simulation time 108625141 ps
CPU time 7.24 seconds
Started Jan 21 01:48:05 PM PST 24
Finished Jan 21 01:48:13 PM PST 24
Peak memory 220128 kb
Host smart-c15a5138-39db-4e20-8364-3242870739d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2795349244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2795349244 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/5.kmac_entropy_mode_error.3332271381
Short name T607
Test name
Test status
Simulation time 6924221076 ps
CPU time 33.97 seconds
Started Jan 21 02:08:24 PM PST 24
Finished Jan 21 02:08:58 PM PST 24
Peak memory 223704 kb
Host smart-19d5a38e-b1b6-4135-8be0-d83811356348
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3332271381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3332271381 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/5.kmac_entropy_ready_error.466532897
Short name T863
Test name
Test status
Simulation time 3062671666 ps
CPU time 26.56 seconds
Started Jan 21 03:05:04 PM PST 24
Finished Jan 21 03:05:33 PM PST 24
Peak memory 223900 kb
Host smart-e384c9cb-1b40-437e-b339-902cc55a1e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466532897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.466532897 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/5.kmac_entropy_refresh.4052658800
Short name T1110
Test name
Test status
Simulation time 53345883308 ps
CPU time 246.08 seconds
Started Jan 21 01:59:51 PM PST 24
Finished Jan 21 02:03:57 PM PST 24
Peak memory 240560 kb
Host smart-6510bd17-48c5-4240-805f-5174159f3bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052658800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.4052658800 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/5.kmac_error.843110255
Short name T643
Test name
Test status
Simulation time 25309789382 ps
CPU time 176.57 seconds
Started Jan 21 01:47:56 PM PST 24
Finished Jan 21 01:50:53 PM PST 24
Peak memory 253584 kb
Host smart-889f1650-ae39-4238-8afe-690c82f8e654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843110255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.843110255 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest


Test location /workspace/coverage/default/5.kmac_key_error.470607497
Short name T521
Test name
Test status
Simulation time 558991354 ps
CPU time 1.48 seconds
Started Jan 21 01:48:08 PM PST 24
Finished Jan 21 01:48:11 PM PST 24
Peak memory 207500 kb
Host smart-0df772d7-ad5b-4571-be66-19c7cee62711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470607497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.470607497 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest


Test location /workspace/coverage/default/5.kmac_lc_escalation.1244385711
Short name T736
Test name
Test status
Simulation time 37673374 ps
CPU time 1.24 seconds
Started Jan 21 01:48:05 PM PST 24
Finished Jan 21 01:48:07 PM PST 24
Peak memory 215848 kb
Host smart-3e603ca9-5f81-4f4f-a75d-045d82290ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244385711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1244385711 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest


Test location /workspace/coverage/default/5.kmac_long_msg_and_output.2093376835
Short name T45
Test name
Test status
Simulation time 4064451501 ps
CPU time 356.42 seconds
Started Jan 21 02:27:43 PM PST 24
Finished Jan 21 02:33:40 PM PST 24
Peak memory 256044 kb
Host smart-a54ace44-6284-4991-a021-d362de806d30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093376835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.2093376835 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/5.kmac_mubi.4001992245
Short name T734
Test name
Test status
Simulation time 5929129456 ps
CPU time 203.31 seconds
Started Jan 21 01:47:56 PM PST 24
Finished Jan 21 01:51:20 PM PST 24
Peak memory 241116 kb
Host smart-306712ac-ed85-4ef4-aebd-4311da658693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001992245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.4001992245 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest


Test location /workspace/coverage/default/5.kmac_sideload.4194083128
Short name T819
Test name
Test status
Simulation time 11490033024 ps
CPU time 313.9 seconds
Started Jan 21 01:47:45 PM PST 24
Finished Jan 21 01:52:59 PM PST 24
Peak memory 243160 kb
Host smart-35e9d3ff-f3bf-4c02-9b1a-3b0faab064db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194083128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.4194083128 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest


Test location /workspace/coverage/default/5.kmac_smoke.3049270070
Short name T615
Test name
Test status
Simulation time 634754412 ps
CPU time 10.64 seconds
Started Jan 21 01:47:49 PM PST 24
Finished Jan 21 01:48:01 PM PST 24
Peak memory 217296 kb
Host smart-9b2d09c0-63ca-46a6-b049-a08dc9b9cbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049270070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3049270070 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest


Test location /workspace/coverage/default/5.kmac_stress_all.364993382
Short name T642
Test name
Test status
Simulation time 18435029965 ps
CPU time 350.51 seconds
Started Jan 21 02:54:53 PM PST 24
Finished Jan 21 03:00:44 PM PST 24
Peak memory 256592 kb
Host smart-aa5bf632-584b-4271-aaed-7ff1a3f8c1d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=364993382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.364993382 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest


Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.1640690243
Short name T345
Test name
Test status
Simulation time 107046705110 ps
CPU time 682.99 seconds
Started Jan 21 01:48:05 PM PST 24
Finished Jan 21 01:59:28 PM PST 24
Peak memory 256488 kb
Host smart-442dbea7-157b-4647-916a-9e50f82c666c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640690243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.1640690243 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.1769712512
Short name T204
Test name
Test status
Simulation time 282084873 ps
CPU time 4.03 seconds
Started Jan 21 01:47:54 PM PST 24
Finished Jan 21 01:47:59 PM PST 24
Peak memory 208448 kb
Host smart-33140426-abf8-4c1c-a769-faab48d80072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769712512 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.1769712512 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.569459069
Short name T355
Test name
Test status
Simulation time 227486905 ps
CPU time 4.01 seconds
Started Jan 21 01:47:57 PM PST 24
Finished Jan 21 01:48:01 PM PST 24
Peak memory 217304 kb
Host smart-89d97192-5a12-4ad2-847b-6507148e61c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569459069 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.kmac_test_vectors_kmac_xof.569459069 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.2251786024
Short name T544
Test name
Test status
Simulation time 100114308295 ps
CPU time 2024.62 seconds
Started Jan 21 03:08:15 PM PST 24
Finished Jan 21 03:42:02 PM PST 24
Peak memory 386876 kb
Host smart-825000a8-d570-42af-bc55-c3a0d830391d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2251786024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2251786024 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.1774831516
Short name T456
Test name
Test status
Simulation time 61405306687 ps
CPU time 1840.33 seconds
Started Jan 21 02:35:50 PM PST 24
Finished Jan 21 03:06:31 PM PST 24
Peak memory 372284 kb
Host smart-b8c86175-6d8c-4bff-81e1-fda8eb62c581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1774831516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1774831516 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.4083048727
Short name T886
Test name
Test status
Simulation time 72681060901 ps
CPU time 1450.54 seconds
Started Jan 21 02:07:12 PM PST 24
Finished Jan 21 02:31:34 PM PST 24
Peak memory 338168 kb
Host smart-7c994cb2-fd1c-41ae-9738-739dfe49c95a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4083048727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.4083048727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.3316869853
Short name T356
Test name
Test status
Simulation time 38082743468 ps
CPU time 756.42 seconds
Started Jan 21 01:47:44 PM PST 24
Finished Jan 21 02:00:21 PM PST 24
Peak memory 294520 kb
Host smart-083577fa-fed6-41e2-a137-9a10412145f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3316869853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.3316869853 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.538981812
Short name T412
Test name
Test status
Simulation time 205610070691 ps
CPU time 4180.38 seconds
Started Jan 21 02:14:58 PM PST 24
Finished Jan 21 03:24:41 PM PST 24
Peak memory 660624 kb
Host smart-382dca12-d2f1-4c5d-9a87-62e37aa5d217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=538981812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.538981812 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.972074463
Short name T154
Test name
Test status
Simulation time 188971306785 ps
CPU time 3634.98 seconds
Started Jan 21 01:47:57 PM PST 24
Finished Jan 21 02:48:33 PM PST 24
Peak memory 565992 kb
Host smart-341bcde9-5f45-4cbc-b34b-97003dff36b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=972074463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.972074463 +enable_masking=0 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/6.kmac_alert_test.3669096970
Short name T947
Test name
Test status
Simulation time 57689008 ps
CPU time 0.85 seconds
Started Jan 21 01:48:28 PM PST 24
Finished Jan 21 01:48:29 PM PST 24
Peak memory 207316 kb
Host smart-b982b7fa-0ba5-49c0-935f-a5b2e5dabebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669096970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3669096970 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest


Test location /workspace/coverage/default/6.kmac_app.84768122
Short name T498
Test name
Test status
Simulation time 15953012987 ps
CPU time 95.41 seconds
Started Jan 21 01:48:13 PM PST 24
Finished Jan 21 01:49:49 PM PST 24
Peak memory 229224 kb
Host smart-ecff6b02-5a4c-4968-a497-18f2809cbd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84768122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.84768122 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest


Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1674778078
Short name T877
Test name
Test status
Simulation time 8585755336 ps
CPU time 116.37 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 01:50:09 PM PST 24
Peak memory 230836 kb
Host smart-6430cc64-3125-493c-aa24-f227cc496fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674778078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1674778078 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/6.kmac_burst_write.2270125449
Short name T631
Test name
Test status
Simulation time 21420299642 ps
CPU time 716.19 seconds
Started Jan 21 01:48:13 PM PST 24
Finished Jan 21 02:00:10 PM PST 24
Peak memory 232160 kb
Host smart-805ac721-04fa-4b8e-9b41-0c499aca759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270125449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2270125449 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest


Test location /workspace/coverage/default/6.kmac_edn_timeout_error.4025281020
Short name T795
Test name
Test status
Simulation time 111305890 ps
CPU time 8.3 seconds
Started Jan 21 01:48:15 PM PST 24
Finished Jan 21 01:48:23 PM PST 24
Peak memory 219084 kb
Host smart-c6e86adc-7628-4919-9399-eeefa27d2260
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025281020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.4025281020 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1657697921
Short name T287
Test name
Test status
Simulation time 860738377 ps
CPU time 13.41 seconds
Started Jan 21 01:48:25 PM PST 24
Finished Jan 21 01:48:39 PM PST 24
Peak memory 215728 kb
Host smart-f66dc097-75e2-4616-9b44-19efd5e1272d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1657697921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1657697921 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/6.kmac_entropy_ready_error.3286538839
Short name T318
Test name
Test status
Simulation time 5663811120 ps
CPU time 27.99 seconds
Started Jan 21 01:48:25 PM PST 24
Finished Jan 21 01:48:54 PM PST 24
Peak memory 218184 kb
Host smart-7267274d-8cdb-4881-bba2-d2ac3de983bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286538839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3286538839 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/6.kmac_entropy_refresh.486330935
Short name T754
Test name
Test status
Simulation time 2021184927 ps
CPU time 17.26 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 01:48:30 PM PST 24
Peak memory 223032 kb
Host smart-88db7621-4ef0-41a6-9b98-86f2ea4a74b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486330935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.486330935 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/6.kmac_error.2965285299
Short name T873
Test name
Test status
Simulation time 1279403626 ps
CPU time 93.11 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 01:49:45 PM PST 24
Peak memory 233904 kb
Host smart-bb176125-cb2e-438e-b40c-4e0e8e912b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965285299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2965285299 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest


Test location /workspace/coverage/default/6.kmac_key_error.1382576175
Short name T575
Test name
Test status
Simulation time 1254767133 ps
CPU time 2.43 seconds
Started Jan 21 02:20:29 PM PST 24
Finished Jan 21 02:20:33 PM PST 24
Peak memory 207572 kb
Host smart-f8721d3a-0d18-403a-9d3d-123e40b9fd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382576175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1382576175 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest


Test location /workspace/coverage/default/6.kmac_lc_escalation.2374254347
Short name T620
Test name
Test status
Simulation time 26918989 ps
CPU time 1.23 seconds
Started Jan 21 01:48:20 PM PST 24
Finished Jan 21 01:48:22 PM PST 24
Peak memory 215956 kb
Host smart-3a04ed98-3c40-42e5-8d1d-37734b4041c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374254347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2374254347 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest


Test location /workspace/coverage/default/6.kmac_long_msg_and_output.4294098165
Short name T306
Test name
Test status
Simulation time 965951578130 ps
CPU time 2750.68 seconds
Started Jan 21 01:48:07 PM PST 24
Finished Jan 21 02:33:59 PM PST 24
Peak memory 467136 kb
Host smart-ee3a7ed8-a660-4eb4-a5ae-f3a8cd4bdd36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294098165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.4294098165 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/6.kmac_mubi.17479703
Short name T366
Test name
Test status
Simulation time 17469617699 ps
CPU time 229.17 seconds
Started Jan 21 01:48:14 PM PST 24
Finished Jan 21 01:52:04 PM PST 24
Peak memory 243944 kb
Host smart-ac9178fe-8079-482d-a7b0-7468e69d1d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17479703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.17479703 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest


Test location /workspace/coverage/default/6.kmac_sideload.74676269
Short name T668
Test name
Test status
Simulation time 919211128 ps
CPU time 68.07 seconds
Started Jan 21 02:36:10 PM PST 24
Finished Jan 21 02:37:19 PM PST 24
Peak memory 223908 kb
Host smart-c895b5f4-dd69-44d1-b322-89d5a8227c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74676269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.74676269 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest


Test location /workspace/coverage/default/6.kmac_smoke.1972804404
Short name T464
Test name
Test status
Simulation time 4423675241 ps
CPU time 36.4 seconds
Started Jan 21 01:48:02 PM PST 24
Finished Jan 21 01:48:39 PM PST 24
Peak memory 218376 kb
Host smart-699ab593-018d-42a9-939c-2ef5dae80536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972804404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1972804404 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest


Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.1087775807
Short name T1104
Test name
Test status
Simulation time 71869650955 ps
CPU time 1967.54 seconds
Started Jan 21 01:48:21 PM PST 24
Finished Jan 21 02:21:10 PM PST 24
Peak memory 415944 kb
Host smart-8f7806cd-8531-4044-916c-73e737ab3ca2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087775807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.1087775807 +en
able_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3605355328
Short name T777
Test name
Test status
Simulation time 530663942 ps
CPU time 4.96 seconds
Started Jan 21 01:48:14 PM PST 24
Finished Jan 21 01:48:20 PM PST 24
Peak memory 216608 kb
Host smart-42c5aa2e-a803-4e88-a8a5-34a1fd03e9fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605355328 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3605355328 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.2833167646
Short name T924
Test name
Test status
Simulation time 61904670 ps
CPU time 3.99 seconds
Started Jan 21 01:48:13 PM PST 24
Finished Jan 21 01:48:18 PM PST 24
Peak memory 208956 kb
Host smart-685a5fb8-ad2f-4cd9-80b1-96b41ffed3ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833167646 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.2833167646 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.2159232320
Short name T1114
Test name
Test status
Simulation time 76471295368 ps
CPU time 1701.26 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 02:16:35 PM PST 24
Peak memory 397688 kb
Host smart-53a53bfe-2fa4-42ef-8b76-4c3410ca00c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2159232320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2159232320 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.246784870
Short name T308
Test name
Test status
Simulation time 206398438806 ps
CPU time 1675.2 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 02:16:09 PM PST 24
Peak memory 378504 kb
Host smart-26fc6752-54c6-4dee-ba61-a53287a1565f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=246784870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.246784870 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.1281780659
Short name T73
Test name
Test status
Simulation time 51584421661 ps
CPU time 1297.75 seconds
Started Jan 21 02:12:18 PM PST 24
Finished Jan 21 02:33:57 PM PST 24
Peak memory 331828 kb
Host smart-e6acd95b-c8ec-4bb3-b28f-9b32d33aa2c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1281780659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1281780659 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.2350738809
Short name T810
Test name
Test status
Simulation time 200279861021 ps
CPU time 967.8 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 02:04:21 PM PST 24
Peak memory 291168 kb
Host smart-5ead9c3f-92c7-4e4a-8dbd-945073694bd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2350738809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2350738809 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.353916073
Short name T376
Test name
Test status
Simulation time 51326787034 ps
CPU time 4234.59 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 02:58:47 PM PST 24
Peak memory 659268 kb
Host smart-213bd786-42d0-4d84-9dbc-c733db5993c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=353916073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.353916073 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1335997877
Short name T1071
Test name
Test status
Simulation time 88004405765 ps
CPU time 3504.13 seconds
Started Jan 21 01:48:12 PM PST 24
Finished Jan 21 02:46:37 PM PST 24
Peak memory 557996 kb
Host smart-df9bd292-7d2c-4ac7-a2c5-21f6fba61536
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1335997877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1335997877 +enable_masking=0 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/7.kmac_alert_test.4164142869
Short name T388
Test name
Test status
Simulation time 22584430 ps
CPU time 0.75 seconds
Started Jan 21 01:48:52 PM PST 24
Finished Jan 21 01:48:53 PM PST 24
Peak memory 207212 kb
Host smart-1b6cd4f7-2dc1-49b2-ab92-50a064ac1894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164142869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.4164142869 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest


Test location /workspace/coverage/default/7.kmac_app.1170705938
Short name T319
Test name
Test status
Simulation time 716261594 ps
CPU time 21.6 seconds
Started Jan 21 01:48:32 PM PST 24
Finished Jan 21 01:48:54 PM PST 24
Peak memory 223836 kb
Host smart-82085300-f904-4d3c-aefe-22d2477887aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170705938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1170705938 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest


Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1928862564
Short name T676
Test name
Test status
Simulation time 27234793898 ps
CPU time 277.7 seconds
Started Jan 21 01:48:33 PM PST 24
Finished Jan 21 01:53:11 PM PST 24
Peak memory 244064 kb
Host smart-7935a3e1-61c3-409c-a7e3-6c3ac58ec7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928862564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1928862564 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/7.kmac_burst_write.1323211423
Short name T531
Test name
Test status
Simulation time 27008081565 ps
CPU time 527.23 seconds
Started Jan 21 01:48:22 PM PST 24
Finished Jan 21 01:57:10 PM PST 24
Peak memory 229572 kb
Host smart-d226a583-c535-46b9-af0d-2df14779f9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323211423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1323211423 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest


Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1139810555
Short name T549
Test name
Test status
Simulation time 389617148 ps
CPU time 7.46 seconds
Started Jan 21 01:48:42 PM PST 24
Finished Jan 21 01:48:50 PM PST 24
Peak memory 218684 kb
Host smart-21b042e1-3f9a-49c6-bd14-a667c5b36a60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1139810555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1139810555 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/7.kmac_entropy_mode_error.4270912433
Short name T553
Test name
Test status
Simulation time 6765836996 ps
CPU time 39.74 seconds
Started Jan 21 01:48:42 PM PST 24
Finished Jan 21 01:49:23 PM PST 24
Peak memory 223540 kb
Host smart-aa0c898b-3fcc-42bf-86f1-85dc300f3fd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4270912433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.4270912433 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/7.kmac_entropy_ready_error.2722906714
Short name T300
Test name
Test status
Simulation time 15419120261 ps
CPU time 48.57 seconds
Started Jan 21 01:48:47 PM PST 24
Finished Jan 21 01:49:37 PM PST 24
Peak memory 221424 kb
Host smart-498ee262-07a6-483b-8924-8950d1c2a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722906714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2722906714 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/7.kmac_entropy_refresh.3347169986
Short name T921
Test name
Test status
Simulation time 2845268037 ps
CPU time 40.36 seconds
Started Jan 21 01:48:31 PM PST 24
Finished Jan 21 01:49:12 PM PST 24
Peak memory 223900 kb
Host smart-6b8e97d4-287f-46c1-a7ce-0b68301e5bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347169986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3347169986 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/7.kmac_error.1392491850
Short name T1039
Test name
Test status
Simulation time 4057598177 ps
CPU time 314.76 seconds
Started Jan 21 01:48:41 PM PST 24
Finished Jan 21 01:53:57 PM PST 24
Peak memory 256676 kb
Host smart-eab89403-80e5-4008-9d16-cc2c262a1759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392491850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1392491850 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest


Test location /workspace/coverage/default/7.kmac_key_error.1535560452
Short name T714
Test name
Test status
Simulation time 628239878 ps
CPU time 3.61 seconds
Started Jan 21 01:48:44 PM PST 24
Finished Jan 21 01:48:49 PM PST 24
Peak memory 207576 kb
Host smart-44e7dc69-80b7-4460-bcc1-b73315bfb499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535560452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1535560452 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest


Test location /workspace/coverage/default/7.kmac_lc_escalation.231642727
Short name T1028
Test name
Test status
Simulation time 132439053 ps
CPU time 1.14 seconds
Started Jan 21 01:48:41 PM PST 24
Finished Jan 21 01:48:43 PM PST 24
Peak memory 215924 kb
Host smart-03e12821-cbe8-4b06-be49-5f87f2300490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231642727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.231642727 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_lc_escalation/latest


Test location /workspace/coverage/default/7.kmac_long_msg_and_output.812549690
Short name T809
Test name
Test status
Simulation time 2691246855936 ps
CPU time 2978.05 seconds
Started Jan 21 01:48:21 PM PST 24
Finished Jan 21 02:38:01 PM PST 24
Peak memory 481528 kb
Host smart-6e8fb0b7-43fc-4a75-8716-0a07acbedf85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812549690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and
_output.812549690 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/7.kmac_mubi.1009357546
Short name T301
Test name
Test status
Simulation time 19440680185 ps
CPU time 139.51 seconds
Started Jan 21 01:48:45 PM PST 24
Finished Jan 21 01:51:06 PM PST 24
Peak memory 234200 kb
Host smart-fa65d1e3-a9b6-4b24-9b5b-3474d85f044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009357546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1009357546 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest


Test location /workspace/coverage/default/7.kmac_sideload.1336923942
Short name T812
Test name
Test status
Simulation time 72987753447 ps
CPU time 295.76 seconds
Started Jan 21 01:48:21 PM PST 24
Finished Jan 21 01:53:17 PM PST 24
Peak memory 241168 kb
Host smart-96944aa0-70ab-4ca9-a2aa-c85de0426df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336923942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1336923942 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest


Test location /workspace/coverage/default/7.kmac_smoke.656261294
Short name T323
Test name
Test status
Simulation time 2988806163 ps
CPU time 58.71 seconds
Started Jan 21 01:48:22 PM PST 24
Finished Jan 21 01:49:22 PM PST 24
Peak memory 219252 kb
Host smart-ec22fe3c-10a8-44f4-b4cf-d8600403dbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656261294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.656261294 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest


Test location /workspace/coverage/default/7.kmac_stress_all.742702368
Short name T210
Test name
Test status
Simulation time 11281002011 ps
CPU time 115.34 seconds
Started Jan 21 01:48:43 PM PST 24
Finished Jan 21 01:50:39 PM PST 24
Peak memory 234996 kb
Host smart-c1cbd441-4bfc-4707-9563-48c32ac0cbee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=742702368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.742702368 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest


Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.403049069
Short name T459
Test name
Test status
Simulation time 198675429102 ps
CPU time 1380.87 seconds
Started Jan 21 01:48:42 PM PST 24
Finished Jan 21 02:11:43 PM PST 24
Peak memory 292944 kb
Host smart-bed35f4e-42e6-48fe-855a-1275b91e5b48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403049069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.403049069 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.59227022
Short name T641
Test name
Test status
Simulation time 792693312 ps
CPU time 4.57 seconds
Started Jan 21 01:48:30 PM PST 24
Finished Jan 21 01:48:35 PM PST 24
Peak memory 208548 kb
Host smart-ab2be407-f5fb-4f74-9779-9d249d310357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59227022 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.kmac_test_vectors_kmac.59227022 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2701319191
Short name T187
Test name
Test status
Simulation time 237007478 ps
CPU time 3.8 seconds
Started Jan 21 01:48:30 PM PST 24
Finished Jan 21 01:48:35 PM PST 24
Peak memory 208988 kb
Host smart-7f2dcac8-4799-4566-b222-05ad5ddc2eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701319191 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2701319191 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2638499466
Short name T386
Test name
Test status
Simulation time 65296386840 ps
CPU time 1867.1 seconds
Started Jan 21 01:48:32 PM PST 24
Finished Jan 21 02:19:40 PM PST 24
Peak memory 393416 kb
Host smart-f21614cf-f6e1-422a-9e90-65a275515057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2638499466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2638499466 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.1093817343
Short name T973
Test name
Test status
Simulation time 18676085814 ps
CPU time 1423.74 seconds
Started Jan 21 01:48:28 PM PST 24
Finished Jan 21 02:12:13 PM PST 24
Peak memory 377780 kb
Host smart-3da69be1-b51c-4983-886f-4e0dc175d948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1093817343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1093817343 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.2757054781
Short name T1103
Test name
Test status
Simulation time 47255663344 ps
CPU time 1314.93 seconds
Started Jan 21 01:48:32 PM PST 24
Finished Jan 21 02:10:28 PM PST 24
Peak memory 336296 kb
Host smart-8810cc74-9214-40db-9556-5703eb313004
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2757054781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2757054781 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.2353104783
Short name T828
Test name
Test status
Simulation time 9420940681 ps
CPU time 785.78 seconds
Started Jan 21 01:48:33 PM PST 24
Finished Jan 21 02:01:39 PM PST 24
Peak memory 291088 kb
Host smart-71092afe-bdaf-4d65-9aad-52919cb5c524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2353104783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2353104783 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.1881182430
Short name T71
Test name
Test status
Simulation time 209597613285 ps
CPU time 4347.75 seconds
Started Jan 21 01:48:34 PM PST 24
Finished Jan 21 03:01:03 PM PST 24
Peak memory 682472 kb
Host smart-aa727a71-3235-4ab2-8a03-3bd3ed9ebc6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1881182430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.1881182430 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.3064793804
Short name T209
Test name
Test status
Simulation time 111379664280 ps
CPU time 3586.11 seconds
Started Jan 21 01:48:31 PM PST 24
Finished Jan 21 02:48:18 PM PST 24
Peak memory 564716 kb
Host smart-274126f6-71fa-41c1-8d90-207217d75bcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3064793804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.3064793804 +enable_masking=0 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/8.kmac_alert_test.2896734776
Short name T821
Test name
Test status
Simulation time 17493586 ps
CPU time 0.81 seconds
Started Jan 21 01:49:08 PM PST 24
Finished Jan 21 01:49:09 PM PST 24
Peak memory 207224 kb
Host smart-78748bef-240b-4761-b222-1046d370ec08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896734776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2896734776 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest


Test location /workspace/coverage/default/8.kmac_app.769355718
Short name T264
Test name
Test status
Simulation time 6397713560 ps
CPU time 60.16 seconds
Started Jan 21 01:48:57 PM PST 24
Finished Jan 21 01:49:58 PM PST 24
Peak memory 225204 kb
Host smart-b81fd502-a2a1-4b59-a7b3-e4c2adc0d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769355718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.769355718 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest


Test location /workspace/coverage/default/8.kmac_burst_write.1666758097
Short name T460
Test name
Test status
Simulation time 12356988721 ps
CPU time 275.97 seconds
Started Jan 21 01:48:48 PM PST 24
Finished Jan 21 01:53:25 PM PST 24
Peak memory 226248 kb
Host smart-3a80cd89-d300-45f3-8338-cac9046e5572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666758097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1666758097 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest


Test location /workspace/coverage/default/8.kmac_edn_timeout_error.4142191800
Short name T551
Test name
Test status
Simulation time 450197518 ps
CPU time 10.27 seconds
Started Jan 21 01:48:57 PM PST 24
Finished Jan 21 01:49:08 PM PST 24
Peak memory 219620 kb
Host smart-8830b0f8-caf4-44d7-a526-59726b392b37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4142191800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.4142191800 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/8.kmac_entropy_mode_error.1234634257
Short name T653
Test name
Test status
Simulation time 571602671 ps
CPU time 16.22 seconds
Started Jan 21 01:48:58 PM PST 24
Finished Jan 21 01:49:15 PM PST 24
Peak memory 222532 kb
Host smart-3af05b14-ffb1-4560-8f4d-f1a03986e3ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1234634257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1234634257 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/8.kmac_entropy_ready_error.1747059303
Short name T75
Test name
Test status
Simulation time 9043301997 ps
CPU time 41.96 seconds
Started Jan 21 01:49:09 PM PST 24
Finished Jan 21 01:49:52 PM PST 24
Peak memory 220792 kb
Host smart-14c315c6-1f1a-4f1d-bf6e-18afd220bfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747059303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1747059303 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/8.kmac_entropy_refresh.3367058094
Short name T577
Test name
Test status
Simulation time 39300744465 ps
CPU time 106.77 seconds
Started Jan 21 01:48:57 PM PST 24
Finished Jan 21 01:50:44 PM PST 24
Peak memory 228648 kb
Host smart-eb610fc4-a6bb-4f91-a7e6-a09024c0144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367058094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3367058094 +enable_masking=0 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/8.kmac_error.2686524769
Short name T511
Test name
Test status
Simulation time 1158527913 ps
CPU time 23.34 seconds
Started Jan 21 01:48:59 PM PST 24
Finished Jan 21 01:49:23 PM PST 24
Peak memory 232060 kb
Host smart-4a82a4c0-ff0b-4632-be4b-6c60d73ef89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686524769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2686524769 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest


Test location /workspace/coverage/default/8.kmac_key_error.1553103021
Short name T63
Test name
Test status
Simulation time 693900320 ps
CPU time 2.01 seconds
Started Jan 21 01:48:57 PM PST 24
Finished Jan 21 01:49:00 PM PST 24
Peak memory 207580 kb
Host smart-57c5034a-f50c-4756-b297-1cc672b38234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553103021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1553103021 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest


Test location /workspace/coverage/default/8.kmac_lc_escalation.3748317076
Short name T346
Test name
Test status
Simulation time 140836817 ps
CPU time 1.46 seconds
Started Jan 21 01:49:11 PM PST 24
Finished Jan 21 01:49:13 PM PST 24
Peak memory 215940 kb
Host smart-2e28e8b3-ae23-4ebc-8add-c6f0cecf6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748317076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3748317076 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest


Test location /workspace/coverage/default/8.kmac_long_msg_and_output.2935845352
Short name T486
Test name
Test status
Simulation time 34927236932 ps
CPU time 736.02 seconds
Started Jan 21 01:48:50 PM PST 24
Finished Jan 21 02:01:07 PM PST 24
Peak memory 285288 kb
Host smart-6e24f2e4-45ee-45ea-8d11-93c826bfa652
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935845352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.2935845352 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/8.kmac_mubi.1469419357
Short name T880
Test name
Test status
Simulation time 38082136917 ps
CPU time 229.67 seconds
Started Jan 21 01:48:57 PM PST 24
Finished Jan 21 01:52:47 PM PST 24
Peak memory 240500 kb
Host smart-ec324f15-f389-426e-af8e-190283908527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469419357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1469419357 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest


Test location /workspace/coverage/default/8.kmac_sideload.3789748692
Short name T367
Test name
Test status
Simulation time 5547664513 ps
CPU time 114.52 seconds
Started Jan 21 01:48:49 PM PST 24
Finished Jan 21 01:50:45 PM PST 24
Peak memory 228212 kb
Host smart-0f57a055-9f86-4c29-b897-cda3812ad2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789748692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3789748692 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest


Test location /workspace/coverage/default/8.kmac_smoke.2790917987
Short name T512
Test name
Test status
Simulation time 551203206 ps
CPU time 6.49 seconds
Started Jan 21 01:48:49 PM PST 24
Finished Jan 21 01:48:57 PM PST 24
Peak memory 217244 kb
Host smart-ec7bbb9e-88ba-42b8-9f5a-433c41be103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790917987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2790917987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest


Test location /workspace/coverage/default/8.kmac_stress_all.2027391437
Short name T270
Test name
Test status
Simulation time 1371410425 ps
CPU time 31.71 seconds
Started Jan 21 01:58:44 PM PST 24
Finished Jan 21 01:59:16 PM PST 24
Peak memory 236460 kb
Host smart-3de6d5fc-c288-4672-8289-2d04cf9a1636
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2027391437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2027391437 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest


Test location /workspace/coverage/default/8.kmac_stress_all_with_rand_reset.593820719
Short name T509
Test name
Test status
Simulation time 1312104309400 ps
CPU time 1738.3 seconds
Started Jan 21 01:49:08 PM PST 24
Finished Jan 21 02:18:08 PM PST 24
Peak memory 337012 kb
Host smart-c7d9ec48-8e93-413e-9d5c-64f55d58e684
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593820719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.593820719 +enab
le_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.1161984987
Short name T417
Test name
Test status
Simulation time 1334483095 ps
CPU time 4.79 seconds
Started Jan 21 01:48:49 PM PST 24
Finished Jan 21 01:48:55 PM PST 24
Peak memory 208988 kb
Host smart-57f2ad97-6427-483c-a83e-1325fd9132a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161984987 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.1161984987 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2045364393
Short name T721
Test name
Test status
Simulation time 378321568 ps
CPU time 4.64 seconds
Started Jan 21 01:49:00 PM PST 24
Finished Jan 21 01:49:05 PM PST 24
Peak memory 208508 kb
Host smart-97f45a6b-efcf-4f39-9661-1807da1230dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045364393 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2045364393 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.495738361
Short name T729
Test name
Test status
Simulation time 190695675660 ps
CPU time 1876.98 seconds
Started Jan 21 01:48:49 PM PST 24
Finished Jan 21 02:20:07 PM PST 24
Peak memory 370216 kb
Host smart-2c3e709c-7cbf-4954-b29e-1e030e070f5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=495738361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.495738361 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.3138650986
Short name T1082
Test name
Test status
Simulation time 61704157803 ps
CPU time 1719.88 seconds
Started Jan 21 01:48:49 PM PST 24
Finished Jan 21 02:17:30 PM PST 24
Peak memory 369216 kb
Host smart-82c39b77-c740-4008-b38c-811552dd4d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3138650986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.3138650986 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.2829924431
Short name T1018
Test name
Test status
Simulation time 97892189955 ps
CPU time 1386.65 seconds
Started Jan 21 01:48:50 PM PST 24
Finished Jan 21 02:11:58 PM PST 24
Peak memory 335124 kb
Host smart-86ec9d49-1f05-43ef-94e7-9332c202791f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2829924431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2829924431 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.1321139536
Short name T694
Test name
Test status
Simulation time 9419821848 ps
CPU time 784.81 seconds
Started Jan 21 01:48:52 PM PST 24
Finished Jan 21 02:01:58 PM PST 24
Peak memory 289176 kb
Host smart-8c9946aa-f7f9-4a32-b385-fa4dedcecfb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1321139536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1321139536 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.2334938447
Short name T518
Test name
Test status
Simulation time 721369621791 ps
CPU time 4970.34 seconds
Started Jan 21 01:48:49 PM PST 24
Finished Jan 21 03:11:41 PM PST 24
Peak memory 656696 kb
Host smart-dc36413e-5e50-4a7a-8443-28fac7980581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2334938447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.2334938447 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.1399543732
Short name T654
Test name
Test status
Simulation time 232085109662 ps
CPU time 4391.77 seconds
Started Jan 21 01:48:49 PM PST 24
Finished Jan 21 03:02:03 PM PST 24
Peak memory 557064 kb
Host smart-9b83b7ad-9563-45a0-8978-f7aa93eb3140
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1399543732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1399543732 +enable_masking=0 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest


Test location /workspace/coverage/default/9.kmac_alert_test.929488322
Short name T21
Test name
Test status
Simulation time 17998456 ps
CPU time 0.77 seconds
Started Jan 21 01:49:35 PM PST 24
Finished Jan 21 01:49:39 PM PST 24
Peak memory 207208 kb
Host smart-72c31a1d-24c2-40b5-95a4-71f980b750f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929488322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.929488322 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest


Test location /workspace/coverage/default/9.kmac_app.3435441627
Short name T909
Test name
Test status
Simulation time 8643998841 ps
CPU time 159.74 seconds
Started Jan 21 01:49:28 PM PST 24
Finished Jan 21 01:52:09 PM PST 24
Peak memory 234128 kb
Host smart-046c80c8-bce6-4f19-bfc2-75140ee107d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435441627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3435441627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest


Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3928051436
Short name T405
Test name
Test status
Simulation time 13208809176 ps
CPU time 204.97 seconds
Started Jan 21 01:49:26 PM PST 24
Finished Jan 21 01:52:52 PM PST 24
Peak memory 241704 kb
Host smart-8cdc59cb-eef6-4915-8f2a-e81f69def9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928051436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3928051436 +enable_
masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest


Test location /workspace/coverage/default/9.kmac_burst_write.417059748
Short name T604
Test name
Test status
Simulation time 69433280077 ps
CPU time 517.88 seconds
Started Jan 21 01:49:16 PM PST 24
Finished Jan 21 01:57:54 PM PST 24
Peak memory 230760 kb
Host smart-89a85866-1402-415c-94f6-4eb0ba9fbd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417059748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.417059748 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest


Test location /workspace/coverage/default/9.kmac_edn_timeout_error.3963047699
Short name T368
Test name
Test status
Simulation time 558633004 ps
CPU time 11.07 seconds
Started Jan 21 01:49:37 PM PST 24
Finished Jan 21 01:49:52 PM PST 24
Peak memory 222192 kb
Host smart-66fc67b4-436a-4a49-b7b5-06b72b05d730
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3963047699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3963047699 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest


Test location /workspace/coverage/default/9.kmac_entropy_mode_error.3107715010
Short name T1146
Test name
Test status
Simulation time 1555967486 ps
CPU time 29.58 seconds
Started Jan 21 02:10:22 PM PST 24
Finished Jan 21 02:10:53 PM PST 24
Peak memory 223556 kb
Host smart-7c5751cc-8181-4333-82cf-ffc91997c632
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3107715010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3107715010 +ena
ble_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest


Test location /workspace/coverage/default/9.kmac_entropy_ready_error.2260873438
Short name T32
Test name
Test status
Simulation time 685593380 ps
CPU time 11.1 seconds
Started Jan 21 01:49:37 PM PST 24
Finished Jan 21 01:49:50 PM PST 24
Peak memory 216040 kb
Host smart-6e2b17ed-00ed-414c-befa-10cc4651f3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260873438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2260873438 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest


Test location /workspace/coverage/default/9.kmac_entropy_refresh.767591176
Short name T321
Test name
Test status
Simulation time 2890540046 ps
CPU time 24.98 seconds
Started Jan 21 01:49:26 PM PST 24
Finished Jan 21 01:49:51 PM PST 24
Peak memory 223888 kb
Host smart-e1ffc47c-7a42-4a05-9933-a22561adce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767591176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.767591176 +enable_masking=0 +sw_
key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest


Test location /workspace/coverage/default/9.kmac_key_error.1168814196
Short name T1027
Test name
Test status
Simulation time 1309594438 ps
CPU time 2.11 seconds
Started Jan 21 01:49:37 PM PST 24
Finished Jan 21 01:49:43 PM PST 24
Peak memory 207392 kb
Host smart-76f5d551-3430-4327-9225-e89d738faf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168814196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1168814196 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest


Test location /workspace/coverage/default/9.kmac_lc_escalation.3270916485
Short name T9
Test name
Test status
Simulation time 106921915 ps
CPU time 1.15 seconds
Started Jan 21 01:49:36 PM PST 24
Finished Jan 21 01:49:39 PM PST 24
Peak memory 215876 kb
Host smart-cf63d89e-5869-4a5b-8cad-e51f0c059d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270916485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3270916485 +enable_masking=0 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest


Test location /workspace/coverage/default/9.kmac_long_msg_and_output.3149356374
Short name T568
Test name
Test status
Simulation time 90063943445 ps
CPU time 1351.96 seconds
Started Jan 21 01:49:16 PM PST 24
Finished Jan 21 02:11:49 PM PST 24
Peak memory 345988 kb
Host smart-217158dc-243b-4110-9435-7930a2dd978e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149356374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.3149356374 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest


Test location /workspace/coverage/default/9.kmac_mubi.3103784973
Short name T673
Test name
Test status
Simulation time 5767310385 ps
CPU time 131.82 seconds
Started Jan 21 01:49:24 PM PST 24
Finished Jan 21 01:51:37 PM PST 24
Peak memory 234424 kb
Host smart-d1a2b38f-7159-4762-a92f-cd2c5616a6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103784973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3103784973 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest


Test location /workspace/coverage/default/9.kmac_sideload.2234909861
Short name T1007
Test name
Test status
Simulation time 12702930410 ps
CPU time 76.4 seconds
Started Jan 21 01:49:17 PM PST 24
Finished Jan 21 01:50:34 PM PST 24
Peak memory 224356 kb
Host smart-614e9733-f082-4afe-9486-dc72aa478476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234909861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2234909861 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest


Test location /workspace/coverage/default/9.kmac_smoke.1839849665
Short name T1019
Test name
Test status
Simulation time 16436262178 ps
CPU time 69.47 seconds
Started Jan 21 01:49:05 PM PST 24
Finished Jan 21 01:50:15 PM PST 24
Peak memory 219156 kb
Host smart-1e0f2dd3-e086-4935-b2e1-4ed00a3f943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839849665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1839849665 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest


Test location /workspace/coverage/default/9.kmac_stress_all.262165166
Short name T691
Test name
Test status
Simulation time 65225322832 ps
CPU time 700.33 seconds
Started Jan 21 01:49:37 PM PST 24
Finished Jan 21 02:01:21 PM PST 24
Peak memory 330524 kb
Host smart-527eb9fa-39ca-4025-ac87-04d9f0683751
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=262165166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.262165166 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3847914689
Short name T936
Test name
Test status
Simulation time 691787883 ps
CPU time 4.49 seconds
Started Jan 21 01:49:26 PM PST 24
Finished Jan 21 01:49:31 PM PST 24
Peak memory 208464 kb
Host smart-785d6d02-775d-4283-85cf-d8f23da54713
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847914689 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3847914689 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.51459649
Short name T379
Test name
Test status
Simulation time 132217960 ps
CPU time 4.08 seconds
Started Jan 21 01:49:27 PM PST 24
Finished Jan 21 01:49:32 PM PST 24
Peak memory 217140 kb
Host smart-69bd66e6-bda3-4a63-9b24-d1770b2d1539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51459649 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.kmac_test_vectors_kmac_xof.51459649 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.3328724479
Short name T1108
Test name
Test status
Simulation time 110663387844 ps
CPU time 1598.69 seconds
Started Jan 21 01:49:15 PM PST 24
Finished Jan 21 02:15:55 PM PST 24
Peak memory 390416 kb
Host smart-1982c238-62a0-4b6c-828f-b092fc34748f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3328724479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.3328724479 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.3959777187
Short name T829
Test name
Test status
Simulation time 61653390983 ps
CPU time 1777.79 seconds
Started Jan 21 01:49:16 PM PST 24
Finished Jan 21 02:18:55 PM PST 24
Peak memory 375896 kb
Host smart-c92de08f-7f62-44fc-b194-259d5eebb402
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3959777187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.3959777187 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3727954056
Short name T76
Test name
Test status
Simulation time 49264673045 ps
CPU time 1378.91 seconds
Started Jan 21 01:49:15 PM PST 24
Finished Jan 21 02:12:15 PM PST 24
Peak memory 335972 kb
Host smart-27b7b0e0-ec0b-45b6-82fe-4d4d110f87fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3727954056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3727954056 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.3086785627
Short name T986
Test name
Test status
Simulation time 104899454995 ps
CPU time 991.42 seconds
Started Jan 21 01:49:16 PM PST 24
Finished Jan 21 02:05:48 PM PST 24
Peak memory 295936 kb
Host smart-415832d0-18fd-4175-90a4-7d3fca7255f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3086785627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3086785627 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.1421083664
Short name T566
Test name
Test status
Simulation time 253505938810 ps
CPU time 5167.56 seconds
Started Jan 21 01:49:19 PM PST 24
Finished Jan 21 03:15:28 PM PST 24
Peak memory 636148 kb
Host smart-13afdcee-c967-4e33-952b-5ed8f8649433
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1421083664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.1421083664 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest


Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.1475618109
Short name T728
Test name
Test status
Simulation time 44221065137 ps
CPU time 3427.16 seconds
Started Jan 21 01:49:16 PM PST 24
Finished Jan 21 02:46:24 PM PST 24
Peak memory 571656 kb
Host smart-278af9a7-b9c7-4eb2-9606-b282149d9f0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1475618109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1475618109 +enable_masking=0 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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