Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260673947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

208871829

1

T1

130

T2

751

T3

186

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	246620064	1			T1	122		T2	381		T3	127
values[0x0]	106921763	1			T1	73		T2	173		T3	61
values[0x1]	116003949	1			T1	127		T2	198		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202884533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

266661243

1

T1

212

T2

751

T3

204

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1512179	1			T1	1		T2	4		T59	3
valid_sources[0x01]	1410639	1			T2	5		T54	2		T65	6
valid_sources[0x02]	1383738	1			T1	2		T2	2		T65	7
valid_sources[0x03]	2070708	1			T2	2		T65	3		T97	2
valid_sources[0x04]	1399400	1			T2	1		T56	128		T54	2
valid_sources[0x05]	2158956	1			T1	1		T2	14		T54	3
valid_sources[0x06]	1863305	1			T2	1		T97	2		T59	1
valid_sources[0x07]	1399863	1			T2	2		T54	1		T59	7
valid_sources[0x08]	1401061	1			T2	2		T56	128		T97	2
valid_sources[0x09]	3835574	1			T1	1		T2	1		T56	128
valid_sources[0x0a]	2459795	1			T2	2		T56	128		T55	2
valid_sources[0x0b]	1391992	1			T1	1		T2	4		T65	2
valid_sources[0x0c]	3857520	1			T2	2		T65	2		T59	3
valid_sources[0x0d]	1858164	1			T2	3		T56	128		T65	2
valid_sources[0x0e]	1398425	1			T1	4		T2	6		T3	10
valid_sources[0x0f]	1402965	1			T2	1		T56	384		T59	11
valid_sources[0x10]	1392868	1			T1	3		T2	2		T56	128
valid_sources[0x11]	1394665	1			T1	2		T2	3		T59	4
valid_sources[0x12]	1584504	1			T1	1		T2	5		T109	1
valid_sources[0x13]	1508547	1			T1	6		T2	1		T65	14
valid_sources[0x14]	1417172	1			T1	5		T2	3		T56	128
valid_sources[0x15]	1395930	1			T1	2		T2	4		T54	5
valid_sources[0x16]	1426632	1			T2	3		T55	2		T65	2
valid_sources[0x17]	1866073	1			T1	3		T2	2		T56	128
valid_sources[0x18]	1401450	1			T1	1		T2	2		T59	4
valid_sources[0x19]	1442504	1			T1	2		T2	1		T55	1
valid_sources[0x1a]	1397434	1			T1	5		T2	1		T54	2
valid_sources[0x1b]	1563231	1			T2	6		T97	1		T60	1
valid_sources[0x1c]	1397882	1			T1	1		T2	3		T56	128
valid_sources[0x1d]	2282103	1			T1	6		T2	2		T97	2
valid_sources[0x1e]	1423840	1			T2	2		T56	256		T65	5
valid_sources[0x1f]	3953623	1			T2	1		T55	1		T97	1
valid_sources[0x20]	1540815	1			T1	1		T2	5		T56	128
valid_sources[0x21]	1404447	1			T1	1		T2	9		T97	1
valid_sources[0x22]	1399959	1			T2	2		T65	1		T98	1
valid_sources[0x23]	1398468	1			T2	4		T97	3		T59	5
valid_sources[0x24]	3810764	1			T1	4		T54	3		T97	1
valid_sources[0x25]	1402545	1			T2	3		T54	2		T55	1
valid_sources[0x26]	1397628	1			T2	1		T3	44		T56	128
valid_sources[0x27]	1388474	1			T56	128		T97	1		T59	1
valid_sources[0x28]	1852900	1			T2	4		T55	1		T65	4
valid_sources[0x29]	2991042	1			T2	3		T65	1		T97	1
valid_sources[0x2a]	3818357	1			T1	2		T2	3		T65	7
valid_sources[0x2b]	1401357	1			T2	2		T56	128		T65	7
valid_sources[0x2c]	1441598	1			T1	1		T2	2		T59	1
valid_sources[0x2d]	1393576	1			T2	3		T65	4		T59	2
valid_sources[0x2e]	3824288	1			T1	1		T56	128		T65	2
valid_sources[0x2f]	1389889	1			T2	5		T59	4		T60	1
valid_sources[0x30]	1396503	1			T2	2		T55	3		T97	1
valid_sources[0x31]	1538045	1			T1	1		T2	6		T54	1
valid_sources[0x32]	1398163	1			T1	1		T2	2		T54	3
valid_sources[0x33]	1399537	1			T1	5		T2	1		T56	128
valid_sources[0x34]	1399571	1			T2	3		T55	1		T59	5
valid_sources[0x35]	1395582	1			T1	1		T2	1		T65	3
valid_sources[0x36]	1420413	1			T2	7		T54	2		T65	6
valid_sources[0x37]	2204379	1			T1	2		T2	6		T109	5
valid_sources[0x38]	1420201	1			T2	1		T65	1		T59	7
valid_sources[0x39]	3474786	1			T1	2		T2	1		T56	128
valid_sources[0x3a]	1404662	1			T2	9		T56	128		T109	2
valid_sources[0x3b]	1397371	1			T56	128		T55	1		T59	1
valid_sources[0x3c]	2319104	1			T1	3		T2	1		T97	1
valid_sources[0x3d]	1409020	1			T2	1		T56	192		T55	4
valid_sources[0x3e]	1445292	1			T1	3		T2	5		T56	128
valid_sources[0x3f]	3786624	1			T1	2		T2	2		T56	128
valid_sources[0x40]	1395979	1			T2	3		T54	2		T55	1
valid_sources[0x41]	1399420	1			T2	5		T54	1		T59	3
valid_sources[0x42]	1410698	1			T2	6		T56	128		T55	1
valid_sources[0x43]	2077561	1			T1	4		T2	5		T55	1
valid_sources[0x44]	1395472	1			T1	2		T2	3		T55	1
valid_sources[0x45]	1396112	1			T2	5		T54	3		T65	2
valid_sources[0x46]	1394641	1			T1	1		T2	3		T109	5
valid_sources[0x47]	1389996	1			T2	3		T97	3		T59	1
valid_sources[0x48]	1406991	1			T2	3		T54	5		T65	1
valid_sources[0x49]	3938366	1			T1	5		T2	1		T56	128
valid_sources[0x4a]	4697927	1			T1	4		T2	4		T56	256
valid_sources[0x4b]	3823289	1			T2	2		T65	5		T59	3
valid_sources[0x4c]	2324429	1			T2	3		T56	128		T55	1
valid_sources[0x4d]	1396293	1			T2	3		T56	128		T97	1
valid_sources[0x4e]	1608988	1			T2	1		T59	9		T98	4
valid_sources[0x4f]	1393434	1			T1	5		T2	2		T55	1
valid_sources[0x50]	3448372	1			T1	1		T56	128		T54	1
valid_sources[0x51]	1525455	1			T1	3		T2	4		T59	13
valid_sources[0x52]	1392580	1			T2	3		T54	2		T97	1
valid_sources[0x53]	1429738	1			T1	3		T2	3		T56	128
valid_sources[0x54]	1402048	1			T2	1		T56	128		T55	1
valid_sources[0x55]	4725971	1			T1	7		T2	6		T97	1
valid_sources[0x56]	1395502	1			T1	2		T2	2		T54	1
valid_sources[0x57]	1946885	1			T2	2		T54	4		T65	6
valid_sources[0x58]	1395844	1			T2	1		T55	1		T97	1
valid_sources[0x59]	1394250	1			T54	4		T59	2		T98	1
valid_sources[0x5a]	1398925	1			T56	192		T55	5		T97	3
valid_sources[0x5b]	1457569	1			T2	2		T59	6		T60	1
valid_sources[0x5c]	3475298	1			T55	1		T59	2		T110	1
valid_sources[0x5d]	3916332	1			T1	2		T2	1		T54	6
valid_sources[0x5e]	2245287	1			T1	4		T2	3		T56	256
valid_sources[0x5f]	1398957	1			T1	4		T2	5		T56	128
valid_sources[0x60]	1513399	1			T1	4		T2	1		T56	256
valid_sources[0x61]	1490765	1			T2	3		T59	10		T98	2
valid_sources[0x62]	1396035	1			T1	1		T2	7		T56	192
valid_sources[0x63]	1952974	1			T1	2		T2	3		T56	128
valid_sources[0x64]	1413643	1			T2	3		T65	2		T59	4
valid_sources[0x65]	1392599	1			T2	5		T59	3		T109	1
valid_sources[0x66]	1396652	1			T2	2		T56	128		T65	4
valid_sources[0x67]	1393517	1			T55	2		T59	1		T98	1
valid_sources[0x68]	1740833	1			T1	3		T2	7		T54	4
valid_sources[0x69]	6255233	1			T2	9		T56	128		T55	1
valid_sources[0x6a]	1425223	1			T1	1		T2	1		T54	3
valid_sources[0x6b]	1910690	1			T1	5		T2	4		T56	128
valid_sources[0x6c]	3426371	1			T1	4		T2	3		T3	118
valid_sources[0x6d]	1395127	1			T1	2		T2	2		T56	128
valid_sources[0x6e]	1401149	1			T1	3		T2	5		T59	4
valid_sources[0x6f]	1476952	1			T1	1		T2	1		T59	5
valid_sources[0x70]	3803443	1			T2	1		T54	2		T55	1
valid_sources[0x71]	1592455	1			T1	4		T2	1		T59	3
valid_sources[0x72]	1393000	1			T2	3		T59	11		T98	1
valid_sources[0x73]	1391794	1			T2	2		T56	128		T59	4
valid_sources[0x74]	2990813	1			T2	3		T59	15		T57	64
valid_sources[0x75]	1398623	1			T2	4		T59	6		T98	1
valid_sources[0x76]	2055651	1			T55	3		T97	1		T59	5
valid_sources[0x77]	1486625	1			T1	2		T2	1		T65	1
valid_sources[0x78]	1399954	1			T1	5		T2	3		T97	1
valid_sources[0x79]	2319222	1			T2	6		T54	9		T55	1
valid_sources[0x7a]	1438656	1			T1	2		T2	3		T54	2
valid_sources[0x7b]	2483189	1			T1	1		T2	5		T65	3
valid_sources[0x7c]	1397110	1			T2	1		T56	128		T54	3
valid_sources[0x7d]	2244458	1			T1	2		T2	2		T65	2
valid_sources[0x7e]	2416302	1			T1	1		T2	1		T3	8
valid_sources[0x7f]	1441930	1			T2	2		T3	55		T55	1
valid_sources[0x80]	1388727	1			T1	3		T2	3		T59	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

90535828

1

T1

65

T2

380

T3

77

values[0x0]

all_enables

biggest_size

63541465

1

T1

30

T2

173

T3

54

values[0x1]

all_enables

biggest_size

54794536

1

T1

35

T2

198

T3

55