Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

269268006

1

T1

192

T2

1

T3

61

full_word

209406134

1

T1

130

T2

751

T3

186

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	478673830	1			T1	322		T2	752		T3	247
auto[TlIntgErrCmd]	109	1			T57	4		T129	9		T130	4
auto[TlIntgErrData]	92	1			T57	6		T129	6		T130	3
auto[TlIntgErrBoth]	109	1			T57	10		T129	5		T130	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

248265747

1

T1

122

T2

381

T3

127

auto[1]

230408393

1

T1

200

T2

371

T3

120

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157595499	1			T1	57		T2	1		T3	50
auto[TlIntgErrNone]	partial	auto[1]	111672226	1			T1	135		T3	11		T56	550
auto[TlIntgErrNone]	full_word	auto[0]	90670106	1			T1	65		T2	380		T3	77
auto[TlIntgErrNone]	full_word	auto[1]	118735999	1			T1	65		T2	371		T3	109
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T57	1		T129	5		T130	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T57	2		T129	4		T130	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T57	1		T134	2		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T174	1		T172	1		T170	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T57	3		T129	3		T133	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T57	2		T129	3		T130	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T130	1		T171	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T57	1		T174	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T57	5		T129	2		T130	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T57	3		T129	3		T130	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T57	1		T151	1		T174	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T57	1		T151	1		T171	1