Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	120436438	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120436438	0	0
T1	3080	146	0	0
T2	6933	0	0	0
T3	1792	0	0	0
T54	1908	86	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	0	0	0
T98	0	302	0	0
T99	0	582	0	0
T100	0	322	0	0
T101	0	177	0	0
T102	0	241	0	0
T103	0	94	0	0
T104	0	723	0	0
T112	0	849	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T65	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	221566474	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	221566474	0	0
T1	3080	139	0	0
T2	6933	0	0	0
T3	1792	0	0	0
T54	1908	81	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	0	0	0
T98	0	291	0	0
T99	0	444	0	0
T100	0	697	0	0
T101	0	147	0	0
T102	0	129	0	0
T103	0	92	0	0
T104	0	2419	0	0
T112	0	1785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T65	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	325701196	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	325701196	0	0
T1	3080	193	0	0
T2	6933	1666	0	0
T3	1792	486	0	0
T54	1908	99	0	0
T55	1868	96	0	0
T56	103284	14697	0	0
T59	11192	1748	0	0
T60	3110	79	0	0
T65	1842	481	0	0
T97	2375	348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T65	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	619238285	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	619238285	0	0
T1	3080	183	0	0
T2	6933	3518	0	0
T3	1792	247	0	0
T54	1908	93	0	0
T55	1868	91	0	0
T56	103284	14685	0	0
T59	11192	1348	0	0
T60	3110	77	0	0
T65	1842	243	0	0
T97	2375	679	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3080	3001	0	0
T2	6933	6853	0	0
T3	1792	1699	0	0
T54	1908	1802	0	0
T55	1868	1740	0	0
T56	103284	103206	0	0
T59	11192	10599	0	0
T60	3110	2840	0	0
T65	1842	1617	0	0
T97	2375	2293	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T65	1	1	0	0
T97	1	1	0	0