Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1942112	0	0
entropy_period_rd_A	2147483647	3026	0	0
intr_enable_rd_A	2147483647	3545	0	0
prefix_0_rd_A	2147483647	2733	0	0
prefix_10_rd_A	2147483647	2871	0	0
prefix_1_rd_A	2147483647	2896	0	0
prefix_2_rd_A	2147483647	2725	0	0
prefix_3_rd_A	2147483647	2871	0	0
prefix_4_rd_A	2147483647	2689	0	0
prefix_5_rd_A	2147483647	2828	0	0
prefix_6_rd_A	2147483647	2607	0	0
prefix_7_rd_A	2147483647	2872	0	0
prefix_8_rd_A	2147483647	2749	0	0
prefix_9_rd_A	2147483647	3116	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1942112	0	0
T1	3080	1	0	0
T2	6933	0	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	0	4	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	0	0	0
T98	0	107	0	0
T99	0	271	0	0
T100	0	2	0	0
T101	0	79	0	0
T102	0	1	0	0
T103	0	178	0	0
T129	0	2	0	0
T130	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3026	0	0
T2	6933	43	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	128	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	3	0	0
T100	0	6	0	0
T120	0	35	0	0
T121	0	7	0	0
T134	0	61	0	0
T148	0	15	0	0
T150	0	35	0	0
T151	0	108	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3545	0	0
T2	6933	37	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	180	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T63	0	11	0	0
T65	1842	0	0	0
T97	2375	16	0	0
T100	0	3	0	0
T111	0	21	0	0
T136	0	6	0	0
T148	0	19	0	0
T152	0	4	0	0
T153	0	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2733	0	0
T2	6933	30	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	88	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	9	0	0
T100	0	2	0	0
T120	0	45	0	0
T121	0	3	0	0
T134	0	30	0	0
T136	0	2	0	0
T148	0	12	0	0
T150	0	11	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2871	0	0
T2	6933	58	0	0
T3	1792	0	0	0
T41	0	36	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	70	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	0	0	0
T100	0	12	0	0
T120	0	50	0	0
T121	0	1	0	0
T134	0	53	0	0
T148	0	30	0	0
T150	0	14	0	0
T151	0	87	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2896	0	0
T2	6933	42	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	89	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	1	0	0
T100	0	10	0	0
T120	0	40	0	0
T121	0	1	0	0
T134	0	41	0	0
T148	0	23	0	0
T150	0	20	0	0
T151	0	65	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2725	0	0
T2	6933	21	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	72	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	1	0	0
T100	0	10	0	0
T120	0	26	0	0
T134	0	41	0	0
T136	0	6	0	0
T148	0	2	0	0
T150	0	25	0	0
T151	0	77	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2871	0	0
T57	30828	87	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T62	1589	0	0	0
T63	1136	0	0	0
T97	2375	4	0	0
T98	5966	0	0	0
T99	3748	0	0	0
T100	0	3	0	0
T104	0	4	0	0
T108	4529	0	0	0
T109	5171	0	0	0
T120	0	29	0	0
T121	0	3	0	0
T134	0	42	0	0
T136	0	2	0	0
T148	0	4	0	0
T150	0	63	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2689	0	0
T2	6933	27	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	88	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	6	0	0
T100	0	9	0	0
T120	0	24	0	0
T121	0	4	0	0
T134	0	52	0	0
T136	0	1	0	0
T148	0	6	0	0
T150	0	11	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2828	0	0
T2	6933	23	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	73	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	3	0	0
T100	0	12	0	0
T104	0	3	0	0
T120	0	36	0	0
T121	0	9	0	0
T134	0	40	0	0
T148	0	21	0	0
T150	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2607	0	0
T2	6933	35	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	78	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	6	0	0
T100	0	12	0	0
T120	0	29	0	0
T134	0	44	0	0
T136	0	1	0	0
T148	0	20	0	0
T150	0	11	0	0
T151	0	67	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2872	0	0
T2	6933	46	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	72	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	7	0	0
T100	0	8	0	0
T120	0	13	0	0
T121	0	2	0	0
T134	0	61	0	0
T136	0	5	0	0
T148	0	1	0	0
T150	0	5	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2749	0	0
T2	6933	23	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	71	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	4	0	0
T100	0	4	0	0
T121	0	3	0	0
T132	0	1	0	0
T134	0	35	0	0
T136	0	8	0	0
T148	0	12	0	0
T150	0	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3116	0	0
T2	6933	42	0	0
T3	1792	0	0	0
T54	1908	0	0	0
T55	1868	0	0	0
T56	103284	0	0	0
T57	30828	68	0	0
T59	11192	0	0	0
T60	3110	0	0	0
T65	1842	0	0	0
T97	2375	2	0	0
T100	0	4	0	0
T120	0	29	0	0
T134	0	39	0	0
T136	0	6	0	0
T148	0	40	0	0
T150	0	7	0	0
T151	0	71	0	0