Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257489308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

205474566

1

T1

3550

T2

11

T3

1899

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	243522047	1			T1	6845		T2	7		T3	1432
values[0x0]	105217288	1			T1	64		T2	5		T3	588
values[0x1]	114224539	1			T1	56		T2	83		T3	622

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200376211	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

262587663

1

T1

4246

T2

73

T3

2125

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1506205	1			T3	18		T44	3		T87	1
valid_sources[0x01]	2037445	1			T1	60		T3	8		T44	7
valid_sources[0x02]	2212129	1			T3	12		T47	2		T54	2
valid_sources[0x03]	1828585	1			T3	13		T47	2		T43	147
valid_sources[0x04]	1356322	1			T3	7		T44	7		T87	2
valid_sources[0x05]	2041113	1			T1	30		T2	7		T3	11
valid_sources[0x06]	2274657	1			T3	15		T47	1		T44	16
valid_sources[0x07]	1357070	1			T3	3		T44	1		T126	1
valid_sources[0x08]	1363496	1			T3	8		T44	8		T128	18
valid_sources[0x09]	1355671	1			T1	60		T2	5		T3	12
valid_sources[0x0a]	1357551	1			T3	7		T50	3		T43	53
valid_sources[0x0b]	1426756	1			T1	210		T2	3		T3	4
valid_sources[0x0c]	2276060	1			T3	6		T44	6		T87	3
valid_sources[0x0d]	3858088	1			T1	60		T2	1		T3	5
valid_sources[0x0e]	2122413	1			T1	120		T3	6		T44	6
valid_sources[0x0f]	1345814	1			T3	7		T44	4		T87	2
valid_sources[0x10]	1354964	1			T3	1		T126	1		T88	1
valid_sources[0x11]	1360114	1			T1	60		T3	11		T47	1
valid_sources[0x12]	1353477	1			T3	8		T44	5		T87	4
valid_sources[0x13]	2041467	1			T1	120		T3	7		T44	10
valid_sources[0x14]	1363454	1			T3	11		T44	17		T87	3
valid_sources[0x15]	1344694	1			T3	11		T44	12		T126	1
valid_sources[0x16]	1354045	1			T3	5		T44	2		T87	2
valid_sources[0x17]	1455799	1			T3	21		T44	15		T87	4
valid_sources[0x18]	2915089	1			T3	2		T87	1		T99	9
valid_sources[0x19]	1354228	1			T3	15		T44	4		T87	1
valid_sources[0x1a]	3580037	1			T1	60		T2	2		T3	8
valid_sources[0x1b]	3871787	1			T1	60		T3	10		T50	1
valid_sources[0x1c]	1726137	1			T1	120		T3	9		T44	5
valid_sources[0x1d]	1380637	1			T3	6		T44	18		T128	24
valid_sources[0x1e]	2227226	1			T3	18		T44	11		T87	1
valid_sources[0x1f]	1357870	1			T3	8		T50	1		T44	2
valid_sources[0x20]	1619503	1			T3	16		T44	5		T87	2
valid_sources[0x21]	3401193	1			T3	6		T44	11		T87	1
valid_sources[0x22]	1357305	1			T1	60		T3	11		T87	2
valid_sources[0x23]	1357296	1			T3	4		T50	3		T43	54
valid_sources[0x24]	1364224	1			T1	60		T3	14		T44	2
valid_sources[0x25]	1355456	1			T1	60		T3	13		T126	2
valid_sources[0x26]	1375198	1			T1	120		T3	12		T50	2
valid_sources[0x27]	1471926	1			T2	1		T3	9		T47	3
valid_sources[0x28]	1359293	1			T1	120		T3	7		T45	21
valid_sources[0x29]	3752333	1			T1	60		T3	12		T101	1
valid_sources[0x2a]	1819086	1			T3	16		T47	1		T50	1
valid_sources[0x2b]	1467338	1			T2	1		T3	9		T50	1
valid_sources[0x2c]	1359495	1			T1	60		T3	8		T44	5
valid_sources[0x2d]	2019341	1			T1	60		T3	6		T44	1
valid_sources[0x2e]	2289911	1			T1	60		T2	4		T3	10
valid_sources[0x2f]	1358374	1			T1	120		T3	7		T54	2
valid_sources[0x30]	1704538	1			T1	60		T3	17		T54	2
valid_sources[0x31]	1350345	1			T2	3		T3	10		T44	7
valid_sources[0x32]	1362776	1			T1	60		T3	13		T47	2
valid_sources[0x33]	1521521	1			T1	60		T3	8		T44	3
valid_sources[0x34]	1427168	1			T2	1		T3	10		T47	3
valid_sources[0x35]	2364858	1			T3	3		T47	1		T44	4
valid_sources[0x36]	1366756	1			T1	120		T3	9		T50	1
valid_sources[0x37]	1465037	1			T3	7		T46	10		T44	14
valid_sources[0x38]	1355943	1			T1	60		T3	5		T44	1
valid_sources[0x39]	1355621	1			T3	8		T50	1		T44	6
valid_sources[0x3a]	1500733	1			T3	11		T44	6		T87	2
valid_sources[0x3b]	1364477	1			T1	60		T3	9		T44	1
valid_sources[0x3c]	2803780	1			T1	60		T3	9		T44	3
valid_sources[0x3d]	2023010	1			T2	2		T3	7		T50	1
valid_sources[0x3e]	1351780	1			T1	60		T3	15		T44	1
valid_sources[0x3f]	1357175	1			T3	17		T44	9		T87	2
valid_sources[0x40]	1353058	1			T2	2		T3	7		T44	5
valid_sources[0x41]	1360272	1			T1	120		T3	6		T47	2
valid_sources[0x42]	1350454	1			T1	30		T3	3		T44	6
valid_sources[0x43]	2239014	1			T3	6		T50	1		T44	4
valid_sources[0x44]	1411758	1			T3	4		T54	1		T44	8
valid_sources[0x45]	1353492	1			T3	11		T44	2		T94	1
valid_sources[0x46]	1408916	1			T1	60		T3	9		T43	73
valid_sources[0x47]	1447959	1			T1	60		T3	12		T47	4
valid_sources[0x48]	1344651	1			T3	16		T44	1		T128	37
valid_sources[0x49]	1687455	1			T1	122		T3	13		T43	1
valid_sources[0x4a]	1433524	1			T1	60		T3	10		T44	3
valid_sources[0x4b]	1351762	1			T3	14		T47	1		T44	3
valid_sources[0x4c]	1775916	1			T3	17		T47	3		T44	5
valid_sources[0x4d]	1359335	1			T3	10		T44	8		T87	2
valid_sources[0x4e]	2245948	1			T3	8		T47	1		T43	21
valid_sources[0x4f]	1382432	1			T3	2		T47	3		T44	3
valid_sources[0x50]	1932423	1			T1	120		T3	23		T44	8
valid_sources[0x51]	2285255	1			T2	1		T3	6		T47	1
valid_sources[0x52]	1523042	1			T3	11		T47	1		T44	27
valid_sources[0x53]	2293911	1			T3	6		T43	18		T44	8
valid_sources[0x54]	1351459	1			T3	10		T54	2		T44	6
valid_sources[0x55]	1354978	1			T3	10		T44	1		T87	2
valid_sources[0x56]	1356242	1			T1	60		T3	7		T44	4
valid_sources[0x57]	1358809	1			T3	10		T44	1		T87	1
valid_sources[0x58]	1435503	1			T1	60		T3	19		T44	6
valid_sources[0x59]	1520764	1			T3	12		T47	2		T44	6
valid_sources[0x5a]	1350447	1			T1	120		T3	14		T54	1
valid_sources[0x5b]	1384682	1			T3	9		T47	2		T44	10
valid_sources[0x5c]	1348789	1			T3	18		T46	15		T44	6
valid_sources[0x5d]	1440746	1			T3	10		T50	1		T43	55
valid_sources[0x5e]	2195088	1			T1	60		T3	10		T44	18
valid_sources[0x5f]	1362405	1			T3	11		T43	4		T44	9
valid_sources[0x60]	1358088	1			T2	2		T3	14		T45	2
valid_sources[0x61]	1355429	1			T2	1		T3	5		T43	27
valid_sources[0x62]	3788777	1			T2	2		T3	5		T44	5
valid_sources[0x63]	3194749	1			T3	12		T44	6		T87	3
valid_sources[0x64]	1393088	1			T2	1		T3	14		T50	1
valid_sources[0x65]	1796057	1			T3	11		T44	6		T87	3
valid_sources[0x66]	1353965	1			T3	7		T44	3		T87	2
valid_sources[0x67]	1352579	1			T3	4		T51	40		T44	2
valid_sources[0x68]	3779227	1			T1	60		T3	13		T50	1
valid_sources[0x69]	1350012	1			T3	19		T47	5		T43	17
valid_sources[0x6a]	1358989	1			T3	10		T44	7		T126	2
valid_sources[0x6b]	1377847	1			T3	10		T44	4		T87	3
valid_sources[0x6c]	3802056	1			T3	12		T46	9		T44	6
valid_sources[0x6d]	2245273	1			T3	8		T46	5		T44	3
valid_sources[0x6e]	2206227	1			T1	60		T3	6		T47	4
valid_sources[0x6f]	5437549	1			T1	60		T3	4		T47	5
valid_sources[0x70]	1359397	1			T2	1		T3	19		T47	1
valid_sources[0x71]	2277853	1			T2	1		T3	5		T47	2
valid_sources[0x72]	1397330	1			T3	5		T47	3		T44	5
valid_sources[0x73]	1348412	1			T1	120		T3	13		T47	2
valid_sources[0x74]	1367932	1			T3	6		T53	40		T44	5
valid_sources[0x75]	1359225	1			T3	6		T45	21		T43	13
valid_sources[0x76]	2025845	1			T3	6		T44	3		T87	2
valid_sources[0x77]	3801861	1			T1	91		T3	12		T44	10
valid_sources[0x78]	3563452	1			T1	60		T3	14		T44	8
valid_sources[0x79]	1349722	1			T3	18		T44	3		T87	2
valid_sources[0x7a]	2223432	1			T3	12		T44	11		T87	5
valid_sources[0x7b]	1354683	1			T1	31		T3	11		T44	5
valid_sources[0x7c]	1403446	1			T1	120		T3	11		T44	4
valid_sources[0x7d]	1836846	1			T3	9		T47	1		T44	1
valid_sources[0x7e]	1357294	1			T1	30		T2	1		T3	8
valid_sources[0x7f]	1395998	1			T1	60		T3	8		T44	1
valid_sources[0x80]	1368274	1			T3	20		T44	6		T87	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89317590

1

T1

3440

T2

5

T3

784

values[0x0]

all_enables

biggest_size

62402808

1

T1

59

T2

1

T3

551

values[0x1]

all_enables

biggest_size

53754168

1

T1

51

T2

5

T3

564