Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

267771953

1

T1

3415

T2

537

T3

748

full_word

206111009

1

T1

3550

T2

20

T3

1899

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	473882652	1			T1	6965		T2	557		T3	2627
auto[TlIntgErrCmd]	87	1			T3	5		T122	4		T123	6
auto[TlIntgErrData]	111	1			T3	8		T44	7		T122	2
auto[TlIntgErrBoth]	112	1			T3	7		T44	3		T122	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245482980

1

T1

6845

T2

37

T3

1432

auto[1]

228399982

1

T1

120

T2

520

T3

1215

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	156006075	1			T1	3405		T2	31		T3	643
auto[TlIntgErrNone]	partial	auto[1]	111765597	1			T1	10		T2	506		T3	85
auto[TlIntgErrNone]	full_word	auto[0]	89476761	1			T1	3440		T2	6		T3	784
auto[TlIntgErrNone]	full_word	auto[1]	116634219	1			T1	110		T2	14		T3	1115
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T3	2		T122	1		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T3	3		T122	3		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T161	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T123	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	58	1			T3	3		T44	5		T122	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T3	5		T44	1		T123	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T44	1		T124	1		T125	4
auto[TlIntgErrData]	full_word	auto[1]	5	1			T123	1		T162	1		T163	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T44	2		T122	2		T123	5
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T3	7		T44	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T164	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T122	1		T123	1		T125	3