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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 118484024 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1282 1282 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 118484024 0 0
T2 5109 59 0 0
T3 18972 0 0 0
T43 2633 0 0 0
T45 2303 0 0 0
T46 1472 0 0 0
T47 1824 0 0 0
T50 989 0 0 0
T53 903 0 0 0
T54 1625 0 0 0
T86 1229 0 0 0
T87 0 702 0 0
T88 0 298 0 0
T89 0 99 0 0
T90 0 1139 0 0
T91 0 698 0 0
T94 0 235 0 0
T95 0 30 0 0
T96 0 697 0 0
T97 0 500 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1282 1282 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T43 1 1 0 0
T45 1 1 0 0
T46 1 1 0 0
T47 1 1 0 0
T50 1 1 0 0
T53 1 1 0 0
T86 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 225959585 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1282 1282 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 225959585 0 0
T2 5109 59 0 0
T3 18972 0 0 0
T43 2633 0 0 0
T45 2303 0 0 0
T46 1472 0 0 0
T47 1824 0 0 0
T50 989 0 0 0
T53 903 0 0 0
T54 1625 0 0 0
T86 1229 0 0 0
T87 0 361 0 0
T88 0 238 0 0
T89 0 97 0 0
T90 0 596 0 0
T91 0 532 0 0
T94 0 119 0 0
T95 0 29 0 0
T96 0 349 0 0
T97 0 268 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1282 1282 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T43 1 1 0 0
T45 1 1 0 0
T46 1 1 0 0
T47 1 1 0 0
T50 1 1 0 0
T53 1 1 0 0
T86 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 323681608 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1282 1282 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 323681608 0 0
T1 14779 13813 0 0
T2 5109 365 0 0
T3 18972 2875 0 0
T43 2633 1531 0 0
T45 2303 300 0 0
T46 1472 131 0 0
T47 1824 204 0 0
T50 989 40 0 0
T53 903 40 0 0
T86 1229 1 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1282 1282 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T43 1 1 0 0
T45 1 1 0 0
T46 1 1 0 0
T47 1 1 0 0
T50 1 1 0 0
T53 1 1 0 0
T86 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 636385229 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1282 1282 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 636385229 0 0
T1 14779 6965 0 0
T2 5109 344 0 0
T3 18972 2647 0 0
T43 2633 673 0 0
T45 2303 274 0 0
T46 1472 120 0 0
T47 1824 415 0 0
T50 989 40 0 0
T53 903 40 0 0
T86 1229 1 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14779 14721 0 0
T2 5109 5023 0 0
T3 18972 17488 0 0
T43 2633 2415 0 0
T45 2303 2247 0 0
T46 1472 1411 0 0
T47 1824 1730 0 0
T50 989 894 0 0
T53 903 832 0 0
T86 1229 1178 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1282 1282 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T43 1 1 0 0
T45 1 1 0 0
T46 1 1 0 0
T47 1 1 0 0
T50 1 1 0 0
T53 1 1 0 0
T86 1 1 0 0

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