Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2318064	0	0
entropy_period_rd_A	2147483647	2596	0	0
intr_enable_rd_A	2147483647	3370	0	0
prefix_0_rd_A	2147483647	2637	0	0
prefix_10_rd_A	2147483647	2666	0	0
prefix_1_rd_A	2147483647	2596	0	0
prefix_2_rd_A	2147483647	2674	0	0
prefix_3_rd_A	2147483647	2763	0	0
prefix_4_rd_A	2147483647	2643	0	0
prefix_5_rd_A	2147483647	2876	0	0
prefix_6_rd_A	2147483647	2779	0	0
prefix_7_rd_A	2147483647	2734	0	0
prefix_8_rd_A	2147483647	2711	0	0
prefix_9_rd_A	2147483647	2795	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2318064	0	0
T2	5109	19	0	0
T3	18972	5	0	0
T43	2633	0	0	0
T45	2303	0	0	0
T46	1472	0	0	0
T47	1824	0	0	0
T50	989	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	0	11	0	0
T88	0	131	0	0
T90	0	11	0	0
T91	0	240	0	0
T92	0	234	0	0
T122	0	1	0	0
T123	0	3	0	0
T125	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2596	0	0
T43	2633	0	0	0
T44	13671	51	0	0
T47	1824	5	0	0
T50	989	0	0	0
T51	1258	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	13	0	0
T100	0	3	0	0
T101	0	76	0	0
T104	0	1	0	0
T105	0	10	0	0
T124	0	52	0	0
T126	1108	0	0	0
T128	0	48	0	0
T141	0	121	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3370	0	0
T43	2633	0	0	0
T44	13671	128	0	0
T47	1824	3	0	0
T50	989	0	0	0
T51	1258	0	0	0
T52	0	28	0	0
T53	903	0	0	0
T54	1625	13	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	25	0	0
T126	1108	0	0	0
T128	0	55	0	0
T144	0	12	0	0
T145	0	29	0	0
T146	0	10	0	0
T147	0	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2637	0	0
T43	2633	0	0	0
T44	13671	54	0	0
T47	1824	7	0	0
T50	989	0	0	0
T51	1258	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	11	0	0
T100	0	8	0	0
T101	0	23	0	0
T105	0	9	0	0
T124	0	28	0	0
T126	1108	0	0	0
T128	0	54	0	0
T141	0	281	0	0
T148	0	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2666	0	0
T44	13671	35	0	0
T87	2439	0	0	0
T94	1445	0	0	0
T99	5505	8	0	0
T100	2601	11	0	0
T101	0	29	0	0
T104	0	5	0	0
T105	0	13	0	0
T124	0	46	0	0
T126	1108	0	0	0
T127	2257	0	0	0
T128	11740	30	0	0
T141	0	201	0	0
T144	1034	0	0	0
T145	1248	0	0	0
T148	0	13	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2596	0	0
T44	13671	38	0	0
T87	2439	0	0	0
T94	1445	0	0	0
T99	5505	5	0	0
T100	2601	10	0	0
T101	0	21	0	0
T105	0	2	0	0
T124	0	35	0	0
T126	1108	0	0	0
T127	2257	0	0	0
T128	11740	53	0	0
T141	0	260	0	0
T144	1034	0	0	0
T145	1248	0	0	0
T148	0	7	0	0
T149	0	61	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2674	0	0
T43	2633	0	0	0
T44	13671	40	0	0
T47	1824	1	0	0
T50	989	0	0	0
T51	1258	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	11	0	0
T100	0	3	0	0
T101	0	35	0	0
T105	0	1	0	0
T124	0	37	0	0
T126	1108	0	0	0
T128	0	22	0	0
T141	0	299	0	0
T148	0	13	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2763	0	0
T44	13671	56	0	0
T87	2439	0	0	0
T94	1445	0	0	0
T99	5505	15	0	0
T100	2601	2	0	0
T101	0	30	0	0
T104	0	5	0	0
T105	0	12	0	0
T124	0	33	0	0
T126	1108	0	0	0
T127	2257	0	0	0
T128	11740	14	0	0
T141	0	263	0	0
T144	1034	0	0	0
T145	1248	0	0	0
T148	0	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2643	0	0
T44	13671	44	0	0
T87	2439	0	0	0
T94	1445	0	0	0
T99	5505	12	0	0
T100	2601	8	0	0
T101	0	34	0	0
T104	0	7	0	0
T105	0	2	0	0
T124	0	25	0	0
T126	1108	0	0	0
T127	2257	0	0	0
T128	11740	75	0	0
T141	0	264	0	0
T144	1034	0	0	0
T145	1248	0	0	0
T148	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2876	0	0
T44	13671	36	0	0
T87	2439	0	0	0
T94	1445	0	0	0
T99	5505	11	0	0
T100	2601	4	0	0
T101	0	41	0	0
T104	0	4	0	0
T105	0	13	0	0
T124	0	50	0	0
T126	1108	0	0	0
T127	2257	0	0	0
T128	11740	55	0	0
T141	0	287	0	0
T144	1034	0	0	0
T145	1248	0	0	0
T148	0	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2779	0	0
T43	2633	0	0	0
T44	13671	48	0	0
T47	1824	1	0	0
T50	989	0	0	0
T51	1258	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	4	0	0
T100	0	16	0	0
T101	0	32	0	0
T105	0	14	0	0
T124	0	51	0	0
T126	1108	0	0	0
T128	0	29	0	0
T141	0	341	0	0
T148	0	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2734	0	0
T43	2633	0	0	0
T44	13671	47	0	0
T47	1824	3	0	0
T50	989	0	0	0
T51	1258	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	17	0	0
T100	0	5	0	0
T101	0	26	0	0
T104	0	5	0	0
T105	0	10	0	0
T124	0	30	0	0
T126	1108	0	0	0
T128	0	56	0	0
T141	0	243	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2711	0	0
T43	2633	0	0	0
T44	13671	44	0	0
T47	1824	2	0	0
T50	989	0	0	0
T51	1258	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	7	0	0
T100	0	3	0	0
T101	0	57	0	0
T104	0	1	0	0
T105	0	2	0	0
T124	0	58	0	0
T126	1108	0	0	0
T128	0	52	0	0
T141	0	330	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2795	0	0
T43	2633	0	0	0
T44	13671	33	0	0
T47	1824	2	0	0
T50	989	0	0	0
T51	1258	0	0	0
T53	903	0	0	0
T54	1625	0	0	0
T86	1229	0	0	0
T87	2439	0	0	0
T99	0	8	0	0
T100	0	15	0	0
T101	0	32	0	0
T104	0	5	0	0
T105	0	6	0	0
T124	0	41	0	0
T126	1108	0	0	0
T128	0	27	0	0
T141	0	300	0	0