Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.88	99.38	88.37		80.95	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	95.51	99.38	88.37		94.12	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.51	99.38	88.37		94.12	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.28	99.42	88.37	100.00	94.12	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.09	97.30	81.25		100.00	91.89	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		162	161	99.38
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	719	9	9	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
541	1	1
558	1	1
559	1	1
560	1	1
561	1	1
581	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
727	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T5,T6

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T7

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T7

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T14

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T13

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T5,T6

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T28,T29,T36
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T4,T5,T6

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T4,T5,T6

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	17	80.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1
StMessageWait	383	Covered	T1
StPad	389	Covered	T1
StPad01	427	Covered	T1
StPadFlush	435	Covered	T1
StPadIdle	333	Covered	T1
StPadRun	421	Covered	T1
StPrefix	328	Covered	T1
StPrefixWait	348	Covered	T1
StTerminalError	495	Covered	T1

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	383	Covered	T1
StMessage->StPad	389	Covered	T1
StMessage->StTerminalError	495	Covered	T1
StMessageWait->StMessage	403	Covered	T1
StMessageWait->StTerminalError	495	Covered	T1
StPad->StPad01	427	Covered	T1
StPad->StPadRun	421	Covered	T1
StPad->StTerminalError	495	Not Covered
StPad01->StPadFlush	452	Covered	T1
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Covered	T1
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1
StPadIdle->StPrefix	328	Covered	T1
StPadIdle->StTerminalError	495	Covered	T1
StPadRun->StPadFlush	435	Covered	T1
StPadRun->StTerminalError	495	Not Covered
StPrefix->StPrefixWait	348	Covered	T1
StPrefix->StTerminalError	495	Covered	T1
StPrefixWait->StMessage	364	Covered	T1
StPrefixWait->StTerminalError	495	Covered	T1

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	719	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T20,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T4,T7,T13
L256	Covered	T4,T5,T6
L384	Covered	T6,T7,T14
L512	Covered	T5,T7,T84
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T5,T6,T7
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T5,T6,T7
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T5,T6,T7
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T6,T7
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T6,T7
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T5,T6,T13
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T5,T6,T7
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T6,T7
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T5,T6,T7
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T7
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T6,T7
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T6,T20,T7
CShake	Covered	T6,T20,T7
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T6,T7,T15
MuxFuncPad	Covered	T5,T6,T7
MuxZeroEnd	Covered	T5,T6,T7
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T6,T7,T15
MuxFuncPad	Covered	T5,T6,T7
MuxZeroEnd	Covered	T5,T6,T7
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T6,T7,T15
MuxFuncPad	Covered	T5,T6,T7
MuxZeroEnd	Covered	T5,T6,T7
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	719	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T5,T6,T7
7'b0000011	Covered	T5,T6,T7
7'b0000111	Covered	T5,T6,T7
7'b0001111	Covered	T5,T6,T7
7'b0011111	Covered	T5,T6,T7
7'b0111111	Covered	T5,T6,T7
7'b1111111	Covered	T5,T6,T7
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	350325	0	0
AlwaysPartialMsgBuf_M	2147483647	202079	0	0
CompleteBlockWhenProcess_A	2147483647	338703	0	0
DoneCondition_M	2147483647	350306	0	0
DonePulse_A	2147483647	350306	0	0
KeccakAddrInRange_A	2147483647	53927966	0	0
KeccakRunPulse_A	2147483647	3125349	0	0
MessageCondition_M	2147483647	49097305	0	0
ModeStableDuringOp_M	2147483647	36270	0	0
MsgReadyCondition_A	2147483647	2147483647	0	0
MsgWidthidth_A	1067	1067	0	0
NoPartialMsgFifo_M	2147483647	48895226	0	0
Pad01NotAttheEndOfBlock_A	2147483647	339513	0	0
PartialEndOfMsg_M	2147483647	202079	0	0
PrefixLessThanBlock_A	1067	1067	0	0
ProcessCondition_M	2147483647	350326	0	0
ProcessPulse_A	2147483647	350326	0	0
StartCondition_M	2147483647	350479	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	350479	0	0
StrengthStableDuringOp_M	2147483647	43858	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350325	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	202079	0	0
T5	955160	214	0	0
T6	129660	121	0	0
T7	344047	142	0	0
T13	650536	340	0	0
T14	136952	270	0	0
T15	363739	40	0	0
T16	285312	188	0	0
T17	472256	270	0	0
T18	38324	14	0	0
T19	0	125	0	0
T20	19737	0	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338703	0	0
T5	955160	219	0	0
T6	129660	160	0	0
T7	344047	163	0	0
T13	650536	374	0	0
T14	136952	287	0	0
T15	363739	44	0	0
T16	285312	194	0	0
T17	472256	289	0	0
T18	38324	15	0	0
T19	0	150	0	0
T20	19737	0	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350306	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350306	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53927966	0	0
T4	3713	1	0	0
T5	955160	48843	0	0
T6	129660	15325	0	0
T7	344047	7687	0	0
T13	650536	99756	0	0
T14	136952	71006	0	0
T15	363739	4696	0	0
T16	285312	79164	0	0
T17	472256	71006	0	0
T18	0	1680	0	0
T20	19737	0	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3125349	0	0
T5	955160	5427	0	0
T6	129660	833	0	0
T7	344047	413	0	0
T13	650536	5542	0	0
T14	136952	5462	0	0
T15	363739	256	0	0
T16	285312	4254	0	0
T17	472256	5462	0	0
T18	38324	88	0	0
T19	0	770	0	0
T20	19737	0	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49097305	0	0
T4	3713	1	0	0
T5	955160	47746	0	0
T6	129660	11675	0	0
T7	344047	2741	0	0
T13	650536	96112	0	0
T14	136952	69082	0	0
T15	363739	3676	0	0
T16	285312	73944	0	0
T17	472256	69082	0	0
T18	0	1316	0	0
T20	19737	0	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36270	0	0
T6	129660	158	0	0
T7	344047	70	0	0
T13	650536	0	0	0
T14	136952	0	0	0
T15	363739	23	0	0
T16	285312	99	0	0
T17	472256	0	0	0
T18	38324	9	0	0
T19	989452	150	0	0
T20	19737	12	0	0
T61	0	31	0	0
T80	0	1	0	0
T81	0	35	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	3713	97	0	0
T5	955160	756240	0	0
T6	129660	709856	0	0
T7	344047	41643	0	0
T13	650536	614040	0	0
T14	136952	115832	0	0
T15	363739	185997	0	0
T16	285312	523400	0	0
T17	472256	439700	0	0
T18	0	18468	0	0
T20	19737	0	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067	1067	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48895226	0	0
T4	3713	1	0	0
T5	955160	47532	0	0
T6	129660	11554	0	0
T7	344047	2599	0	0
T13	650536	95772	0	0
T14	136952	68812	0	0
T15	363739	3636	0	0
T16	285312	73756	0	0
T17	472256	68812	0	0
T18	0	1302	0	0
T20	19737	0	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	339513	0	0
T5	955160	222	0	0
T6	129660	163	0	0
T7	344047	163	0	0
T13	650536	374	0	0
T14	136952	289	0	0
T15	363739	44	0	0
T16	285312	197	0	0
T17	472256	289	0	0
T18	38324	15	0	0
T19	0	150	0	0
T20	19737	0	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	202079	0	0
T5	955160	214	0	0
T6	129660	121	0	0
T7	344047	142	0	0
T13	650536	340	0	0
T14	136952	270	0	0
T15	363739	40	0	0
T16	285312	188	0	0
T17	472256	270	0	0
T18	38324	14	0	0
T19	0	125	0	0
T20	19737	0	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067	1067	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350326	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350326	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350479	0	0
T4	3713	1	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	0	17	0	0
T20	19737	0	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	3713	3554	0	0
T5	955160	955093	0	0
T6	129660	129652	0	0
T7	344047	343973	0	0
T13	650536	650526	0	0
T14	136952	136942	0	0
T15	363739	363675	0	0
T16	285312	285299	0	0
T17	472256	472247	0	0
T20	19737	19637	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350479	0	0
T4	3713	1	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	0	17	0	0
T20	19737	0	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43858	0	0
T4	3713	3	0	0
T5	955160	2	0	0
T6	129660	159	0	0
T7	344047	89	0	0
T13	650536	2	0	0
T14	136952	2	0	0
T15	363739	24	0	0
T16	285312	135	0	0
T17	472256	2	0	0
T20	19737	11	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	3713	3554	0	0
T5	955160	955093	0	0
T6	129660	129652	0	0
T7	344047	343973	0	0
T13	650536	650526	0	0
T14	136952	136942	0	0
T15	363739	363675	0	0
T16	285312	285299	0	0
T17	472256	472247	0	0
T20	19737	19637	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	8758129	0
StMessageFeed_C	2147483647	2147483647	0
StPadSendMsg_C	2147483647	3895386	0
StPad_C	2147483647	339513	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	8758129	0
T5	955160	6150	0
T6	129660	4225	0
T7	344047	4075	0
T13	650536	9750	0
T14	136952	7750	0
T15	363739	1175	0
T16	285312	5225	0
T17	472256	7750	0
T18	38324	425	0
T19	0	3900	0
T20	19737	0	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147483647	0
T4	3713	97	0
T5	955160	761667	0
T6	129660	710586	0
T7	344047	41931	0
T13	650536	614594	0
T14	136952	116378	0
T15	363739	186220	0
T16	285312	527497	0
T17	472256	440246	0
T18	0	18545	0
T20	19737	0	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3895386	0
T5	955160	1065	0
T6	129660	1699	0
T7	344047	2580	0
T13	650536	3594	0
T14	136952	1884	0
T15	363739	400	0
T16	285312	2218	0
T17	472256	1884	0
T18	38324	154	0
T19	0	1484	0
T20	19737	0	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	339513	0
T5	955160	222	0
T6	129660	163	0
T7	344047	163	0
T13	650536	374	0
T14	136952	289	0
T15	363739	44	0
T16	285312	197	0
T17	472256	289	0
T18	38324	15	0
T19	0	150	0
T20	19737	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		162	161	99.38
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	719	9	9	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
541	1	1
558	1	1
559	1	1
560	1	1
561	1	1
581	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
727	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T5,T6

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T7

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T7

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T7

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T14

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T13

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T5,T6

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T28,T29,T36
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T4,T5,T6

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	17	16	94.12
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1
StMessageWait	383	Covered	T1
StPad	389	Covered	T1
StPad01	427	Covered	T1
StPadFlush	435	Covered	T1
StPadIdle	333	Covered	T1
StPadRun	421	Covered	T1
StPrefix	328	Covered	T1
StPrefixWait	348	Covered	T1
StTerminalError	495	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	383	Covered	T1
StMessage->StPad	389	Covered	T1
StMessage->StTerminalError	495	Covered	T1
StMessageWait->StMessage	403	Covered	T1
StMessageWait->StTerminalError	495	Covered	T1
StPad->StPad01	427	Covered	T1
StPad->StPadRun	421	Covered	T1
StPad->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	452	Covered	T1
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Covered	T1
StPadFlush->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadIdle->StMessage	330	Covered	T1
StPadIdle->StPrefix	328	Covered	T1
StPadIdle->StTerminalError	495	Covered	T1
StPadRun->StPadFlush	435	Covered	T1
StPadRun->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	348	Covered	T1
StPrefix->StTerminalError	495	Excluded	T1	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefixWait->StMessage	364	Covered	T1
StPrefixWait->StTerminalError	495	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	719	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T20,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T4,T7,T13
L256	Covered	T4,T5,T6
L384	Covered	T6,T7,T14
L512	Covered	T5,T7,T84
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T6,T7,T15
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T5,T6,T7
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T5,T6,T7
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T5,T6,T7
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T6,T7
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T6,T7
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T5,T6,T13
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T5,T6,T7
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T6,T7
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T5,T6,T7
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T7
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T6,T7
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T6,T20,T7
CShake	Covered	T6,T20,T7
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T6,T7,T15
MuxFuncPad	Covered	T5,T6,T7
MuxZeroEnd	Covered	T5,T6,T7
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T6,T7,T15
MuxFuncPad	Covered	T5,T6,T7
MuxZeroEnd	Covered	T5,T6,T7
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T6,T7,T15
MuxFuncPad	Covered	T5,T6,T7
MuxZeroEnd	Covered	T5,T6,T7
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	719	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T5,T6,T7
7'b0000011	Covered	T5,T6,T7
7'b0000111	Covered	T5,T6,T7
7'b0001111	Covered	T5,T6,T7
7'b0011111	Covered	T5,T6,T7
7'b0111111	Covered	T5,T6,T7
7'b1111111	Covered	T5,T6,T7
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	350325	0	0
AlwaysPartialMsgBuf_M	2147483647	202079	0	0
CompleteBlockWhenProcess_A	2147483647	338703	0	0
DoneCondition_M	2147483647	350306	0	0
DonePulse_A	2147483647	350306	0	0
KeccakAddrInRange_A	2147483647	53927966	0	0
KeccakRunPulse_A	2147483647	3125349	0	0
MessageCondition_M	2147483647	49097305	0	0
ModeStableDuringOp_M	2147483647	36270	0	0
MsgReadyCondition_A	2147483647	2147483647	0	0
MsgWidthidth_A	1067	1067	0	0
NoPartialMsgFifo_M	2147483647	48895226	0	0
Pad01NotAttheEndOfBlock_A	2147483647	339513	0	0
PartialEndOfMsg_M	2147483647	202079	0	0
PrefixLessThanBlock_A	1067	1067	0	0
ProcessCondition_M	2147483647	350326	0	0
ProcessPulse_A	2147483647	350326	0	0
StartCondition_M	2147483647	350479	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	350479	0	0
StrengthStableDuringOp_M	2147483647	43858	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350325	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	202079	0	0
T5	955160	214	0	0
T6	129660	121	0	0
T7	344047	142	0	0
T13	650536	340	0	0
T14	136952	270	0	0
T15	363739	40	0	0
T16	285312	188	0	0
T17	472256	270	0	0
T18	38324	14	0	0
T19	0	125	0	0
T20	19737	0	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338703	0	0
T5	955160	219	0	0
T6	129660	160	0	0
T7	344047	163	0	0
T13	650536	374	0	0
T14	136952	287	0	0
T15	363739	44	0	0
T16	285312	194	0	0
T17	472256	289	0	0
T18	38324	15	0	0
T19	0	150	0	0
T20	19737	0	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350306	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350306	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53927966	0	0
T4	3713	1	0	0
T5	955160	48843	0	0
T6	129660	15325	0	0
T7	344047	7687	0	0
T13	650536	99756	0	0
T14	136952	71006	0	0
T15	363739	4696	0	0
T16	285312	79164	0	0
T17	472256	71006	0	0
T18	0	1680	0	0
T20	19737	0	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3125349	0	0
T5	955160	5427	0	0
T6	129660	833	0	0
T7	344047	413	0	0
T13	650536	5542	0	0
T14	136952	5462	0	0
T15	363739	256	0	0
T16	285312	4254	0	0
T17	472256	5462	0	0
T18	38324	88	0	0
T19	0	770	0	0
T20	19737	0	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49097305	0	0
T4	3713	1	0	0
T5	955160	47746	0	0
T6	129660	11675	0	0
T7	344047	2741	0	0
T13	650536	96112	0	0
T14	136952	69082	0	0
T15	363739	3676	0	0
T16	285312	73944	0	0
T17	472256	69082	0	0
T18	0	1316	0	0
T20	19737	0	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36270	0	0
T6	129660	158	0	0
T7	344047	70	0	0
T13	650536	0	0	0
T14	136952	0	0	0
T15	363739	23	0	0
T16	285312	99	0	0
T17	472256	0	0	0
T18	38324	9	0	0
T19	989452	150	0	0
T20	19737	12	0	0
T61	0	31	0	0
T80	0	1	0	0
T81	0	35	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	3713	97	0	0
T5	955160	756240	0	0
T6	129660	709856	0	0
T7	344047	41643	0	0
T13	650536	614040	0	0
T14	136952	115832	0	0
T15	363739	185997	0	0
T16	285312	523400	0	0
T17	472256	439700	0	0
T18	0	18468	0	0
T20	19737	0	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067	1067	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48895226	0	0
T4	3713	1	0	0
T5	955160	47532	0	0
T6	129660	11554	0	0
T7	344047	2599	0	0
T13	650536	95772	0	0
T14	136952	68812	0	0
T15	363739	3636	0	0
T16	285312	73756	0	0
T17	472256	68812	0	0
T18	0	1302	0	0
T20	19737	0	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	339513	0	0
T5	955160	222	0	0
T6	129660	163	0	0
T7	344047	163	0	0
T13	650536	374	0	0
T14	136952	289	0	0
T15	363739	44	0	0
T16	285312	197	0	0
T17	472256	289	0	0
T18	38324	15	0	0
T19	0	150	0	0
T20	19737	0	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	202079	0	0
T5	955160	214	0	0
T6	129660	121	0	0
T7	344047	142	0	0
T13	650536	340	0	0
T14	136952	270	0	0
T15	363739	40	0	0
T16	285312	188	0	0
T17	472256	270	0	0
T18	38324	14	0	0
T19	0	125	0	0
T20	19737	0	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067	1067	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350326	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350326	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	38324	17	0	0
T19	0	156	0	0
T20	19737	0	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350479	0	0
T4	3713	1	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	0	17	0	0
T20	19737	0	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	3713	3554	0	0
T5	955160	955093	0	0
T6	129660	129652	0	0
T7	344047	343973	0	0
T13	650536	650526	0	0
T14	136952	136942	0	0
T15	363739	363675	0	0
T16	285312	285299	0	0
T17	472256	472247	0	0
T20	19737	19637	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350479	0	0
T4	3713	1	0	0
T5	955160	246	0	0
T6	129660	169	0	0
T7	344047	163	0	0
T13	650536	390	0	0
T14	136952	310	0	0
T15	363739	47	0	0
T16	285312	209	0	0
T17	472256	310	0	0
T18	0	17	0	0
T20	19737	0	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43858	0	0
T4	3713	3	0	0
T5	955160	2	0	0
T6	129660	159	0	0
T7	344047	89	0	0
T13	650536	2	0	0
T14	136952	2	0	0
T15	363739	24	0	0
T16	285312	135	0	0
T17	472256	2	0	0
T20	19737	11	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	3713	3554	0	0
T5	955160	955093	0	0
T6	129660	129652	0	0
T7	344047	343973	0	0
T13	650536	650526	0	0
T14	136952	136942	0	0
T15	363739	363675	0	0
T16	285312	285299	0	0
T17	472256	472247	0	0
T20	19737	19637	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	8758129	0
StMessageFeed_C	2147483647	2147483647	0
StPadSendMsg_C	2147483647	3895386	0
StPad_C	2147483647	339513	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	8758129	0
T5	955160	6150	0
T6	129660	4225	0
T7	344047	4075	0
T13	650536	9750	0
T14	136952	7750	0
T15	363739	1175	0
T16	285312	5225	0
T17	472256	7750	0
T18	38324	425	0
T19	0	3900	0
T20	19737	0	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147483647	0
T4	3713	97	0
T5	955160	761667	0
T6	129660	710586	0
T7	344047	41931	0
T13	650536	614594	0
T14	136952	116378	0
T15	363739	186220	0
T16	285312	527497	0
T17	472256	440246	0
T18	0	18545	0
T20	19737	0	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3895386	0
T5	955160	1065	0
T6	129660	1699	0
T7	344047	2580	0
T13	650536	3594	0
T14	136952	1884	0
T15	363739	400	0
T16	285312	2218	0
T17	472256	1884	0
T18	38324	154	0
T19	0	1484	0
T20	19737	0	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	339513	0
T5	955160	222	0
T6	129660	163	0
T7	344047	163	0
T13	650536	374	0
T14	136952	289	0
T15	363739	44	0
T16	285312	197	0
T17	472256	289	0
T18	38324	15	0
T19	0	150	0
T20	19737	0	0