Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260623638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

209524602

1

T1

46

T2

1279

T3

481

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	247210392	1			T1	61		T2	632		T3	350
values[0x0]	106939186	1			T1	50		T2	338		T3	132
values[0x1]	115998662	1			T1	107		T2	309		T3	140

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202852737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

267295503

1

T1

119

T2

1279

T3

524

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1380488	1			T2	7		T57	1		T58	18
valid_sources[0x01]	1378576	1			T2	2		T57	6		T58	3
valid_sources[0x02]	1498706	1			T2	4		T58	6		T103	3
valid_sources[0x03]	1377705	1			T2	1		T57	10		T92	6
valid_sources[0x04]	1606825	1			T2	9		T57	10		T91	2
valid_sources[0x05]	1383897	1			T2	5		T57	1		T59	2
valid_sources[0x06]	3813933	1			T2	4		T58	4		T59	2
valid_sources[0x07]	1371312	1			T2	6		T57	11		T91	1
valid_sources[0x08]	1412443	1			T2	3		T57	1		T92	43
valid_sources[0x09]	1379836	1			T2	2		T57	11		T91	1
valid_sources[0x0a]	3894678	1			T2	11		T57	3		T58	13
valid_sources[0x0b]	1370046	1			T2	2		T57	1		T58	3
valid_sources[0x0c]	1379391	1			T1	50		T2	3		T57	8
valid_sources[0x0d]	5925782	1			T2	3		T57	3		T92	2
valid_sources[0x0e]	1384088	1			T2	4		T57	2		T92	7
valid_sources[0x0f]	3405151	1			T2	7		T103	3		T126	1
valid_sources[0x10]	1375125	1			T2	8		T57	4		T92	17
valid_sources[0x11]	1380482	1			T2	3		T3	118		T57	11
valid_sources[0x12]	1858778	1			T2	3		T57	2		T61	67
valid_sources[0x13]	1377681	1			T2	5		T57	14		T103	2
valid_sources[0x14]	1392866	1			T2	3		T57	18		T58	1
valid_sources[0x15]	2528171	1			T57	6		T91	1		T103	2
valid_sources[0x16]	1389817	1			T2	4		T57	4		T92	3
valid_sources[0x17]	1377984	1			T2	6		T57	18		T58	15
valid_sources[0x18]	2046069	1			T2	1		T57	4		T103	1
valid_sources[0x19]	2049786	1			T2	4		T58	2		T103	4
valid_sources[0x1a]	1385120	1			T2	3		T57	3		T91	1
valid_sources[0x1b]	3435603	1			T2	14		T57	14		T91	2
valid_sources[0x1c]	1393698	1			T1	31		T2	1		T57	15
valid_sources[0x1d]	1374254	1			T2	8		T57	5		T92	11
valid_sources[0x1e]	3796192	1			T2	3		T58	13		T59	2
valid_sources[0x1f]	3828893	1			T2	1		T57	5		T91	1
valid_sources[0x20]	2686174	1			T2	3		T57	3		T61	37
valid_sources[0x21]	3414462	1			T2	5		T57	18		T59	2
valid_sources[0x22]	1376361	1			T2	9		T57	1		T58	18
valid_sources[0x23]	1381390	1			T2	6		T57	5		T103	3
valid_sources[0x24]	1423301	1			T2	1		T57	4		T91	1
valid_sources[0x25]	1419592	1			T2	6		T57	9		T92	6
valid_sources[0x26]	2027290	1			T2	4		T57	2		T92	5
valid_sources[0x27]	3821643	1			T2	8		T92	19		T114	1
valid_sources[0x28]	1398415	1			T2	4		T57	3		T91	1
valid_sources[0x29]	1631286	1			T2	9		T58	11		T59	2
valid_sources[0x2a]	1379860	1			T2	6		T57	5		T58	2
valid_sources[0x2b]	1371684	1			T2	6		T58	28		T91	2
valid_sources[0x2c]	1414917	1			T2	2		T57	1		T92	4
valid_sources[0x2d]	1383976	1			T2	3		T57	21		T58	17
valid_sources[0x2e]	1380478	1			T2	10		T57	14		T59	2
valid_sources[0x2f]	2042669	1			T2	10		T58	14		T91	1
valid_sources[0x30]	1393226	1			T2	9		T57	7		T59	2
valid_sources[0x31]	1378111	1			T2	6		T57	11		T92	7
valid_sources[0x32]	1376506	1			T57	15		T92	1		T59	1
valid_sources[0x33]	3789099	1			T2	4		T57	14		T58	11
valid_sources[0x34]	1395432	1			T2	5		T57	2		T92	9
valid_sources[0x35]	1376777	1			T2	1		T57	4		T112	1
valid_sources[0x36]	3550890	1			T2	6		T57	12		T58	13
valid_sources[0x37]	1531773	1			T2	2		T57	2		T91	1
valid_sources[0x38]	1531279	1			T2	2		T57	7		T91	2
valid_sources[0x39]	1383819	1			T2	4		T57	13		T92	1
valid_sources[0x3a]	1377011	1			T2	4		T57	3		T103	2
valid_sources[0x3b]	1380590	1			T2	12		T57	5		T103	5
valid_sources[0x3c]	1371524	1			T2	10		T57	3		T59	1
valid_sources[0x3d]	1375901	1			T2	8		T57	9		T91	1
valid_sources[0x3e]	1375278	1			T2	4		T57	4		T92	5
valid_sources[0x3f]	1370687	1			T2	6		T57	2		T92	2
valid_sources[0x40]	1378961	1			T2	6		T57	18		T92	4
valid_sources[0x41]	1375878	1			T2	12		T57	9		T92	12
valid_sources[0x42]	1388369	1			T2	5		T57	1		T92	3
valid_sources[0x43]	2160503	1			T2	6		T57	6		T58	7
valid_sources[0x44]	1381889	1			T2	12		T57	3		T58	1
valid_sources[0x45]	1378099	1			T2	2		T57	4		T59	3
valid_sources[0x46]	1523156	1			T2	4		T57	4		T58	3
valid_sources[0x47]	1372315	1			T2	3		T57	4		T114	1
valid_sources[0x48]	1381509	1			T2	1		T57	11		T91	1
valid_sources[0x49]	4323515	1			T2	4		T57	6		T59	2
valid_sources[0x4a]	1373052	1			T2	5		T57	7		T58	25
valid_sources[0x4b]	1507972	1			T2	9		T57	3		T59	1
valid_sources[0x4c]	1373707	1			T2	4		T57	1		T92	18
valid_sources[0x4d]	1483331	1			T2	4		T57	2		T103	4
valid_sources[0x4e]	1785884	1			T2	4		T92	26		T103	4
valid_sources[0x4f]	3403776	1			T2	2		T57	6		T58	10
valid_sources[0x50]	2231284	1			T2	8		T57	4		T58	45
valid_sources[0x51]	1380230	1			T2	2		T57	1		T58	4
valid_sources[0x52]	2449952	1			T2	5		T57	4		T58	19
valid_sources[0x53]	3110018	1			T2	8		T57	1		T58	24
valid_sources[0x54]	1673719	1			T2	6		T57	2		T59	4
valid_sources[0x55]	1452541	1			T2	2		T57	7		T58	8
valid_sources[0x56]	1440113	1			T2	1		T57	5		T91	1
valid_sources[0x57]	1384589	1			T2	4		T57	7		T92	1
valid_sources[0x58]	1376632	1			T2	1		T57	3		T91	1
valid_sources[0x59]	1394620	1			T2	5		T3	55		T57	3
valid_sources[0x5a]	3503288	1			T2	9		T57	5		T58	5
valid_sources[0x5b]	2297703	1			T2	4		T57	10		T92	6
valid_sources[0x5c]	3870450	1			T2	3		T57	7		T68	61
valid_sources[0x5d]	1438536	1			T2	5		T57	12		T103	5
valid_sources[0x5e]	1387088	1			T2	3		T57	2		T58	6
valid_sources[0x5f]	1382004	1			T2	3		T57	20		T59	1
valid_sources[0x60]	1375929	1			T2	10		T57	1		T59	1
valid_sources[0x61]	2060837	1			T2	9		T57	6		T58	13
valid_sources[0x62]	1382722	1			T2	11		T57	8		T68	31
valid_sources[0x63]	1371098	1			T2	7		T57	2		T92	14
valid_sources[0x64]	1375753	1			T2	4		T91	1		T92	51
valid_sources[0x65]	3836237	1			T2	5		T57	6		T58	42
valid_sources[0x66]	1441605	1			T2	8		T58	11		T114	1
valid_sources[0x67]	1728814	1			T2	1		T91	1		T92	8
valid_sources[0x68]	1376979	1			T2	1		T57	22		T58	3
valid_sources[0x69]	1373145	1			T2	3		T57	4		T92	6
valid_sources[0x6a]	1480081	1			T2	4		T57	2		T58	5
valid_sources[0x6b]	1383906	1			T57	10		T58	12		T91	1
valid_sources[0x6c]	4036397	1			T1	2		T2	4		T57	5
valid_sources[0x6d]	2301384	1			T2	3		T57	4		T59	4
valid_sources[0x6e]	2006783	1			T2	1		T114	1		T103	2
valid_sources[0x6f]	2703605	1			T2	16		T57	10		T91	1
valid_sources[0x70]	2265035	1			T2	7		T57	13		T58	10
valid_sources[0x71]	1390532	1			T2	2		T57	9		T58	8
valid_sources[0x72]	2096736	1			T2	1		T114	1		T112	1
valid_sources[0x73]	1373778	1			T2	10		T57	13		T58	10
valid_sources[0x74]	1383843	1			T2	3		T92	8		T103	2
valid_sources[0x75]	2967815	1			T2	3		T57	10		T59	3
valid_sources[0x76]	1376714	1			T2	6		T57	2		T58	7
valid_sources[0x77]	2133206	1			T2	2		T57	3		T61	38
valid_sources[0x78]	2462318	1			T2	2		T57	4		T58	5
valid_sources[0x79]	1380890	1			T2	2		T57	14		T92	2
valid_sources[0x7a]	2056144	1			T2	9		T3	83		T57	17
valid_sources[0x7b]	2191017	1			T2	11		T57	5		T91	1
valid_sources[0x7c]	1377891	1			T2	3		T57	2		T92	10
valid_sources[0x7d]	1379208	1			T2	3		T57	2		T91	1
valid_sources[0x7e]	1381217	1			T2	7		T57	2		T58	18
valid_sources[0x7f]	1374888	1			T2	15		T57	6		T58	1
valid_sources[0x80]	1376111	1			T2	11		T57	7		T91	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

91070827

1

T1

30

T2

632

T3

214

values[0x0]

all_enables

biggest_size

63598568

1

T1

4

T2

338

T3

129

values[0x1]

all_enables

biggest_size

54855207

1

T1

12

T2

309

T3

138