Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

270071815

1

T1

172

T3

141

T57

355

full_word

210111118

1

T1

46

T2

1279

T3

481

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	480182613	1			T1	218		T2	1279		T3	622
auto[TlIntgErrCmd]	112	1			T120	11		T121	5		T122	5
auto[TlIntgErrData]	112	1			T120	8		T121	9		T122	9
auto[TlIntgErrBoth]	96	1			T120	1		T121	6		T122	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249014421

1

T1

61

T2

632

T3

350

auto[1]

231168512

1

T1

157

T2

647

T3

272

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157796556	1			T1	31		T3	136		T57	328
auto[TlIntgErrNone]	partial	auto[1]	112274966	1			T1	141		T3	5		T57	27
auto[TlIntgErrNone]	full_word	auto[0]	91217715	1			T1	30		T2	632		T3	214
auto[TlIntgErrNone]	full_word	auto[1]	118893376	1			T1	16		T2	647		T3	267
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T120	4		T121	2		T122	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T120	5		T121	3		T122	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T163	1		T164	1		T161	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T120	2		T162	1		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T120	2		T121	5		T122	5
auto[TlIntgErrData]	partial	auto[1]	50	1			T120	5		T121	4		T122	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T165	2		T166	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T120	1		T122	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T121	2		T122	4		T123	5
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T120	1		T121	4		T122	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T127	1		T167	1		T168	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T122	1		T167	1		T165	1