Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	98.55	92.86		100.00	92.00	88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	94.46	98.55	92.86		100.00	92.00	88.89

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	98.55	92.86		100.00	92.00	88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.80	98.75	92.86	100.00	100.00	92.31	90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.54	96.32	91.89	100.00	92.31	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		69	68	98.55
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	429	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
392	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
423	1	1
429	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T1
StKmacFlush	206	Covered	T1
StKmacIdle	181	Covered	T1
StKmacMsg	192	Covered	T1
StTerminalError	239	Covered	T1

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	192	Covered	T1
StKey->StTerminalError	239	Covered	T1
StKmacFlush->StKmacIdle	216	Covered	T1
StKmacFlush->StTerminalError	239	Covered	T1
StKmacIdle->StKey	179	Covered	T1
StKmacIdle->StTerminalError	239	Covered	T1
StKmacMsg->StKmacFlush	206	Covered	T1
StKmacMsg->StTerminalError	239	Covered	T1

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		50	46	92.00
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	418	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T4,T5,T6
StKmacIdle	0	-	-	-	Covered	T4,T5,T6
StKey	-	1	-	-	Covered	T4,T5,T6
StKey	-	0	-	-	Covered	T4,T5,T6
StKmacMsg	-	-	1	-	Covered	T4,T5,T6
StKmacMsg	-	-	0	-	Covered	T4,T5,T6
StKmacFlush	-	-	-	1	Covered	T4,T5,T6
StKmacFlush	-	-	-	0	Covered	T4,T5,T6
StTerminalError	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Not Covered
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T14,T15,T16
Key256	Covered	T4,T5,T6
Key384	Covered	T14,T15,T16
Key512	Covered	T14,T15,T16
default	Not Covered

	LineNo.	Expression
-1-:	418	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T15,T17,T19
L256	Covered	T4,T5,T6
L384	Covered	T17,T18,T19
L512	Covered	T16,T18,T35
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T14,T15,T16
Key256	Covered	T4,T5,T6
Key384	Covered	T14,T15,T16
Key512	Covered	T14,T15,T16
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	8997100	0	0
KeyDataStable_M	2147483647	594140	0	0
KeyLengthStable_M	2147483647	287255	0	0
KmacEnStable_M	2147483647	25162	0	0
MaxKeyLenMatchToKey512_A	1061	1061	0	0
ModeStable_M	2147483647	37531	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	45036	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8997100	0	0
T4	20918	109	0	0
T5	16778	109	0	0
T6	20852	109	0	0
T13	21533	109	0	0
T14	145902	0	0	0
T15	975860	0	0	0
T16	491374	0	0	0
T17	163311	2921	0	0
T18	296372	3899	0	0
T19	940916	5924	0	0
T29	0	26071	0	0
T31	0	37862	0	0
T32	0	2774	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	594140	0	0
T4	20918	8	0	0
T5	16778	8	0	0
T6	20852	8	0	0
T13	21533	8	0	0
T14	145902	0	0	0
T15	975860	0	0	0
T16	491374	0	0	0
T17	163311	780	0	0
T18	296372	894	0	0
T19	940916	908	0	0
T20	0	288	0	0
T29	0	1376	0	0
T31	0	2582	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	287255	0	0
T4	20918	1	0	0
T5	16778	1	0	0
T6	20852	1	0	0
T13	21533	1	0	0
T14	145902	1804	0	0
T15	975860	325	0	0
T16	491374	202	0	0
T17	163311	62	0	0
T18	296372	170	0	0
T19	940916	253	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25162	0	0
T4	20918	1	0	0
T5	16778	1	0	0
T6	20852	1	0	0
T13	21533	1	0	0
T14	145902	0	0	0
T15	975860	0	0	0
T16	491374	0	0	0
T17	163311	30	0	0
T18	296372	71	0	0
T19	940916	101	0	0
T20	0	32	0	0
T29	0	47	0	0
T31	0	114	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37531	0	0
T4	20918	1	0	0
T5	16778	1	0	0
T6	20852	1	0	0
T13	21533	1	0	0
T14	145902	1	0	0
T15	975860	0	0	0
T16	491374	0	0	0
T17	163311	40	0	0
T18	296372	130	0	0
T19	940916	262	0	0
T29	0	78	0	0
T31	0	209	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45036	0	0
T4	20918	2	0	0
T5	16778	2	0	0
T6	20852	2	0	0
T13	21533	2	0	0
T14	145902	2	0	0
T15	975860	2	0	0
T16	491374	2	0	0
T17	163311	42	0	0
T18	296372	121	0	0
T19	940916	256	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	20918	20835	0	0
T5	16778	16706	0	0
T6	20852	20788	0	0
T13	21533	21463	0	0
T14	145902	145901	0	0
T15	975860	975851	0	0
T16	491374	491368	0	0
T17	163311	163233	0	0
T18	296372	296301	0	0
T19	940916	940829	0	0