Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	121332103	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121332103	0	0
T1	2425	308	0	0
T2	12245	0	0	0
T3	3997	0	0	0
T57	11479	0	0	0
T58	11117	0	0	0
T59	0	307	0	0
T60	0	378	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T93	0	212	0	0
T94	0	471	0	0
T95	0	199	0	0
T96	0	95	0	0
T97	0	298	0	0
T100	0	67	0	0
T101	0	220	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T61	1	1	0	0
T68	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	230090705	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	230090705	0	0
T1	2425	154	0	0
T2	12245	0	0	0
T3	3997	0	0	0
T57	11479	0	0	0
T58	11117	0	0	0
T59	0	169	0	0
T60	0	373	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T93	0	201	0	0
T94	0	244	0	0
T95	0	140	0	0
T96	0	297	0	0
T97	0	224	0	0
T100	0	62	0	0
T101	0	116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T61	1	1	0	0
T68	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	326909638	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	326909638	0	0
T1	2425	123	0	0
T2	12245	2762	0	0
T3	3997	1217	0	0
T57	11479	2771	0	0
T58	11117	2446	0	0
T61	1829	260	0	0
T68	1209	241	0	0
T90	1232	1	0	0
T91	1947	130	0	0
T92	3608	2427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T61	1	1	0	0
T68	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	631825675	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	631825675	0	0
T1	2425	63	0	0
T2	12245	6015	0	0
T3	3997	622	0	0
T57	11479	4490	0	0
T58	11117	4435	0	0
T61	1829	142	0	0
T68	1209	122	0	0
T90	1232	1	0	0
T91	1947	120	0	0
T92	3608	1274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2425	2303	0	0
T2	12245	12160	0	0
T3	3997	3743	0	0
T57	11479	10965	0	0
T58	11117	11051	0	0
T61	1829	1482	0	0
T68	1209	1056	0	0
T90	1232	1134	0	0
T91	1947	1879	0	0
T92	3608	3522	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T61	1	1	0	0
T68	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0