Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.54	96.32	91.89	100.00	92.31	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2131698	0	0
entropy_period_rd_A	2147483647	4016	0	0
intr_enable_rd_A	2147483647	4509	0	0
prefix_0_rd_A	2147483647	3931	0	0
prefix_10_rd_A	2147483647	3782	0	0
prefix_1_rd_A	2147483647	4142	0	0
prefix_2_rd_A	2147483647	3977	0	0
prefix_3_rd_A	2147483647	4104	0	0
prefix_4_rd_A	2147483647	3935	0	0
prefix_5_rd_A	2147483647	4272	0	0
prefix_6_rd_A	2147483647	3970	0	0
prefix_7_rd_A	2147483647	3985	0	0
prefix_8_rd_A	2147483647	3882	0	0
prefix_9_rd_A	2147483647	4248	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2131698	0	0
T60	8303	240	0	0
T93	4781	151	0	0
T94	1599	5	0	0
T95	1637	76	0	0
T96	0	1	0	0
T97	0	141	0	0
T100	1997	0	0	0
T101	0	1	0	0
T103	6054	0	0	0
T112	5980	0	0	0
T113	8577	0	0	0
T121	0	3	0	0
T122	0	1	0	0
T123	0	2	0	0
T125	3038	0	0	0
T126	2374	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4016	0	0
T2	12245	60	0	0
T3	3997	0	0	0
T57	11479	32	0	0
T58	11117	21	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T103	0	24	0	0
T105	0	29	0	0
T114	1205	0	0	0
T120	0	66	0	0
T122	0	107	0	0
T123	0	123	0	0
T129	0	59	0	0
T148	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4509	0	0
T2	12245	18	0	0
T3	3997	0	0	0
T57	11479	47	0	0
T58	11117	10	0	0
T61	1829	0	0	0
T65	0	11	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	2	0	0
T103	0	18	0	0
T105	0	35	0	0
T114	1205	0	0	0
T120	0	45	0	0
T122	0	185	0	0
T129	0	52	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3931	0	0
T2	12245	70	0	0
T3	3997	0	0	0
T57	11479	26	0	0
T58	11117	10	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	6	0	0
T103	0	8	0	0
T105	0	11	0	0
T114	1205	0	0	0
T120	0	39	0	0
T122	0	79	0	0
T129	0	29	0	0
T148	0	1	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3782	0	0
T2	12245	19	0	0
T3	3997	0	0	0
T57	11479	26	0	0
T58	11117	16	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	8	0	0
T103	0	28	0	0
T105	0	39	0	0
T114	1205	0	0	0
T120	0	22	0	0
T122	0	65	0	0
T129	0	81	0	0
T148	0	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4142	0	0
T2	12245	15	0	0
T3	3997	0	0	0
T57	11479	22	0	0
T58	11117	22	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	5	0	0
T103	0	19	0	0
T105	0	28	0	0
T114	1205	0	0	0
T120	0	29	0	0
T122	0	98	0	0
T129	0	43	0	0
T148	0	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3977	0	0
T2	12245	43	0	0
T3	3997	0	0	0
T57	11479	30	0	0
T58	11117	19	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T103	0	12	0	0
T105	0	16	0	0
T114	1205	0	0	0
T120	0	44	0	0
T122	0	78	0	0
T123	0	32	0	0
T129	0	62	0	0
T148	0	7	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4104	0	0
T2	12245	70	0	0
T3	3997	0	0	0
T57	11479	49	0	0
T58	11117	38	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T103	0	14	0	0
T105	0	22	0	0
T114	1205	0	0	0
T120	0	41	0	0
T122	0	86	0	0
T123	0	43	0	0
T129	0	53	0	0
T148	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3935	0	0
T2	12245	36	0	0
T3	3997	0	0	0
T57	11479	28	0	0
T58	11117	11	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	9	0	0
T103	0	17	0	0
T105	0	31	0	0
T114	1205	0	0	0
T120	0	27	0	0
T122	0	103	0	0
T129	0	38	0	0
T148	0	17	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4272	0	0
T2	12245	90	0	0
T3	3997	0	0	0
T57	11479	23	0	0
T58	11117	36	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	1	0	0
T103	0	8	0	0
T105	0	18	0	0
T114	1205	0	0	0
T120	0	57	0	0
T122	0	66	0	0
T129	0	49	0	0
T148	0	10	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3970	0	0
T2	12245	42	0	0
T3	3997	0	0	0
T57	11479	29	0	0
T58	11117	28	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	8	0	0
T103	0	25	0	0
T105	0	35	0	0
T114	1205	0	0	0
T120	0	31	0	0
T122	0	82	0	0
T129	0	53	0	0
T148	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3985	0	0
T2	12245	8	0	0
T3	3997	0	0	0
T57	11479	34	0	0
T58	11117	34	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	2	0	0
T103	0	38	0	0
T105	0	25	0	0
T114	1205	0	0	0
T120	0	68	0	0
T122	0	103	0	0
T129	0	51	0	0
T148	0	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3882	0	0
T2	12245	52	0	0
T3	3997	0	0	0
T57	11479	19	0	0
T58	11117	25	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	3	0	0
T103	0	24	0	0
T105	0	17	0	0
T114	1205	0	0	0
T120	0	41	0	0
T122	0	78	0	0
T129	0	23	0	0
T148	0	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4248	0	0
T2	12245	45	0	0
T3	3997	0	0	0
T57	11479	35	0	0
T58	11117	9	0	0
T61	1829	0	0	0
T68	1209	0	0	0
T90	1232	0	0	0
T91	1947	0	0	0
T92	3608	0	0	0
T96	0	7	0	0
T103	0	8	0	0
T105	0	27	0	0
T114	1205	0	0	0
T120	0	53	0	0
T122	0	97	0	0
T129	0	33	0	0
T148	0	11	0	0