Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255250274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

200765257

1

T1

8104

T2

14256

T3

53672

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	240475072	1			T1	8535		T2	14853		T3	57291
values[0x0]	103453286	1			T1	1887		T2	3508		T3	13298
values[0x1]	112087173	1			T1	1961		T2	3718		T3	14041

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198825480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

257190051

1

T1

9009

T2

15965

T3

60767

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1449613	1			T1	7		T2	86		T3	22
valid_sources[0x01]	1441793	1			T1	2		T2	93		T3	27
valid_sources[0x02]	1881848	1			T1	2		T2	103		T3	17
valid_sources[0x03]	4769787	1			T1	5		T2	84		T3	27
valid_sources[0x04]	1522408	1			T1	2		T2	98		T3	23
valid_sources[0x05]	1443686	1			T1	5		T2	86		T3	32
valid_sources[0x06]	1433539	1			T1	2		T2	90		T3	34
valid_sources[0x07]	2346454	1			T1	3		T2	78		T3	27
valid_sources[0x08]	1562318	1			T1	2		T2	106		T3	27
valid_sources[0x09]	1471709	1			T1	2		T2	92		T3	31
valid_sources[0x0a]	1447949	1			T1	5		T2	89		T3	22
valid_sources[0x0b]	1428331	1			T1	1		T2	89		T3	28
valid_sources[0x0c]	1440870	1			T1	5		T2	72		T3	28
valid_sources[0x0d]	1443153	1			T1	2		T2	92		T3	22
valid_sources[0x0e]	3888807	1			T1	2		T2	85		T3	29
valid_sources[0x0f]	1439308	1			T1	3		T2	84		T3	21
valid_sources[0x10]	1436133	1			T1	7		T2	77		T3	24
valid_sources[0x11]	1443935	1			T1	3		T2	83		T3	26
valid_sources[0x12]	1432230	1			T1	6		T2	80		T3	30
valid_sources[0x13]	1441941	1			T1	5		T2	89		T3	30
valid_sources[0x14]	3327764	1			T1	2		T2	93		T3	16
valid_sources[0x15]	1514838	1			T1	4		T2	76		T3	78165
valid_sources[0x16]	1498013	1			T1	4		T2	98		T3	18
valid_sources[0x17]	1435346	1			T1	7		T2	95		T3	21
valid_sources[0x18]	1440552	1			T1	1		T2	96		T3	28
valid_sources[0x19]	1441401	1			T2	94		T3	27		T12	7572
valid_sources[0x1a]	1438741	1			T1	4		T2	99		T3	22
valid_sources[0x1b]	1883954	1			T1	2		T2	94		T3	20
valid_sources[0x1c]	1442907	1			T2	85		T3	26		T12	7655
valid_sources[0x1d]	1437636	1			T1	1		T2	91		T3	27
valid_sources[0x1e]	1442784	1			T1	5		T2	102		T3	29
valid_sources[0x1f]	1439659	1			T1	2		T2	72		T3	20
valid_sources[0x20]	1589461	1			T1	3		T2	89		T3	18
valid_sources[0x21]	1434923	1			T1	6		T2	80		T3	26
valid_sources[0x22]	1538017	1			T1	3		T2	84		T3	25
valid_sources[0x23]	1436193	1			T1	4		T2	80		T3	26
valid_sources[0x24]	3519545	1			T1	4		T2	99		T3	23
valid_sources[0x25]	1686090	1			T1	2		T2	101		T3	27
valid_sources[0x26]	1996036	1			T1	3		T2	98		T3	34
valid_sources[0x27]	1506069	1			T1	2		T2	105		T3	26
valid_sources[0x28]	1438874	1			T1	5		T2	76		T3	31
valid_sources[0x29]	2101889	1			T1	8		T2	95		T3	27
valid_sources[0x2a]	2500894	1			T1	5		T2	84		T3	26
valid_sources[0x2b]	1649478	1			T1	1		T2	71		T3	22
valid_sources[0x2c]	1459364	1			T1	3		T2	107		T3	28
valid_sources[0x2d]	1440312	1			T1	1		T2	84		T3	28
valid_sources[0x2e]	1433894	1			T1	4		T2	102		T3	20
valid_sources[0x2f]	1438395	1			T1	2		T2	84		T3	19
valid_sources[0x30]	1444467	1			T1	6		T2	89		T3	20
valid_sources[0x31]	2150169	1			T1	2		T2	88		T3	21
valid_sources[0x32]	1890048	1			T1	3		T2	90		T3	28
valid_sources[0x33]	1439327	1			T2	93		T3	25		T12	7651
valid_sources[0x34]	1437621	1			T1	4		T2	92		T3	21
valid_sources[0x35]	1443406	1			T1	4		T2	89		T3	22
valid_sources[0x36]	1428437	1			T1	10		T2	84		T3	30
valid_sources[0x37]	1441014	1			T1	9		T2	101		T3	19
valid_sources[0x38]	4035345	1			T1	4		T2	100		T3	24
valid_sources[0x39]	1437274	1			T2	94		T3	25		T12	7564
valid_sources[0x3a]	1448947	1			T1	3		T2	88		T3	26
valid_sources[0x3b]	3555569	1			T1	3		T2	86		T3	22
valid_sources[0x3c]	1442643	1			T1	6		T2	94		T3	26
valid_sources[0x3d]	1447553	1			T1	3		T2	94		T3	23
valid_sources[0x3e]	1894878	1			T1	3		T2	90		T3	31
valid_sources[0x3f]	1512754	1			T1	5		T2	83		T3	26
valid_sources[0x40]	1474138	1			T1	3		T2	91		T3	27
valid_sources[0x41]	1439788	1			T1	3		T2	93		T3	26
valid_sources[0x42]	1965171	1			T1	6		T2	74		T3	32
valid_sources[0x43]	1439250	1			T1	3		T2	103		T3	31
valid_sources[0x44]	1438758	1			T1	3		T2	100		T3	19
valid_sources[0x45]	2788897	1			T1	4		T2	100		T3	31
valid_sources[0x46]	1433263	1			T1	3		T2	91		T3	36
valid_sources[0x47]	1442761	1			T1	5		T2	78		T3	21
valid_sources[0x48]	2300634	1			T1	5		T2	84		T3	22
valid_sources[0x49]	1436591	1			T1	3		T2	84		T3	24
valid_sources[0x4a]	1434681	1			T1	1		T2	92		T3	21
valid_sources[0x4b]	1439681	1			T1	5		T2	90		T3	27
valid_sources[0x4c]	2361889	1			T1	5		T2	83		T3	32
valid_sources[0x4d]	1438384	1			T1	2		T2	85		T3	22
valid_sources[0x4e]	1432828	1			T1	5		T2	66		T3	31
valid_sources[0x4f]	1441628	1			T1	10		T2	82		T3	29
valid_sources[0x50]	1448366	1			T2	85		T3	15		T12	7956
valid_sources[0x51]	1438775	1			T1	4		T2	87		T3	20
valid_sources[0x52]	1433976	1			T1	4		T2	81		T3	25
valid_sources[0x53]	2268432	1			T1	4		T2	82		T3	27
valid_sources[0x54]	1434005	1			T1	5		T2	85		T3	30
valid_sources[0x55]	2460044	1			T1	5		T2	68		T3	26
valid_sources[0x56]	1447935	1			T1	4		T2	95		T3	18
valid_sources[0x57]	1445331	1			T1	1		T2	76		T3	26
valid_sources[0x58]	3494543	1			T1	7		T2	80		T3	41
valid_sources[0x59]	1829313	1			T1	5		T2	74		T3	16
valid_sources[0x5a]	1444654	1			T1	3		T2	103		T3	19
valid_sources[0x5b]	2231395	1			T2	100		T3	28		T12	8298
valid_sources[0x5c]	1636403	1			T1	1		T2	92		T3	25
valid_sources[0x5d]	2302275	1			T1	4		T2	76		T3	25
valid_sources[0x5e]	2655333	1			T1	3		T2	78		T3	29
valid_sources[0x5f]	2093770	1			T1	3		T2	86		T3	26
valid_sources[0x60]	1890106	1			T1	5		T2	92		T3	28
valid_sources[0x61]	1438812	1			T1	2		T2	97		T3	23
valid_sources[0x62]	1613070	1			T1	8		T2	84		T3	25
valid_sources[0x63]	1437482	1			T1	2		T2	87		T3	27
valid_sources[0x64]	3851626	1			T1	1		T2	81		T3	28
valid_sources[0x65]	1442929	1			T1	2		T2	99		T3	19
valid_sources[0x66]	1437547	1			T1	4		T2	93		T3	24
valid_sources[0x67]	1561663	1			T1	4		T2	90		T3	27
valid_sources[0x68]	1439654	1			T1	3		T2	88		T3	30
valid_sources[0x69]	2475366	1			T1	7		T2	93		T3	23
valid_sources[0x6a]	1464349	1			T1	6		T2	83		T3	26
valid_sources[0x6b]	1433333	1			T1	2		T2	89		T3	24
valid_sources[0x6c]	1446510	1			T1	2		T2	92		T3	26
valid_sources[0x6d]	1436127	1			T1	2		T2	78		T3	24
valid_sources[0x6e]	1439755	1			T1	5		T2	75		T3	20
valid_sources[0x6f]	1444852	1			T1	7		T2	89		T3	25
valid_sources[0x70]	1430199	1			T1	4		T2	98		T3	39
valid_sources[0x71]	1492625	1			T1	3		T2	73		T3	30
valid_sources[0x72]	1480626	1			T1	5		T2	107		T3	30
valid_sources[0x73]	1441276	1			T1	5		T2	96		T3	17
valid_sources[0x74]	1438695	1			T2	70		T3	22		T12	7624
valid_sources[0x75]	1445112	1			T1	4		T2	85		T3	25
valid_sources[0x76]	1488126	1			T1	5		T2	83		T3	24
valid_sources[0x77]	3882603	1			T1	3		T2	81		T3	26
valid_sources[0x78]	2304518	1			T1	1		T2	78		T3	22
valid_sources[0x79]	1442746	1			T1	4		T2	102		T3	33
valid_sources[0x7a]	1433350	1			T1	2		T2	89		T3	19
valid_sources[0x7b]	1443138	1			T1	4		T2	82		T3	26
valid_sources[0x7c]	1434468	1			T1	2		T2	78		T3	23
valid_sources[0x7d]	1451024	1			T1	4		T2	91		T3	27
valid_sources[0x7e]	1448652	1			T1	2		T2	79		T3	28
valid_sources[0x7f]	1437297	1			T1	2		T2	83		T3	37
valid_sources[0x80]	1897559	1			T1	4		T2	100		T3	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87591077

1

T1

5817

T2

9969

T3

38716

values[0x0]

all_enables

biggest_size

60886092

1

T1

1254

T2

2279

T3

8117

values[0x1]

all_enables

biggest_size

52288088

1

T1

1033

T2

2008

T3

6839