| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| cip_base_pkg.dut_and_edn_rsts | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 4 | 0 | 4 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| resets_trans | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 4 | 0 | 4 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| rst1_start_last_end_first | 283 | 1 | T4 | 24 | T5 | 1 | T33 | 1 | ||||
| rst1_start_first_end_last | 340 | 1 | T4 | 30 | T27 | 1 | T34 | 1 | ||||
| rst1_start_last_end_last | 614 | 1 | T4 | 23 | T6 | 1 | T27 | 8 | ||||
| rst1_start_first_end_first | 462 | 1 | T4 | 31 | T9 | 1 | T91 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |