Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259427940

1

T1

4279

T2

7823

T3

30958

full_word

201024810

1

T1

8104

T2

14256

T3

53672

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	460452450	1			T1	12383		T2	22079		T3	84630
auto[TlIntgErrCmd]	95	1			T96	3		T97	5		T98	8
auto[TlIntgErrData]	92	1			T96	3		T97	8		T98	6
auto[TlIntgErrBoth]	113	1			T96	4		T97	7		T98	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241265716

1

T1

8535

T2

14853

T3

57291

auto[1]

219187034

1

T1

3848

T2

7226

T3

27339

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153610082	1			T1	2718		T2	4884		T3	18575
auto[TlIntgErrNone]	partial	auto[1]	105817579	1			T1	1561		T2	2939		T3	12383
auto[TlIntgErrNone]	full_word	auto[0]	87655498	1			T1	5817		T2	9969		T3	38716
auto[TlIntgErrNone]	full_word	auto[1]	113369291	1			T1	2287		T2	4287		T3	14956
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T96	1		T97	3		T98	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T96	2		T97	1		T98	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T154	1		T155	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T97	1		T98	1		T156	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T97	4		T98	5		T156	3
auto[TlIntgErrData]	partial	auto[1]	30	1			T96	2		T97	3		T98	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T97	1		T132	1		T157	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T96	1		T157	1		T158	2
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T97	4		T98	2		T156	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T96	4		T97	3		T98	4
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T155	1		T159	3		T160	1