Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256902706

1

T1

438

T2

7

T3

402357

full_word

200921463

1

T1

5172

T2

149

T3

261901

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	457823849	1			T1	5610		T2	156		T3	664258
auto[TlIntgErrCmd]	117	1			T130	6		T131	7		T132	6
auto[TlIntgErrData]	96	1			T130	6		T131	3		T132	5
auto[TlIntgErrBoth]	107	1			T130	8		T131	10		T132	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240844986

1

T1

1074

T2

74

T3

340393

auto[1]

216979183

1

T1

4536

T2

82

T3

323865

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153089388	1			T1	343		T2	3		T3	240511
auto[TlIntgErrNone]	partial	auto[1]	103813026	1			T1	95		T2	4		T3	161846
auto[TlIntgErrNone]	full_word	auto[0]	87755445	1			T1	731		T2	71		T3	99882
auto[TlIntgErrNone]	full_word	auto[1]	113165990	1			T1	4441		T2	78		T3	162019
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T130	3		T131	5		T132	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T130	2		T131	2		T132	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T197	1		T198	1		T199	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T130	1		T132	1		T200	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T130	3		T131	2		T132	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T130	2		T131	1		T132	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T200	1		T166	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T130	1		T200	2		T166	2
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T130	5		T131	2		T132	4
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T130	2		T131	8		T132	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T130	1		T191	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T132	1		T191	2		T192	1