Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	567860	0	0
entropy_period_rd_A	2147483647	2227	0	0
intr_enable_rd_A	2147483647	2884	0	0
prefix_0_rd_A	2147483647	2308	0	0
prefix_10_rd_A	2147483647	2314	0	0
prefix_1_rd_A	2147483647	2443	0	0
prefix_2_rd_A	2147483647	2347	0	0
prefix_3_rd_A	2147483647	2268	0	0
prefix_4_rd_A	2147483647	2287	0	0
prefix_5_rd_A	2147483647	2307	0	0
prefix_6_rd_A	2147483647	2352	0	0
prefix_7_rd_A	2147483647	2254	0	0
prefix_8_rd_A	2147483647	2311	0	0
prefix_9_rd_A	2147483647	2174	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	567860	0	0
T34	3862	0	0	0
T39	214225	24717	0	0
T66	0	103884	0	0
T67	0	66522	0	0
T116	362914	0	0	0
T117	142645	0	0	0
T118	375214	0	0	0
T136	0	119742	0	0
T137	0	27952	0	0
T138	0	25379	0	0
T139	0	80465	0	0
T140	0	45337	0	0
T141	0	19461	0	0
T142	0	50943	0	0
T143	510321	0	0	0
T144	15957	0	0	0
T145	184774	0	0	0
T146	132869	0	0	0
T147	170804	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T104	11793	59	0	0
T105	12323	27	0	0
T111	2021	8	0	0
T115	7464	44	0	0
T157	78205	137	0	0
T158	5346	16	0	0
T159	12530	33	0	0
T160	11017	29	0	0
T161	5598	32	0	0
T162	2704	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2884	0	0
T104	11793	46	0	0
T105	12323	32	0	0
T115	7464	61	0	0
T133	1246	20	0	0
T157	78205	236	0	0
T158	5346	7	0	0
T159	12530	70	0	0
T160	11017	22	0	0
T161	5598	11	0	0
T163	10436	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2308	0	0
T104	11793	17	0	0
T105	12323	32	0	0
T111	2021	7	0	0
T115	7464	13	0	0
T157	78205	230	0	0
T158	5346	4	0	0
T159	12530	7	0	0
T160	11017	29	0	0
T161	5598	13	0	0
T162	2704	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2314	0	0
T104	11793	42	0	0
T105	12323	27	0	0
T111	2021	9	0	0
T115	7464	21	0	0
T157	78205	238	0	0
T158	5346	25	0	0
T159	12530	31	0	0
T160	11017	29	0	0
T161	5598	3	0	0
T162	2704	11	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2443	0	0
T104	11793	27	0	0
T105	12323	26	0	0
T111	2021	1	0	0
T115	7464	40	0	0
T157	78205	252	0	0
T159	12530	71	0	0
T161	5598	30	0	0
T162	2704	15	0	0
T164	2098	1	0	0
T165	2154	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T104	11793	35	0	0
T105	12323	18	0	0
T111	2021	8	0	0
T115	7464	31	0	0
T157	78205	259	0	0
T158	5346	1	0	0
T159	12530	40	0	0
T160	11017	15	0	0
T161	5598	19	0	0
T162	2704	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2268	0	0
T104	11793	45	0	0
T105	12323	43	0	0
T111	2021	9	0	0
T115	7464	24	0	0
T157	78205	173	0	0
T158	5346	24	0	0
T159	12530	12	0	0
T160	11017	32	0	0
T161	5598	19	0	0
T162	2704	6	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T104	11793	13	0	0
T105	12323	49	0	0
T111	2021	8	0	0
T115	7464	29	0	0
T157	78205	246	0	0
T159	12530	46	0	0
T160	11017	25	0	0
T161	5598	7	0	0
T162	2704	8	0	0
T163	10436	6	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2307	0	0
T104	11793	31	0	0
T105	12323	33	0	0
T115	7464	23	0	0
T157	78205	183	0	0
T158	5346	3	0	0
T159	12530	51	0	0
T160	11017	28	0	0
T161	5598	35	0	0
T162	2704	11	0	0
T166	25016	88	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2352	0	0
T104	11793	18	0	0
T105	12323	19	0	0
T115	7464	25	0	0
T157	78205	236	0	0
T158	5346	12	0	0
T159	12530	39	0	0
T160	11017	33	0	0
T161	5598	8	0	0
T162	2704	8	0	0
T163	10436	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2254	0	0
T104	11793	27	0	0
T105	12323	25	0	0
T111	2021	3	0	0
T115	7464	34	0	0
T157	78205	220	0	0
T158	5346	9	0	0
T159	12530	41	0	0
T160	11017	59	0	0
T161	5598	18	0	0
T162	2704	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2311	0	0
T104	11793	32	0	0
T105	12323	16	0	0
T111	2021	4	0	0
T115	7464	37	0	0
T157	78205	229	0	0
T158	5346	5	0	0
T159	12530	24	0	0
T160	11017	29	0	0
T161	5598	4	0	0
T162	2704	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2174	0	0
T104	11793	41	0	0
T105	12323	32	0	0
T111	2021	5	0	0
T115	7464	14	0	0
T157	78205	236	0	0
T159	12530	44	0	0
T160	11017	58	0	0
T161	5598	2	0	0
T162	2704	5	0	0
T164	2098	2	0	0