Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258720789

1

T1

397620

T2

272603

T3

75457

full_word

203122790

1

T1

262009

T2

184239

T3

129856

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	461843309	1			T1	659629		T2	456842		T3	205313
auto[TlIntgErrCmd]	101	1			T108	5		T109	4		T110	6
auto[TlIntgErrData]	80	1			T108	7		T109	4		T110	3
auto[TlIntgErrBoth]	89	1			T108	8		T109	2		T110	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242610043

1

T1

338099

T2

235479

T3

137663

auto[1]

219233536

1

T1

321530

T2

221363

T3

67650

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153968590	1			T1	238673		T2	163979		T3	45730
auto[TlIntgErrNone]	partial	auto[1]	104751952	1			T1	158947		T2	108624		T3	29727
auto[TlIntgErrNone]	full_word	auto[0]	88641326	1			T1	99426		T2	71500		T3	91933
auto[TlIntgErrNone]	full_word	auto[1]	114481441	1			T1	162583		T2	112739		T3	37923
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T108	2		T109	1		T110	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T108	3		T109	3		T110	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T167	1		T168	1		T169	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T170	1		T171	1		-	-
auto[TlIntgErrData]	partial	auto[0]	33	1			T108	4		T109	2		T110	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T108	2		T109	2		T110	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T108	1		T162	1		T172	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T164	1		T167	1		T166	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T108	2		T109	1		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T108	6		T109	1		T161	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T161	1		T165	1		T172	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T161	1		T165	1		T166	2