Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

255970209

1

T1

45374

T2

105673

T3

51

full_word

200770462

1

T1

91422

T2

81620

T3

218

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456740421	1			T1	136796		T2	187293		T3	269
auto[TlIntgErrCmd]	96	1			T110	6		T111	4		T112	5
auto[TlIntgErrData]	79	1			T110	3		T111	3		T112	10
auto[TlIntgErrBoth]	75	1			T110	1		T111	3		T112	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239903075

1

T1

96366

T2

98812

T3

120

auto[1]

216837596

1

T1

40430

T2

88481

T3

149

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152617995	1			T1	27954		T2	66610		T3	21
auto[TlIntgErrNone]	partial	auto[1]	103351995	1			T1	17420		T2	39063		T3	30
auto[TlIntgErrNone]	full_word	auto[0]	87284970	1			T1	68412		T2	32202		T3	99
auto[TlIntgErrNone]	full_word	auto[1]	113485461	1			T1	23010		T2	49418		T3	119
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T110	2		T111	1		T112	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T110	4		T111	3		T112	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T180	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T112	1		T175	1		T181	1
auto[TlIntgErrData]	partial	auto[0]	26	1			T110	1		T111	2		T112	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T110	2		T111	1		T112	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T182	1		T183	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	10	1			T112	2		T184	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T111	2		T112	2		T145	1
auto[TlIntgErrBoth]	partial	auto[1]	35	1			T110	1		T111	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T112	2		T184	1		T181	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T178	1		T186	1		-	-