Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	544300	0	0
entropy_period_rd_A	2147483647	2381	0	0
intr_enable_rd_A	2147483647	3634	0	0
prefix_0_rd_A	2147483647	2681	0	0
prefix_10_rd_A	2147483647	2476	0	0
prefix_1_rd_A	2147483647	2659	0	0
prefix_2_rd_A	2147483647	2618	0	0
prefix_3_rd_A	2147483647	2665	0	0
prefix_4_rd_A	2147483647	2631	0	0
prefix_5_rd_A	2147483647	2575	0	0
prefix_6_rd_A	2147483647	2618	0	0
prefix_7_rd_A	2147483647	2682	0	0
prefix_8_rd_A	2147483647	2672	0	0
prefix_9_rd_A	2147483647	2634	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	544300	0	0
T44	993171	14659	0	0
T45	0	112587	0	0
T46	0	93513	0	0
T118	0	16878	0	0
T119	0	36696	0	0
T120	0	27574	0	0
T121	0	60818	0	0
T122	0	41983	0	0
T123	0	32048	0	0
T124	0	103892	0	0
T125	520278	0	0	0
T126	960309	0	0	0
T127	178000	0	0	0
T128	134018	0	0	0
T129	134247	0	0	0
T130	58672	0	0	0
T131	17543	0	0	0
T132	1275	0	0	0
T133	133877	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T93	0	17	0	0
T95	0	14	0	0
T103	0	14	0	0
T110	0	37	0	0
T119	416076	121	0	0
T123	0	44	0	0
T124	0	96	0	0
T143	0	40	0	0
T144	0	10	0	0
T145	0	50	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3634	0	0
T93	0	23	0	0
T95	0	16	0	0
T103	0	8	0	0
T110	0	62	0	0
T119	416076	73	0	0
T123	0	31	0	0
T124	0	96	0	0
T143	0	17	0	0
T144	0	22	0	0
T145	0	111	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2681	0	0
T93	0	25	0	0
T95	0	18	0	0
T103	0	12	0	0
T110	0	20	0	0
T119	416076	75	0	0
T123	0	81	0	0
T124	0	140	0	0
T143	0	16	0	0
T144	0	18	0	0
T145	0	43	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2476	0	0
T93	0	17	0	0
T95	0	22	0	0
T103	0	6	0	0
T110	0	18	0	0
T119	416076	44	0	0
T123	0	19	0	0
T124	0	147	0	0
T143	0	25	0	0
T144	0	20	0	0
T145	0	38	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2659	0	0
T93	0	29	0	0
T95	0	16	0	0
T103	0	13	0	0
T110	0	25	0	0
T119	416076	93	0	0
T123	0	55	0	0
T124	0	107	0	0
T143	0	24	0	0
T144	0	17	0	0
T145	0	36	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2618	0	0
T93	0	30	0	0
T95	0	24	0	0
T103	0	4	0	0
T110	0	22	0	0
T119	416076	123	0	0
T123	0	46	0	0
T124	0	128	0	0
T143	0	23	0	0
T144	0	14	0	0
T145	0	43	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2665	0	0
T93	0	23	0	0
T95	0	11	0	0
T103	0	6	0	0
T110	0	10	0	0
T119	416076	118	0	0
T123	0	58	0	0
T124	0	116	0	0
T143	0	13	0	0
T144	0	27	0	0
T145	0	25	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2631	0	0
T93	0	23	0	0
T95	0	18	0	0
T103	0	14	0	0
T110	0	28	0	0
T119	416076	124	0	0
T123	0	41	0	0
T124	0	141	0	0
T143	0	42	0	0
T144	0	5	0	0
T145	0	37	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2575	0	0
T93	0	25	0	0
T95	0	9	0	0
T103	0	7	0	0
T110	0	23	0	0
T119	416076	137	0	0
T123	0	43	0	0
T124	0	190	0	0
T143	0	46	0	0
T144	0	16	0	0
T145	0	30	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2618	0	0
T93	0	16	0	0
T95	0	9	0	0
T103	0	13	0	0
T110	0	29	0	0
T119	416076	92	0	0
T123	0	45	0	0
T124	0	140	0	0
T143	0	10	0	0
T144	0	16	0	0
T145	0	40	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2682	0	0
T93	0	18	0	0
T95	0	10	0	0
T103	0	12	0	0
T110	0	11	0	0
T119	416076	192	0	0
T123	0	70	0	0
T124	0	225	0	0
T143	0	26	0	0
T144	0	24	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0
T155	0	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2672	0	0
T93	0	23	0	0
T95	0	20	0	0
T103	0	9	0	0
T110	0	17	0	0
T119	416076	158	0	0
T123	0	17	0	0
T124	0	113	0	0
T143	0	12	0	0
T144	0	12	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0
T155	0	15	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2634	0	0
T93	0	14	0	0
T95	0	4	0	0
T103	0	13	0	0
T110	0	21	0	0
T119	416076	152	0	0
T123	0	63	0	0
T124	0	179	0	0
T143	0	3	0	0
T144	0	12	0	0
T145	0	39	0	0
T146	45574	0	0	0
T147	213450	0	0	0
T148	179199	0	0	0
T149	187472	0	0	0
T150	418802	0	0	0
T151	500144	0	0	0
T152	17497	0	0	0
T153	180278	0	0	0
T154	512867	0	0	0