Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260984084

1

T1

34668

T2

59990

T3

29577

full_word

203807809

1

T1

61753

T2

93069

T3

157684

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	464791553	1			T1	96421		T2	153059		T3	187261
auto[TlIntgErrCmd]	120	1			T118	10		T119	2		T120	7
auto[TlIntgErrData]	113	1			T118	4		T119	3		T120	8
auto[TlIntgErrBoth]	107	1			T118	6		T119	5		T120	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244776350

1

T1

68088

T2

104678

T3

62884

auto[1]

220015543

1

T1

28333

T2

48381

T3

124377

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155950649	1			T1	22000		T2	38057		T3	27932
auto[TlIntgErrNone]	partial	auto[1]	105033123	1			T1	12668		T2	21933		T3	1645
auto[TlIntgErrNone]	full_word	auto[0]	88825549	1			T1	46088		T2	66621		T3	34952
auto[TlIntgErrNone]	full_word	auto[1]	114982232	1			T1	15665		T2	26448		T3	122732
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T118	4		T120	4		T142	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T118	5		T119	1		T120	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T118	1		T172	1		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T119	1		T120	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T118	1		T119	2		T120	4
auto[TlIntgErrData]	partial	auto[1]	52	1			T118	2		T119	1		T120	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T172	2		T175	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T118	1		T176	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T118	3		T119	3		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T118	3		T119	2		T120	3
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T174	1		T178	3		T173	1