Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	369866	0	0
entropy_period_rd_A	2147483647	1509	0	0
intr_enable_rd_A	2147483647	2228	0	0
prefix_0_rd_A	2147483647	1705	0	0
prefix_10_rd_A	2147483647	1620	0	0
prefix_1_rd_A	2147483647	1603	0	0
prefix_2_rd_A	2147483647	1538	0	0
prefix_3_rd_A	2147483647	1577	0	0
prefix_4_rd_A	2147483647	1581	0	0
prefix_5_rd_A	2147483647	1620	0	0
prefix_6_rd_A	2147483647	1705	0	0
prefix_7_rd_A	2147483647	1543	0	0
prefix_8_rd_A	2147483647	1701	0	0
prefix_9_rd_A	2147483647	1559	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	369866	0	0
T4	6905	0	0	0
T17	216724	24911	0	0
T18	21148	0	0	0
T42	2752	0	0	0
T45	0	55813	0	0
T46	0	32388	0	0
T77	177493	0	0	0
T79	223834	0	0	0
T86	183940	0	0	0
T87	505639	0	0	0
T88	295906	0	0	0
T89	462419	0	0	0
T118	0	2	0	0
T124	0	78603	0	0
T125	0	75564	0	0
T126	0	33363	0	0
T127	0	65534	0	0
T128	0	324	0	0
T129	0	84	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1509	0	0
T46	374424	104	0	0
T107	0	33	0	0
T120	0	133	0	0
T123	0	13	0	0
T137	0	8	0	0
T138	0	16	0	0
T139	0	9	0	0
T140	0	16	0	0
T141	0	3	0	0
T142	0	92	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2228	0	0
T46	374424	88	0	0
T107	0	63	0	0
T120	0	160	0	0
T121	0	9	0	0
T122	0	30	0	0
T123	0	11	0	0
T137	0	3	0	0
T138	0	21	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0
T152	0	27	0	0
T153	0	26	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1705	0	0
T46	374424	100	0	0
T101	0	57	0	0
T107	0	25	0	0
T120	0	71	0	0
T123	0	8	0	0
T137	0	7	0	0
T138	0	11	0	0
T139	0	2	0	0
T140	0	6	0	0
T142	0	104	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1620	0	0
T46	374424	79	0	0
T101	0	72	0	0
T107	0	35	0	0
T120	0	78	0	0
T123	0	6	0	0
T137	0	4	0	0
T138	0	21	0	0
T139	0	5	0	0
T140	0	5	0	0
T142	0	82	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1603	0	0
T46	374424	118	0	0
T101	0	56	0	0
T107	0	30	0	0
T120	0	60	0	0
T123	0	6	0	0
T137	0	6	0	0
T138	0	22	0	0
T139	0	11	0	0
T140	0	8	0	0
T142	0	87	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T46	374424	59	0	0
T101	0	62	0	0
T107	0	14	0	0
T120	0	81	0	0
T123	0	1	0	0
T137	0	9	0	0
T138	0	17	0	0
T139	0	11	0	0
T140	0	10	0	0
T142	0	106	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1577	0	0
T46	374424	76	0	0
T101	0	77	0	0
T107	0	40	0	0
T120	0	72	0	0
T123	0	10	0	0
T137	0	2	0	0
T138	0	18	0	0
T139	0	7	0	0
T140	0	3	0	0
T142	0	83	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1581	0	0
T46	374424	88	0	0
T101	0	63	0	0
T107	0	29	0	0
T120	0	85	0	0
T123	0	4	0	0
T137	0	9	0	0
T138	0	13	0	0
T139	0	15	0	0
T140	0	10	0	0
T142	0	83	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1620	0	0
T46	374424	74	0	0
T101	0	58	0	0
T107	0	18	0	0
T120	0	78	0	0
T123	0	8	0	0
T137	0	4	0	0
T138	0	6	0	0
T139	0	5	0	0
T140	0	12	0	0
T142	0	79	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1705	0	0
T46	374424	107	0	0
T101	0	53	0	0
T107	0	24	0	0
T120	0	89	0	0
T123	0	5	0	0
T137	0	6	0	0
T138	0	15	0	0
T139	0	12	0	0
T140	0	8	0	0
T142	0	84	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1543	0	0
T46	374424	105	0	0
T101	0	64	0	0
T107	0	33	0	0
T120	0	75	0	0
T123	0	14	0	0
T137	0	9	0	0
T138	0	21	0	0
T139	0	1	0	0
T140	0	3	0	0
T142	0	59	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1701	0	0
T46	374424	90	0	0
T101	0	69	0	0
T107	0	24	0	0
T120	0	81	0	0
T123	0	12	0	0
T137	0	4	0	0
T138	0	10	0	0
T139	0	12	0	0
T140	0	10	0	0
T142	0	66	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1559	0	0
T46	374424	91	0	0
T101	0	69	0	0
T107	0	19	0	0
T120	0	108	0	0
T123	0	6	0	0
T137	0	6	0	0
T138	0	15	0	0
T139	0	10	0	0
T140	0	3	0	0
T142	0	68	0	0
T143	2968	0	0	0
T144	6585	0	0	0
T145	422564	0	0	0
T146	17448	0	0	0
T147	506316	0	0	0
T148	172757	0	0	0
T149	1475	0	0	0
T150	25405	0	0	0
T151	478748	0	0	0