Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254470332

1

T1

61564

T2

985

T3

141276

full_word

200094754

1

T1

107223

T2

1702

T3

100323

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454564756	1			T1	168787		T2	2687		T3	241599
auto[TlIntgErrCmd]	106	1			T110	3		T111	5		T112	3
auto[TlIntgErrData]	112	1			T110	7		T111	8		T112	4
auto[TlIntgErrBoth]	112	1			T110	10		T111	7		T112	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238979926

1

T1

114759

T2

1737

T3

126995

auto[1]

215585160

1

T1

54028

T2

950

T3

114603

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152118665	1			T1	37339		T2	568		T3	842625
auto[TlIntgErrNone]	partial	auto[1]	102351360	1			T1	24225		T2	417		T3	570138
auto[TlIntgErrNone]	full_word	auto[0]	86861121	1			T1	77420		T2	1169		T3	427329
auto[TlIntgErrNone]	full_word	auto[1]	113233610	1			T1	29803		T2	533		T3	575901
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T111	2		T142	1		T177	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T110	3		T111	2		T112	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T181	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T111	1		T182	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T110	4		T111	3		T112	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T110	2		T111	3		T112	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T110	1		T179	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T111	2		T182	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T110	4		T112	1		T142	5
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T110	6		T111	7		T112	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T182	2		T178	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T184	1		T178	1		T185	1