Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	418190	0	0
entropy_period_rd_A	2147483647	2528	0	0
intr_enable_rd_A	2147483647	3362	0	0
prefix_0_rd_A	2147483647	2473	0	0
prefix_10_rd_A	2147483647	2251	0	0
prefix_1_rd_A	2147483647	2364	0	0
prefix_2_rd_A	2147483647	2192	0	0
prefix_3_rd_A	2147483647	2196	0	0
prefix_4_rd_A	2147483647	2296	0	0
prefix_5_rd_A	2147483647	2525	0	0
prefix_6_rd_A	2147483647	2407	0	0
prefix_7_rd_A	2147483647	2337	0	0
prefix_8_rd_A	2147483647	2348	0	0
prefix_9_rd_A	2147483647	2469	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	418190	0	0
T4	4386	0	0	0
T5	2557	0	0	0
T18	680082	108142	0	0
T25	0	15734	0	0
T29	77416	0	0	0
T37	1433	0	0	0
T38	135463	0	0	0
T39	931052	0	0	0
T49	0	57040	0	0
T80	493369	0	0	0
T81	476787	0	0	0
T82	256732	0	0	0
T110	0	3	0	0
T118	0	34981	0	0
T119	0	107991	0	0
T120	0	11637	0	0
T121	0	30494	0	0
T122	0	31580	0	0
T123	0	18355	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2528	0	0
T25	168090	64	0	0
T104	0	31	0	0
T120	0	32	0	0
T138	0	24	0	0
T139	0	7	0	0
T140	0	95	0	0
T141	0	14	0	0
T142	0	67	0	0
T143	0	96	0	0
T144	0	73	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3362	0	0
T25	168090	42	0	0
T104	0	48	0	0
T117	0	22	0	0
T120	0	39	0	0
T138	0	5	0	0
T139	0	19	0	0
T140	0	233	0	0
T141	0	37	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0
T154	0	8	0	0
T155	0	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T25	168090	50	0	0
T104	0	41	0	0
T120	0	68	0	0
T138	0	38	0	0
T139	0	1	0	0
T140	0	249	0	0
T141	0	34	0	0
T142	0	56	0	0
T143	0	203	0	0
T144	0	55	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2251	0	0
T25	168090	46	0	0
T104	0	42	0	0
T120	0	20	0	0
T138	0	11	0	0
T139	0	7	0	0
T140	0	242	0	0
T141	0	27	0	0
T142	0	33	0	0
T143	0	226	0	0
T144	0	57	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2364	0	0
T25	168090	80	0	0
T104	0	24	0	0
T120	0	57	0	0
T138	0	12	0	0
T139	0	3	0	0
T140	0	211	0	0
T141	0	3	0	0
T142	0	43	0	0
T143	0	225	0	0
T144	0	33	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192	0	0
T25	168090	44	0	0
T104	0	27	0	0
T120	0	26	0	0
T139	0	10	0	0
T140	0	248	0	0
T141	0	42	0	0
T142	0	30	0	0
T143	0	217	0	0
T144	0	41	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0
T156	0	50	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2196	0	0
T25	168090	30	0	0
T104	0	15	0	0
T120	0	23	0	0
T139	0	6	0	0
T140	0	244	0	0
T141	0	19	0	0
T142	0	43	0	0
T143	0	218	0	0
T144	0	37	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0
T156	0	27	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2296	0	0
T25	168090	34	0	0
T104	0	17	0	0
T120	0	25	0	0
T138	0	26	0	0
T139	0	3	0	0
T140	0	219	0	0
T141	0	30	0	0
T142	0	36	0	0
T143	0	226	0	0
T144	0	34	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2525	0	0
T25	168090	67	0	0
T104	0	40	0	0
T120	0	48	0	0
T138	0	20	0	0
T139	0	5	0	0
T140	0	230	0	0
T141	0	28	0	0
T142	0	32	0	0
T143	0	234	0	0
T144	0	44	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2407	0	0
T25	168090	59	0	0
T104	0	29	0	0
T120	0	52	0	0
T138	0	4	0	0
T139	0	11	0	0
T140	0	224	0	0
T141	0	34	0	0
T142	0	47	0	0
T143	0	195	0	0
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T146	486323	0	0	0
T147	177878	0	0	0
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T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2337	0	0
T25	168090	59	0	0
T104	0	16	0	0
T120	0	40	0	0
T138	0	8	0	0
T139	0	4	0	0
T140	0	212	0	0
T141	0	34	0	0
T142	0	36	0	0
T143	0	215	0	0
T144	0	39	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2348	0	0
T25	168090	50	0	0
T104	0	28	0	0
T120	0	48	0	0
T138	0	8	0	0
T139	0	12	0	0
T140	0	243	0	0
T141	0	13	0	0
T142	0	30	0	0
T143	0	202	0	0
T144	0	63	0	0
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T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2469	0	0
T25	168090	32	0	0
T104	0	21	0	0
T120	0	60	0	0
T138	0	29	0	0
T139	0	13	0	0
T140	0	247	0	0
T141	0	30	0	0
T142	0	41	0	0
T143	0	276	0	0
T144	0	50	0	0
T145	751455	0	0	0
T146	486323	0	0	0
T147	177878	0	0	0
T148	904948	0	0	0
T149	609077	0	0	0
T150	2374	0	0	0
T151	111917	0	0	0
T152	920889	0	0	0
T153	466568	0	0	0