Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256162126	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

200920953

1

T1

95083

T2

12

T3

359158

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	241487730	1			T1	101882		T2	1		T3	472589
values[0x0]	103558427	1			T1	22676		T2	13		T3	216933
values[0x1]	112036922	1			T1	24347		T2	9		T3	236797

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199662358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

257420721

1

T1

107217

T2

12

T3

484423

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1359586	1			T1	644		T3	3492		T4	2973
valid_sources[0x01]	1350552	1			T1	525		T2	1		T3	3604
valid_sources[0x02]	3750626	1			T1	519		T3	3991		T4	3020
valid_sources[0x03]	1356610	1			T1	541		T3	3894		T4	2974
valid_sources[0x04]	1353567	1			T1	604		T3	3578		T4	3049
valid_sources[0x05]	1355170	1			T1	595		T3	3523		T4	3003
valid_sources[0x06]	1348127	1			T1	606		T3	2977		T4	3067
valid_sources[0x07]	1353599	1			T1	589		T3	3283		T4	3159
valid_sources[0x08]	1370819	1			T1	665		T3	3550		T4	3038
valid_sources[0x09]	1359369	1			T1	505		T3	3767		T4	2971
valid_sources[0x0a]	1348734	1			T1	590		T3	3365		T4	3029
valid_sources[0x0b]	4459700	1			T1	607		T3	3562		T4	3075
valid_sources[0x0c]	2119422	1			T1	546		T3	3633		T4	3059
valid_sources[0x0d]	1352935	1			T1	560		T3	3760		T4	2991
valid_sources[0x0e]	1357581	1			T1	538		T2	1		T3	3726
valid_sources[0x0f]	1351387	1			T1	539		T3	3688		T4	3079
valid_sources[0x10]	1810553	1			T1	497		T3	4019		T4	3042
valid_sources[0x11]	2189323	1			T1	552		T3	3491		T4	3069
valid_sources[0x12]	1483417	1			T1	542		T3	3452		T4	2990
valid_sources[0x13]	1356642	1			T1	597		T3	3875		T4	3028
valid_sources[0x14]	1357696	1			T1	642		T3	3849		T4	3097
valid_sources[0x15]	2357256	1			T1	581		T3	3230		T4	3004
valid_sources[0x16]	1355035	1			T1	566		T3	3025		T4	3053
valid_sources[0x17]	6169940	1			T1	550		T3	3202		T4	3070
valid_sources[0x18]	1932643	1			T1	538		T3	3450		T4	2970
valid_sources[0x19]	1471305	1			T1	564		T3	4084		T4	3071
valid_sources[0x1a]	1351407	1			T1	583		T3	3542		T4	3011
valid_sources[0x1b]	2096757	1			T1	593		T3	3748		T4	3075
valid_sources[0x1c]	1596912	1			T1	568		T3	3799		T4	2991
valid_sources[0x1d]	1388958	1			T1	563		T3	3450		T4	3114
valid_sources[0x1e]	1355830	1			T1	490		T3	3846		T4	3070
valid_sources[0x1f]	1356827	1			T1	610		T3	3740		T4	3014
valid_sources[0x20]	1346535	1			T1	589		T3	3441		T4	3018
valid_sources[0x21]	1360460	1			T1	633		T3	4278		T4	2887
valid_sources[0x22]	1356726	1			T1	643		T3	3797		T4	3032
valid_sources[0x23]	1358857	1			T1	625		T3	3366		T4	3062
valid_sources[0x24]	1353445	1			T1	590		T3	3500		T4	3132
valid_sources[0x25]	1356890	1			T1	680		T3	3894		T4	2954
valid_sources[0x26]	3488476	1			T1	513		T3	3566		T4	2958
valid_sources[0x27]	1346972	1			T1	598		T3	3398		T4	2959
valid_sources[0x28]	1357147	1			T1	599		T3	3727		T4	3007
valid_sources[0x29]	1353653	1			T1	577		T3	3603		T4	2985
valid_sources[0x2a]	1353919	1			T1	565		T3	4225		T4	2976
valid_sources[0x2b]	1498333	1			T1	519		T3	3874		T4	3098
valid_sources[0x2c]	1531792	1			T1	568		T3	3901		T4	2994
valid_sources[0x2d]	1358452	1			T1	577		T3	4192		T4	2968
valid_sources[0x2e]	1348857	1			T1	586		T3	3417		T4	2946
valid_sources[0x2f]	1349809	1			T1	610		T2	2		T3	3575
valid_sources[0x30]	1381075	1			T1	619		T3	3401		T4	3106
valid_sources[0x31]	1380100	1			T1	579		T3	3780		T4	3076
valid_sources[0x32]	2262629	1			T1	577		T3	3650		T4	3136
valid_sources[0x33]	3565932	1			T1	654		T3	3616		T4	3136
valid_sources[0x34]	1351874	1			T1	556		T3	3376		T4	3070
valid_sources[0x35]	1356523	1			T1	587		T3	3917		T4	3093
valid_sources[0x36]	1356540	1			T1	615		T3	3405		T4	2997
valid_sources[0x37]	1550150	1			T1	539		T3	3469		T4	3032
valid_sources[0x38]	1411991	1			T1	589		T3	3017		T4	3036
valid_sources[0x39]	1383598	1			T1	705		T3	3398		T4	2979
valid_sources[0x3a]	3764112	1			T1	562		T3	2987		T4	3047
valid_sources[0x3b]	3762188	1			T1	625		T3	3718		T4	3073
valid_sources[0x3c]	1347906	1			T1	492		T3	3446		T4	3072
valid_sources[0x3d]	3758149	1			T1	606		T3	3356		T4	3066
valid_sources[0x3e]	4255473	1			T1	589		T3	3246		T4	3110
valid_sources[0x3f]	1379273	1			T1	572		T3	3847		T4	2950
valid_sources[0x40]	3471326	1			T1	606		T3	3739		T4	3099
valid_sources[0x41]	3374907	1			T1	615		T3	3586		T4	3090
valid_sources[0x42]	1348549	1			T1	608		T3	3880		T4	3107
valid_sources[0x43]	2208387	1			T1	675		T3	3237		T4	3100
valid_sources[0x44]	1361329	1			T1	559		T3	3371		T4	3037
valid_sources[0x45]	1357959	1			T1	637		T3	3330		T4	2968
valid_sources[0x46]	1350741	1			T1	607		T3	3325		T4	3015
valid_sources[0x47]	1351222	1			T1	556		T3	3505		T4	3054
valid_sources[0x48]	1353765	1			T1	600		T3	3871		T4	3097
valid_sources[0x49]	1654584	1			T1	539		T3	3408		T4	3039
valid_sources[0x4a]	1350749	1			T1	543		T3	3359		T4	3001
valid_sources[0x4b]	1365677	1			T1	572		T3	3709		T4	3026
valid_sources[0x4c]	1352323	1			T1	555		T3	3828		T4	3106
valid_sources[0x4d]	1355428	1			T1	574		T3	2825		T4	3041
valid_sources[0x4e]	1359305	1			T1	564		T3	3540		T4	3060
valid_sources[0x4f]	1353097	1			T1	622		T3	4116		T4	2989
valid_sources[0x50]	1347074	1			T1	583		T3	3635		T4	3118
valid_sources[0x51]	1351429	1			T1	552		T3	4258		T4	3002
valid_sources[0x52]	1352791	1			T1	596		T3	3452		T4	3085
valid_sources[0x53]	1349780	1			T1	613		T3	3473		T4	2990
valid_sources[0x54]	1645754	1			T1	500		T3	3504		T4	2897
valid_sources[0x55]	1425863	1			T1	538		T3	3764		T4	2943
valid_sources[0x56]	3401268	1			T1	628		T3	4068		T4	3043
valid_sources[0x57]	1355234	1			T1	570		T3	3912		T4	3065
valid_sources[0x58]	4950196	1			T1	545		T3	3466		T4	3061
valid_sources[0x59]	1347343	1			T1	569		T3	4065		T4	2966
valid_sources[0x5a]	3381927	1			T1	605		T3	3713		T4	3111
valid_sources[0x5b]	1362049	1			T1	636		T3	4231		T4	3095
valid_sources[0x5c]	2073517	1			T1	561		T3	3513		T4	3138
valid_sources[0x5d]	1354752	1			T1	657		T3	3202		T4	3126
valid_sources[0x5e]	1358132	1			T1	524		T3	3744		T4	3166
valid_sources[0x5f]	1436497	1			T1	537		T3	3623		T4	3089
valid_sources[0x60]	3776408	1			T1	578		T3	3895		T4	3107
valid_sources[0x61]	1356495	1			T1	586		T3	4002		T4	2976
valid_sources[0x62]	1354956	1			T1	625		T3	3805		T4	2950
valid_sources[0x63]	1353612	1			T1	627		T3	3729		T4	3058
valid_sources[0x64]	1679764	1			T1	602		T3	3561		T4	3098
valid_sources[0x65]	1355930	1			T1	605		T3	3442		T4	3022
valid_sources[0x66]	2006923	1			T1	592		T3	3226		T4	2945
valid_sources[0x67]	1353062	1			T1	594		T3	3365		T4	2998
valid_sources[0x68]	1853047	1			T1	534		T3	3424		T4	2952
valid_sources[0x69]	2065386	1			T1	603		T3	3818		T4	3080
valid_sources[0x6a]	1371679	1			T1	618		T3	4017		T4	3028
valid_sources[0x6b]	1357567	1			T1	573		T3	3197		T4	2979
valid_sources[0x6c]	1673125	1			T1	530		T3	3660		T4	3133
valid_sources[0x6d]	1347764	1			T1	540		T2	2		T3	3333
valid_sources[0x6e]	2084711	1			T1	515		T2	2		T3	3556
valid_sources[0x6f]	1350253	1			T1	548		T2	2		T3	3378
valid_sources[0x70]	1381339	1			T1	599		T3	3792		T4	3152
valid_sources[0x71]	1352465	1			T1	575		T2	1		T3	3285
valid_sources[0x72]	1358479	1			T1	619		T3	3715		T4	3120
valid_sources[0x73]	1350435	1			T1	643		T3	3439		T4	3002
valid_sources[0x74]	1351820	1			T1	590		T3	3219		T4	3000
valid_sources[0x75]	1354920	1			T1	522		T3	3997		T4	3015
valid_sources[0x76]	5025545	1			T1	534		T3	3671		T4	2983
valid_sources[0x77]	1932052	1			T1	564		T3	3266		T4	3099
valid_sources[0x78]	1356912	1			T1	570		T3	3527		T4	3041
valid_sources[0x79]	1358351	1			T1	547		T3	3817		T4	2952
valid_sources[0x7a]	1353712	1			T1	605		T2	1		T3	3812
valid_sources[0x7b]	1372364	1			T1	583		T3	3470		T4	3069
valid_sources[0x7c]	1352747	1			T1	565		T3	3692		T4	2971
valid_sources[0x7d]	5322754	1			T1	552		T3	3809		T4	3152
valid_sources[0x7e]	2885484	1			T1	583		T3	3459		T4	3034
valid_sources[0x7f]	1359685	1			T1	559		T3	3113		T4	3000
valid_sources[0x80]	1353224	1			T1	598		T3	3444		T4	3075

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87882041

1

T1

69119

T2

1

T3

135366

values[0x0]

all_enables

biggest_size

60838537

1

T1

13892

T2

8

T3

121499

values[0x1]

all_enables

biggest_size

52200375

1

T1

12072

T2

3

T3

102293