Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258386707

1

T1

53822

T2

11

T3

567161

full_word

201059896

1

T1

95083

T2

12

T3

359158

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	459446333	1			T1	148905		T2	23		T3	926319
auto[TlIntgErrCmd]	82	1			T108	5		T109	3		T110	4
auto[TlIntgErrData]	85	1			T108	3		T109	2		T110	10
auto[TlIntgErrBoth]	103	1			T108	2		T109	5		T110	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241914711

1

T1

101882

T2

1

T3

472589

auto[1]

217531892

1

T1

47023

T2

22

T3

453730

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153997988	1			T1	32763		T3	337223		T4	272888
auto[TlIntgErrNone]	partial	auto[1]	104388473	1			T1	21059		T2	11		T3	229938
auto[TlIntgErrNone]	full_word	auto[0]	87916599	1			T1	69119		T2	1		T3	135366
auto[TlIntgErrNone]	full_word	auto[1]	113143273	1			T1	25964		T2	11		T3	223792
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T108	2		T109	1		T180	1
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T108	3		T109	2		T110	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T177	1		T181	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T110	1		T183	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T108	1		T110	6		T177	5
auto[TlIntgErrData]	partial	auto[1]	37	1			T108	1		T109	2		T110	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T110	1		T179	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T108	1		T180	1		T178	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T108	1		T109	3		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T108	1		T109	1		T110	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T177	1		T184	1		T185	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T109	1		T184	1		T186	1