Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332579 |
1 |
|
|
T1 |
2240 |
|
T4 |
2032 |
|
T5 |
1259 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
166341 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
126500 |
1 |
|
|
T1 |
2207 |
|
T4 |
1056 |
|
T5 |
185 |
seven_bytes |
5736 |
1 |
|
|
T4 |
26 |
|
T5 |
21 |
|
T27 |
21 |
six_bytes |
5595 |
1 |
|
|
T4 |
24 |
|
T5 |
25 |
|
T27 |
13 |
five_bytes |
5726 |
1 |
|
|
T4 |
21 |
|
T5 |
26 |
|
T27 |
19 |
four_bytes |
5715 |
1 |
|
|
T4 |
30 |
|
T5 |
31 |
|
T27 |
13 |
three_bytes |
5728 |
1 |
|
|
T4 |
25 |
|
T5 |
31 |
|
T27 |
12 |
two_bytes |
5739 |
1 |
|
|
T4 |
22 |
|
T5 |
34 |
|
T27 |
10 |
one_byte |
5499 |
1 |
|
|
T4 |
32 |
|
T5 |
28 |
|
T27 |
13 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
325987 |
1 |
|
|
T1 |
2174 |
|
T4 |
1986 |
|
T5 |
1243 |
auto[1] |
6592 |
1 |
|
|
T1 |
66 |
|
T4 |
46 |
|
T5 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332579 |
1 |
|
|
T1 |
2240 |
|
T4 |
2032 |
|
T5 |
1259 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332555 |
1 |
|
|
T1 |
2240 |
|
T4 |
2031 |
|
T5 |
1259 |
auto[1] |
24 |
1 |
|
|
T4 |
1 |
|
T158 |
1 |
|
T74 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2351 |
1 |
|
|
T1 |
33 |
|
T4 |
20 |
|
T5 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6592 |
1 |
|
|
T1 |
66 |
|
T4 |
46 |
|
T5 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176361 |
1 |
|
|
T1 |
1343 |
|
T4 |
1113 |
|
T5 |
293 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90264 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
64722 |
1 |
|
|
T1 |
1324 |
|
T4 |
373 |
|
T5 |
7 |
seven_bytes |
3133 |
1 |
|
|
T4 |
27 |
|
T5 |
7 |
|
T27 |
18 |
six_bytes |
3061 |
1 |
|
|
T4 |
15 |
|
T5 |
11 |
|
T27 |
17 |
five_bytes |
3026 |
1 |
|
|
T4 |
22 |
|
T5 |
7 |
|
T27 |
18 |
four_bytes |
3116 |
1 |
|
|
T4 |
21 |
|
T5 |
10 |
|
T27 |
18 |
three_bytes |
3023 |
1 |
|
|
T4 |
23 |
|
T5 |
3 |
|
T27 |
18 |
two_bytes |
2938 |
1 |
|
|
T4 |
14 |
|
T5 |
10 |
|
T27 |
16 |
one_byte |
3078 |
1 |
|
|
T4 |
22 |
|
T5 |
11 |
|
T27 |
29 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172993 |
1 |
|
|
T1 |
1305 |
|
T4 |
1093 |
|
T5 |
285 |
auto[1] |
3368 |
1 |
|
|
T1 |
38 |
|
T4 |
20 |
|
T5 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176361 |
1 |
|
|
T1 |
1343 |
|
T4 |
1113 |
|
T5 |
293 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176347 |
1 |
|
|
T1 |
1342 |
|
T4 |
1113 |
|
T5 |
293 |
auto[1] |
14 |
1 |
|
|
T1 |
1 |
|
T105 |
1 |
|
T158 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1192 |
1 |
|
|
T1 |
19 |
|
T4 |
6 |
|
T5 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3368 |
1 |
|
|
T1 |
38 |
|
T4 |
20 |
|
T5 |
8 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176987 |
1 |
|
|
T1 |
779 |
|
T4 |
2128 |
|
T5 |
514 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87486 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
68804 |
1 |
|
|
T1 |
765 |
|
T4 |
480 |
|
T5 |
14 |
seven_bytes |
2971 |
1 |
|
|
T4 |
47 |
|
T5 |
17 |
|
T27 |
20 |
six_bytes |
3047 |
1 |
|
|
T4 |
45 |
|
T5 |
9 |
|
T27 |
14 |
five_bytes |
2958 |
1 |
|
|
T4 |
53 |
|
T5 |
18 |
|
T27 |
14 |
four_bytes |
2944 |
1 |
|
|
T4 |
51 |
|
T5 |
10 |
|
T27 |
12 |
three_bytes |
3002 |
1 |
|
|
T4 |
37 |
|
T5 |
12 |
|
T27 |
14 |
two_bytes |
2899 |
1 |
|
|
T4 |
43 |
|
T5 |
13 |
|
T27 |
18 |
one_byte |
2876 |
1 |
|
|
T4 |
52 |
|
T5 |
16 |
|
T27 |
11 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173525 |
1 |
|
|
T1 |
751 |
|
T4 |
2096 |
|
T5 |
504 |
auto[1] |
3462 |
1 |
|
|
T1 |
28 |
|
T4 |
32 |
|
T5 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176987 |
1 |
|
|
T1 |
779 |
|
T4 |
2128 |
|
T5 |
514 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176971 |
1 |
|
|
T1 |
779 |
|
T4 |
2128 |
|
T5 |
514 |
auto[1] |
16 |
1 |
|
|
T71 |
1 |
|
T72 |
1 |
|
T159 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1227 |
1 |
|
|
T1 |
14 |
|
T4 |
9 |
|
T5 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3462 |
1 |
|
|
T1 |
28 |
|
T4 |
32 |
|
T5 |
10 |