Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254778390

1

T1

53628

T2

78

T3

16

full_word

199375593

1

T1

98260

T2

1080

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454153663	1			T1	151888		T2	1158		T3	22
auto[TlIntgErrCmd]	115	1			T108	6		T109	8		T110	8
auto[TlIntgErrData]	101	1			T108	3		T109	4		T110	6
auto[TlIntgErrBoth]	104	1			T108	11		T109	8		T110	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238325120

1

T1

104640

T2

81

T3

1

auto[1]

215828863

1

T1

47248

T2

1077

T3

21

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151684858	1			T1	32019		T2	36		T4	35381
auto[TlIntgErrNone]	partial	auto[1]	103093234	1			T1	21609		T2	42		T3	16
auto[TlIntgErrNone]	full_word	auto[0]	86640126	1			T1	72621		T2	45		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	112735445	1			T1	25639		T2	1035		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T108	2		T109	3		T110	5
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T108	4		T109	5		T110	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T171	1		T173	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T168	2		T174	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T108	1		T109	2		T110	4
auto[TlIntgErrData]	partial	auto[1]	50	1			T108	2		T109	2		T110	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T172	1		T170	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T173	2		T169	1		T170	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T108	4		T109	2		T110	4
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T108	6		T109	5		T110	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T108	1		T176	1		T168	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T109	1		T172	1		T177	2