Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	96.27	93.33	100.00	92.31	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	570997	0	0
entropy_period_rd_A	2147483647	1622	0	0
intr_enable_rd_A	2147483647	2465	0	0
prefix_0_rd_A	2147483647	1736	0	0
prefix_10_rd_A	2147483647	1698	0	0
prefix_1_rd_A	2147483647	1897	0	0
prefix_2_rd_A	2147483647	1847	0	0
prefix_3_rd_A	2147483647	1623	0	0
prefix_4_rd_A	2147483647	1702	0	0
prefix_5_rd_A	2147483647	1713	0	0
prefix_6_rd_A	2147483647	1755	0	0
prefix_7_rd_A	2147483647	1698	0	0
prefix_8_rd_A	2147483647	1681	0	0
prefix_9_rd_A	2147483647	1788	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	570997	0	0
T5	162322	25309	0	0
T15	124052	0	0	0
T16	7258	0	0	0
T17	427537	0	0	0
T18	257529	0	0	0
T19	474478	0	0	0
T20	20958	0	0	0
T21	24261	0	0	0
T40	1198	0	0	0
T42	0	32934	0	0
T43	0	23109	0	0
T76	173155	0	0	0
T114	0	85499	0	0
T115	0	52643	0	0
T116	0	68539	0	0
T117	0	99326	0	0
T118	0	40566	0	0
T119	0	45235	0	0
T120	0	37382	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1622	0	0
T42	353578	87	0	0
T43	0	53	0	0
T110	0	128	0	0
T118	0	140	0	0
T137	0	67	0	0
T138	0	126	0	0
T139	0	13	0	0
T140	0	12	0	0
T141	0	11	0	0
T142	0	5	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2465	0	0
T42	353578	83	0	0
T43	0	52	0	0
T110	0	216	0	0
T112	0	16	0	0
T118	0	83	0	0
T137	0	70	0	0
T138	0	235	0	0
T139	0	8	0	0
T140	0	12	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0
T152	0	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1736	0	0
T42	353578	116	0	0
T43	0	23	0	0
T110	0	86	0	0
T118	0	86	0	0
T137	0	75	0	0
T138	0	221	0	0
T139	0	5	0	0
T140	0	18	0	0
T141	0	19	0	0
T142	0	7	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1698	0	0
T42	353578	125	0	0
T43	0	31	0	0
T110	0	95	0	0
T118	0	112	0	0
T137	0	74	0	0
T138	0	229	0	0
T139	0	8	0	0
T140	0	7	0	0
T141	0	17	0	0
T142	0	10	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T42	353578	127	0	0
T43	0	51	0	0
T110	0	71	0	0
T118	0	117	0	0
T137	0	104	0	0
T138	0	243	0	0
T139	0	14	0	0
T140	0	10	0	0
T141	0	12	0	0
T142	0	1	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T42	353578	114	0	0
T43	0	76	0	0
T110	0	76	0	0
T118	0	125	0	0
T137	0	65	0	0
T138	0	212	0	0
T140	0	1	0	0
T141	0	15	0	0
T142	0	9	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0
T153	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1623	0	0
T42	353578	91	0	0
T43	0	9	0	0
T110	0	80	0	0
T118	0	74	0	0
T137	0	77	0	0
T138	0	217	0	0
T139	0	8	0	0
T140	0	20	0	0
T141	0	13	0	0
T142	0	4	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1702	0	0
T42	353578	101	0	0
T43	0	39	0	0
T110	0	64	0	0
T118	0	101	0	0
T137	0	85	0	0
T138	0	211	0	0
T139	0	10	0	0
T140	0	2	0	0
T141	0	13	0	0
T142	0	9	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1713	0	0
T42	353578	107	0	0
T43	0	35	0	0
T110	0	83	0	0
T118	0	126	0	0
T137	0	66	0	0
T138	0	203	0	0
T139	0	8	0	0
T140	0	12	0	0
T141	0	14	0	0
T142	0	8	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1755	0	0
T42	353578	116	0	0
T43	0	52	0	0
T110	0	70	0	0
T118	0	118	0	0
T137	0	100	0	0
T138	0	229	0	0
T139	0	3	0	0
T140	0	13	0	0
T141	0	9	0	0
T142	0	4	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
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T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1698	0	0
T42	353578	89	0	0
T43	0	66	0	0
T110	0	76	0	0
T118	0	160	0	0
T137	0	37	0	0
T138	0	188	0	0
T139	0	13	0	0
T140	0	7	0	0
T141	0	15	0	0
T142	0	10	0	0
T143	138152	0	0	0
T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1681	0	0
T42	353578	120	0	0
T43	0	11	0	0
T110	0	61	0	0
T118	0	73	0	0
T137	0	47	0	0
T138	0	241	0	0
T139	0	2	0	0
T140	0	13	0	0
T141	0	3	0	0
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T143	138152	0	0	0
T144	1099	0	0	0
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T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
T151	2173	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1788	0	0
T42	353578	126	0	0
T43	0	50	0	0
T110	0	83	0	0
T118	0	115	0	0
T137	0	96	0	0
T138	0	247	0	0
T139	0	12	0	0
T140	0	14	0	0
T141	0	12	0	0
T142	0	5	0	0
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T144	1099	0	0	0
T145	205344	0	0	0
T146	5997	0	0	0
T147	327527	0	0	0
T148	251664	0	0	0
T149	281207	0	0	0
T150	5662	0	0	0
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