Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258977186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203716381

1

T1

359545

T2

184335

T3

38848

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	244295989	1			T1	461079		T2	233067		T3	40854
values[0x0]	104949018	1			T1	212746		T2	105159		T3	8644
values[0x1]	113448560	1			T1	229473		T2	113791		T3	9196

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201900319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

260793248

1

T1

477497

T2

242344

T3

43374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2399767	1			T1	3488		T2	1756		T3	259
valid_sources[0x01]	1369696	1			T1	3628		T2	1818		T3	245
valid_sources[0x02]	2258349	1			T1	3487		T2	1505		T3	257
valid_sources[0x03]	1410560	1			T1	3588		T2	1723		T3	205
valid_sources[0x04]	2376707	1			T1	3284		T2	1747		T3	215
valid_sources[0x05]	1369325	1			T1	3513		T2	1775		T3	201
valid_sources[0x06]	1365241	1			T1	3481		T2	1719		T3	197
valid_sources[0x07]	1431227	1			T1	3491		T2	1685		T3	271
valid_sources[0x08]	2194886	1			T1	3509		T2	1949		T3	216
valid_sources[0x09]	1368154	1			T1	3536		T2	1913		T3	242
valid_sources[0x0a]	4293114	1			T1	3466		T2	1624		T3	289
valid_sources[0x0b]	1405589	1			T1	3563		T2	1600		T3	246
valid_sources[0x0c]	1370180	1			T1	3384		T2	1729		T3	195
valid_sources[0x0d]	1372786	1			T1	3598		T2	1839		T3	196
valid_sources[0x0e]	1404389	1			T1	3449		T2	1915		T3	240
valid_sources[0x0f]	1375764	1			T1	3413		T2	1912		T3	255
valid_sources[0x10]	1361590	1			T1	3619		T2	1881		T3	215
valid_sources[0x11]	1388840	1			T1	3578		T2	1770		T3	212
valid_sources[0x12]	1369011	1			T1	3553		T2	1738		T3	225
valid_sources[0x13]	1382738	1			T1	3568		T2	1766		T3	196
valid_sources[0x14]	2040558	1			T1	3488		T2	1747		T3	218
valid_sources[0x15]	1363933	1			T1	3506		T2	1764		T3	221
valid_sources[0x16]	1997130	1			T1	3452		T2	1828		T3	240
valid_sources[0x17]	3154867	1			T1	3539		T2	1836		T3	191
valid_sources[0x18]	1553207	1			T1	3485		T2	1561		T3	234
valid_sources[0x19]	1833131	1			T1	3312		T2	1718		T3	230
valid_sources[0x1a]	1825924	1			T1	3537		T2	1744		T3	242
valid_sources[0x1b]	1370765	1			T1	3577		T2	1874		T3	246
valid_sources[0x1c]	1364449	1			T1	3571		T2	1817		T3	216
valid_sources[0x1d]	1518237	1			T1	3562		T2	1749		T3	260
valid_sources[0x1e]	1365982	1			T1	3515		T2	1941		T3	252
valid_sources[0x1f]	1371905	1			T1	3351		T2	1812		T3	254
valid_sources[0x20]	1657844	1			T1	3484		T2	1835		T3	234
valid_sources[0x21]	1370552	1			T1	3641		T2	1776		T3	267
valid_sources[0x22]	2079111	1			T1	3615		T2	1797		T3	239
valid_sources[0x23]	2296070	1			T1	3538		T2	1754		T3	253
valid_sources[0x24]	1362632	1			T1	3538		T2	1837		T3	247
valid_sources[0x25]	1411148	1			T1	3521		T2	1649		T3	198
valid_sources[0x26]	4639673	1			T1	3446		T2	1887		T3	257
valid_sources[0x27]	1396199	1			T1	3456		T2	1610		T3	256
valid_sources[0x28]	1364116	1			T1	3745		T2	1770		T3	264
valid_sources[0x29]	1506164	1			T1	3486		T2	1913		T3	226
valid_sources[0x2a]	1368669	1			T1	3289		T2	1741		T3	224
valid_sources[0x2b]	3446746	1			T1	3807		T2	1936		T3	199
valid_sources[0x2c]	4319273	1			T1	3605		T2	1766		T3	217
valid_sources[0x2d]	2619526	1			T1	3434		T2	1835		T3	223
valid_sources[0x2e]	1364778	1			T1	3644		T2	1579		T3	207
valid_sources[0x2f]	1516025	1			T1	3548		T2	1780		T3	251
valid_sources[0x30]	2451702	1			T1	3604		T2	1711		T3	213
valid_sources[0x31]	1380562	1			T1	3553		T2	1759		T3	241
valid_sources[0x32]	1580862	1			T1	3465		T2	1778		T3	221
valid_sources[0x33]	1372452	1			T1	3571		T2	1647		T3	266
valid_sources[0x34]	1373881	1			T1	3583		T2	1859		T3	281
valid_sources[0x35]	1367964	1			T1	3483		T2	1852		T3	229
valid_sources[0x36]	3568038	1			T1	3483		T2	1823		T3	183
valid_sources[0x37]	1375726	1			T1	3547		T2	1672		T3	265
valid_sources[0x38]	1627273	1			T1	3624		T2	1625		T3	199
valid_sources[0x39]	1375287	1			T1	3448		T2	1911		T3	257
valid_sources[0x3a]	1373996	1			T1	3613		T2	1628		T3	231
valid_sources[0x3b]	3813873	1			T1	3627		T2	1956		T3	237
valid_sources[0x3c]	2075756	1			T1	3452		T2	1823		T3	200
valid_sources[0x3d]	1378617	1			T1	3675		T2	1870		T3	214
valid_sources[0x3e]	1367850	1			T1	3435		T2	1806		T3	233
valid_sources[0x3f]	1365197	1			T1	3662		T2	1946		T3	219
valid_sources[0x40]	1469458	1			T1	3336		T2	1810		T3	246
valid_sources[0x41]	3888417	1			T1	3529		T2	1664		T3	229
valid_sources[0x42]	1377158	1			T1	3549		T2	1974		T3	225
valid_sources[0x43]	1369752	1			T1	3390		T2	1767		T3	232
valid_sources[0x44]	1480906	1			T1	3663		T2	1679		T3	203
valid_sources[0x45]	1383709	1			T1	3592		T2	1588		T3	237
valid_sources[0x46]	1543505	1			T1	3583		T2	1905		T3	276
valid_sources[0x47]	1382417	1			T1	3598		T2	1666		T3	217
valid_sources[0x48]	1368345	1			T1	3633		T2	1817		T3	239
valid_sources[0x49]	1369714	1			T1	3501		T2	1851		T3	238
valid_sources[0x4a]	1379397	1			T1	3441		T2	1877		T3	246
valid_sources[0x4b]	1410939	1			T1	3375		T2	1643		T3	177
valid_sources[0x4c]	2050452	1			T1	3628		T2	1843		T3	194
valid_sources[0x4d]	1368774	1			T1	3485		T2	1742		T3	227
valid_sources[0x4e]	1423449	1			T1	3570		T2	1912		T3	244
valid_sources[0x4f]	1372691	1			T1	3449		T2	1723		T3	240
valid_sources[0x50]	1427550	1			T1	3584		T2	1861		T3	211
valid_sources[0x51]	1366103	1			T1	3756		T2	1713		T3	240
valid_sources[0x52]	1368410	1			T1	3501		T2	1786		T3	244
valid_sources[0x53]	1368806	1			T1	3403		T2	1717		T3	225
valid_sources[0x54]	4207365	1			T1	3585		T2	1809		T3	228
valid_sources[0x55]	1475574	1			T1	3433		T2	1624		T3	228
valid_sources[0x56]	1373470	1			T1	3506		T2	1722		T3	253
valid_sources[0x57]	2952012	1			T1	3567		T2	2008		T3	218
valid_sources[0x58]	1370100	1			T1	3628		T2	1774		T3	237
valid_sources[0x59]	3772204	1			T1	3737		T2	1676		T3	209
valid_sources[0x5a]	2159119	1			T1	3443		T2	1817		T3	242
valid_sources[0x5b]	1477919	1			T1	3567		T2	1718		T3	206
valid_sources[0x5c]	1371662	1			T1	3462		T2	1747		T3	235
valid_sources[0x5d]	1368656	1			T1	3467		T2	1738		T3	234
valid_sources[0x5e]	1362838	1			T1	3645		T2	1814		T3	222
valid_sources[0x5f]	1624760	1			T1	3472		T2	1787		T3	246
valid_sources[0x60]	1433923	1			T1	3758		T2	1727		T3	254
valid_sources[0x61]	1416406	1			T1	3635		T2	1918		T3	260
valid_sources[0x62]	1367246	1			T1	3454		T2	1833		T3	199
valid_sources[0x63]	1422064	1			T1	3672		T2	1728		T3	204
valid_sources[0x64]	1374132	1			T1	3589		T2	1756		T3	247
valid_sources[0x65]	2250027	1			T1	3552		T2	1659		T3	215
valid_sources[0x66]	3415556	1			T1	3435		T2	1725		T3	215
valid_sources[0x67]	2064372	1			T1	3535		T2	1800		T3	264
valid_sources[0x68]	5384668	1			T1	3582		T2	1792		T3	233
valid_sources[0x69]	2414341	1			T1	3483		T2	1593		T3	231
valid_sources[0x6a]	1373093	1			T1	3476		T2	1697		T3	225
valid_sources[0x6b]	2021771	1			T1	3291		T2	1638		T3	232
valid_sources[0x6c]	1368659	1			T1	3421		T2	1709		T3	253
valid_sources[0x6d]	1364885	1			T1	3459		T2	1707		T3	250
valid_sources[0x6e]	2692614	1			T1	3594		T2	1675		T3	209
valid_sources[0x6f]	1374580	1			T1	3619		T2	1772		T3	252
valid_sources[0x70]	1385525	1			T1	3633		T2	1656		T3	227
valid_sources[0x71]	1369431	1			T1	3455		T2	1805		T3	210
valid_sources[0x72]	3824579	1			T1	3528		T2	1723		T3	214
valid_sources[0x73]	1367715	1			T1	3671		T2	1878		T3	219
valid_sources[0x74]	1372435	1			T1	3465		T2	1784		T3	251
valid_sources[0x75]	1374284	1			T1	3510		T2	1801		T3	238
valid_sources[0x76]	1379428	1			T1	3545		T2	1908		T3	257
valid_sources[0x77]	1498157	1			T1	3407		T2	1621		T3	220
valid_sources[0x78]	1422930	1			T1	3491		T2	1855		T3	229
valid_sources[0x79]	2408296	1			T1	3336		T2	1801		T3	198
valid_sources[0x7a]	1365054	1			T1	3626		T2	1764		T3	226
valid_sources[0x7b]	1371617	1			T1	3480		T2	1671		T3	226
valid_sources[0x7c]	1368337	1			T1	3529		T2	1922		T3	224
valid_sources[0x7d]	1376653	1			T1	3613		T2	1718		T3	244
valid_sources[0x7e]	1368904	1			T1	3626		T2	1871		T3	252
valid_sources[0x7f]	2257756	1			T1	3415		T2	1787		T3	189
valid_sources[0x80]	1363957	1			T1	3385		T2	1733		T3	217

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88877450

1

T1

132258

T2

70605

T3

29062

values[0x0]

all_enables

biggest_size

61771761

1

T1

122855

T2

61218

T3

5275

values[0x1]

all_enables

biggest_size

53067170

1

T1

104432

T2

52512

T3

4511