Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259925732

1

T1

543753

T2

267682

T3

19846

full_word

203776728

1

T1

359545

T2

184335

T3

38848

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	463702130	1			T1	903298		T2	452017		T3	58694
auto[TlIntgErrCmd]	115	1			T119	5		T120	8		T121	7
auto[TlIntgErrData]	100	1			T120	6		T121	5		T174	5
auto[TlIntgErrBoth]	115	1			T119	5		T120	6		T121	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244483892

1

T1

461079

T2

233067

T3

40854

auto[1]

219218568

1

T1

442219

T2

218950

T3

17840

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155591013	1			T1	328821		T2	162462		T3	11792
auto[TlIntgErrNone]	partial	auto[1]	104334418	1			T1	214932		T2	105220		T3	8054
auto[TlIntgErrNone]	full_word	auto[0]	88892739	1			T1	132258		T2	70605		T3	29062
auto[TlIntgErrNone]	full_word	auto[1]	114883960	1			T1	227287		T2	113730		T3	9786
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T119	4		T120	3		T121	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T119	1		T120	5		T121	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T179	1		T180	1		T181	2
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T121	1		T174	1		T150	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T120	1		T121	2		T174	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T120	5		T121	2		T174	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T121	1		T178	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T150	1		T183	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T119	3		T120	4		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T119	2		T120	2		T121	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T179	1		T185	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T186	1		T184	1		T182	2