Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	221534	0	0
entropy_period_rd_A	2147483647	1666	0	0
intr_enable_rd_A	2147483647	2039	0	0
prefix_0_rd_A	2147483647	1260	0	0
prefix_10_rd_A	2147483647	1335	0	0
prefix_1_rd_A	2147483647	1256	0	0
prefix_2_rd_A	2147483647	1209	0	0
prefix_3_rd_A	2147483647	1241	0	0
prefix_4_rd_A	2147483647	1327	0	0
prefix_5_rd_A	2147483647	1296	0	0
prefix_6_rd_A	2147483647	1265	0	0
prefix_7_rd_A	2147483647	1138	0	0
prefix_8_rd_A	2147483647	1387	0	0
prefix_9_rd_A	2147483647	1157	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	221534	0	0
T29	325501	0	0	0
T50	310541	45348	0	0
T51	0	49675	0	0
T52	0	44261	0	0
T56	4051	0	0	0
T94	57005	0	0	0
T95	247625	0	0	0
T119	0	1	0	0
T120	0	1	0	0
T125	0	78904	0	0
T126	0	266	0	0
T127	0	70	0	0
T128	0	2	0	0
T129	0	1	0	0
T130	17570	0	0	0
T131	711650	0	0	0
T132	176926	0	0	0
T133	21163	0	0	0
T134	6234	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1666	0	0
T119	13656	60	0	0
T128	4259	4	0	0
T129	4130	4	0	0
T135	8204	20	0	0
T147	2852	14	0	0
T148	1827	3	0	0
T149	10009	47	0	0
T150	22551	152	0	0
T151	20999	64	0	0
T152	1793	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2039	0	0
T119	13656	73	0	0
T128	4259	11	0	0
T129	4130	9	0	0
T135	8204	25	0	0
T147	2852	9	0	0
T148	1827	6	0	0
T149	10009	62	0	0
T150	22551	147	0	0
T151	20999	68	0	0
T153	1273	17	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1260	0	0
T119	13656	44	0	0
T128	4259	10	0	0
T129	4130	5	0	0
T135	8204	17	0	0
T148	1827	1	0	0
T149	10009	39	0	0
T150	22551	79	0	0
T151	20999	36	0	0
T154	3945	7	0	0
T155	20971	42	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1335	0	0
T119	13656	46	0	0
T128	4259	6	0	0
T129	4130	11	0	0
T135	8204	12	0	0
T147	2852	7	0	0
T148	1827	1	0	0
T149	10009	62	0	0
T150	22551	71	0	0
T151	20999	37	0	0
T154	3945	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256	0	0
T119	13656	45	0	0
T128	4259	5	0	0
T129	4130	10	0	0
T135	8204	19	0	0
T147	2852	6	0	0
T148	1827	1	0	0
T149	10009	24	0	0
T150	22551	88	0	0
T151	20999	33	0	0
T154	3945	13	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1209	0	0
T119	13656	49	0	0
T128	4259	10	0	0
T129	4130	10	0	0
T135	8204	7	0	0
T147	2852	7	0	0
T148	1827	2	0	0
T149	10009	35	0	0
T150	22551	79	0	0
T151	20999	40	0	0
T154	3945	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1241	0	0
T119	13656	44	0	0
T128	4259	9	0	0
T135	8204	12	0	0
T147	2852	8	0	0
T149	10009	48	0	0
T150	22551	74	0	0
T151	20999	44	0	0
T152	1793	6	0	0
T154	3945	3	0	0
T155	20971	32	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1327	0	0
T119	13656	51	0	0
T128	4259	5	0	0
T135	8204	10	0	0
T147	2852	9	0	0
T148	1827	3	0	0
T149	10009	62	0	0
T150	22551	113	0	0
T151	20999	36	0	0
T152	1793	8	0	0
T154	3945	11	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1296	0	0
T119	13656	49	0	0
T128	4259	7	0	0
T129	4130	3	0	0
T135	8204	22	0	0
T147	2852	5	0	0
T149	10009	47	0	0
T150	22551	87	0	0
T151	20999	26	0	0
T152	1793	2	0	0
T154	3945	13	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1265	0	0
T119	13656	51	0	0
T128	4259	3	0	0
T129	4130	4	0	0
T135	8204	16	0	0
T147	2852	15	0	0
T149	10009	46	0	0
T150	22551	84	0	0
T151	20999	37	0	0
T154	3945	13	0	0
T155	20971	49	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138	0	0
T119	13656	48	0	0
T128	4259	17	0	0
T129	4130	6	0	0
T135	8204	11	0	0
T147	2852	12	0	0
T149	10009	23	0	0
T150	22551	60	0	0
T151	20999	37	0	0
T154	3945	10	0	0
T155	20971	64	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1387	0	0
T119	13656	42	0	0
T128	4259	9	0	0
T135	8204	19	0	0
T147	2852	7	0	0
T148	1827	7	0	0
T149	10009	57	0	0
T150	22551	75	0	0
T151	20999	48	0	0
T154	3945	11	0	0
T155	20971	49	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1157	0	0
T119	13656	34	0	0
T128	4259	2	0	0
T129	4130	8	0	0
T135	8204	17	0	0
T147	2852	13	0	0
T149	10009	25	0	0
T150	22551	63	0	0
T151	20999	42	0	0
T152	1793	3	0	0
T154	3945	6	0	0