Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257349179

1

T1

434248

T2

12249

T3

327

full_word

203053638

1

T1

319715

T2

175879

T3

9548

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	460402507	1			T1	753963		T2	188128		T3	9875
auto[TlIntgErrCmd]	107	1			T114	2		T115	8		T116	7
auto[TlIntgErrData]	94	1			T114	3		T115	8		T116	4
auto[TlIntgErrBoth]	109	1			T114	5		T115	4		T116	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241702631

1

T1

399496

T2

51597

T3

8297

auto[1]

218700186

1

T1

354467

T2

136531

T3

1578

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153844373	1			T1	263139		T2	10264		T3	149
auto[TlIntgErrNone]	partial	auto[1]	103504520	1			T1	171109		T2	1985		T3	178
auto[TlIntgErrNone]	full_word	auto[0]	87858110	1			T1	136357		T2	41333		T3	8148
auto[TlIntgErrNone]	full_word	auto[1]	115195504	1			T1	183358		T2	134546		T3	1400
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T114	2		T115	4		T116	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T115	3		T116	4		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T115	1		T116	1		T168	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T114	1		T115	4		T116	4
auto[TlIntgErrData]	partial	auto[1]	37	1			T114	2		T115	4		T167	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T169	1		T170	1		T171	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T172	1		T173	2		T174	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T114	4		T115	3		T116	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T114	1		T115	1		T116	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T116	1		T168	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T175	1		T171	1		T172	2